Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 2 | /* |
Simon Glass | 2f0c2f0 | 2019-09-25 08:56:38 -0600 | [diff] [blame] | 3 | * Common code for Intel CPUs |
| 4 | * |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 5 | * Copyright (c) 2016 Google, Inc |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_CPU_COMMON_H |
| 9 | #define __ASM_CPU_COMMON_H |
| 10 | |
Simon Glass | 55a6b13 | 2019-09-25 08:56:37 -0600 | [diff] [blame] | 11 | /* Standard Intel bus clock is fixed at 100MHz */ |
| 12 | enum { |
| 13 | INTEL_BCLK_MHZ = 100 |
| 14 | }; |
| 15 | |
Simon Glass | d3abc5d | 2019-09-25 08:11:35 -0600 | [diff] [blame] | 16 | struct cpu_info; |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 17 | struct udevice; |
Simon Glass | d3abc5d | 2019-09-25 08:11:35 -0600 | [diff] [blame] | 18 | |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 19 | /** |
| 20 | * cpu_common_init() - Set up common CPU init |
| 21 | * |
| 22 | * This reports BIST failure, enables the LAPIC, updates microcode, enables |
| 23 | * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA. |
| 24 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 25 | * Return: 0 if OK, -ve on error |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 26 | */ |
| 27 | int cpu_common_init(void); |
| 28 | |
| 29 | /** |
| 30 | * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate |
| 31 | * |
| 32 | * If a change is needed, this function will do a soft reset so it takes |
| 33 | * effect. |
| 34 | * |
| 35 | * Some details are available here: |
| 36 | * http://forum.hwbot.org/showthread.php?t=76092 |
| 37 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 38 | * Return: 0 if OK, -ve on error |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 39 | */ |
| 40 | int cpu_set_flex_ratio_to_tdp_nominal(void); |
| 41 | |
Simon Glass | d3abc5d | 2019-09-25 08:11:35 -0600 | [diff] [blame] | 42 | /** |
| 43 | * cpu_intel_get_info() - Obtain CPU info for Intel CPUs |
| 44 | * |
| 45 | * Most Intel CPUs use the same MSR to obtain the clock speed, and use the same |
| 46 | * features. This function fills in these values, given the value of the base |
| 47 | * clock in MHz (typically this should be set to 100). |
| 48 | * |
| 49 | * @info: cpu_info struct to fill in |
| 50 | * @bclk_mz: the base clock in MHz |
| 51 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 52 | * Return: 0 always |
Simon Glass | d3abc5d | 2019-09-25 08:11:35 -0600 | [diff] [blame] | 53 | */ |
| 54 | int cpu_intel_get_info(struct cpu_info *info, int bclk_mz); |
| 55 | |
Simon Glass | 246ac08 | 2019-09-25 08:56:36 -0600 | [diff] [blame] | 56 | /** |
| 57 | * cpu_configure_thermal_target() - Set the thermal target for a CPU |
| 58 | * |
| 59 | * This looks up the tcc-offset property and uses it to set the |
| 60 | * MSR_TEMPERATURE_TARGET value. |
| 61 | * |
| 62 | * @dev: CPU device |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 63 | * Return: 0 if OK, -ENOENT if no target is given in device tree |
Simon Glass | 246ac08 | 2019-09-25 08:56:36 -0600 | [diff] [blame] | 64 | */ |
| 65 | int cpu_configure_thermal_target(struct udevice *dev); |
| 66 | |
Simon Glass | 2f0c2f0 | 2019-09-25 08:56:38 -0600 | [diff] [blame] | 67 | /** |
| 68 | * cpu_set_perf_control() - Set the nominal CPU clock speed |
| 69 | * |
| 70 | * This sets the clock speed as a multiplier of BCLK |
| 71 | * |
| 72 | * @clk_ratio: Ratio to use |
| 73 | */ |
| 74 | void cpu_set_perf_control(uint clk_ratio); |
| 75 | |
| 76 | /** |
| 77 | * cpu_config_tdp_levels() - Check for configurable TDP option |
| 78 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 79 | * Return: true if the CPU has configurable TDP (Thermal-design power) |
Simon Glass | 2f0c2f0 | 2019-09-25 08:56:38 -0600 | [diff] [blame] | 80 | */ |
| 81 | bool cpu_config_tdp_levels(void); |
| 82 | |
Simon Glass | a275209 | 2019-09-25 08:56:40 -0600 | [diff] [blame] | 83 | /** enum burst_mode_t - Burst-mode states */ |
| 84 | enum burst_mode_t { |
| 85 | BURST_MODE_UNKNOWN, |
| 86 | BURST_MODE_UNAVAILABLE, |
| 87 | BURST_MODE_DISABLED, |
| 88 | BURST_MODE_ENABLED |
| 89 | }; |
| 90 | |
| 91 | /* |
| 92 | * cpu_get_burst_mode_state() - Get the Burst/Turbo Mode State |
| 93 | * |
| 94 | * This reads MSR IA32_MISC_ENABLE 0x1A0 |
| 95 | * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED. |
| 96 | * Also checks cpuid 0x6 to see whether burst mode is supported. |
| 97 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 98 | * Return: current burst mode status |
Simon Glass | a275209 | 2019-09-25 08:56:40 -0600 | [diff] [blame] | 99 | */ |
| 100 | enum burst_mode_t cpu_get_burst_mode_state(void); |
| 101 | |
| 102 | /** |
| 103 | * cpu_set_burst_mode() - Set CPU burst mode |
| 104 | * |
| 105 | * @burst_mode: true to enable burst mode, false to disable |
| 106 | */ |
| 107 | void cpu_set_burst_mode(bool burst_mode); |
| 108 | |
| 109 | /** |
| 110 | * cpu_set_eist() - Enable Enhanced Intel Speed Step Technology |
| 111 | * |
| 112 | * @eist_status: true to enable EIST, false to disable |
| 113 | */ |
| 114 | void cpu_set_eist(bool eist_status); |
| 115 | |
| 116 | /** |
| 117 | * cpu_set_p_state_to_turbo_ratio() - Set turbo ratio |
| 118 | * |
| 119 | * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the |
| 120 | * factory configured values for of 1-core, 2-core, 3-core |
| 121 | * and 4-core turbo ratio limits for all processors. |
| 122 | * |
| 123 | * 7:0 - MAX_TURBO_1_CORE |
| 124 | * 15:8 - MAX_TURBO_2_CORES |
| 125 | * 23:16 - MAX_TURBO_3_CORES |
| 126 | * 31:24 - MAX_TURBO_4_CORES |
| 127 | * |
| 128 | * Set PERF_CTL MSR (0x199) P_Req with that value. |
| 129 | */ |
| 130 | void cpu_set_p_state_to_turbo_ratio(void); |
| 131 | |
Simon Glass | 6c0da2d | 2020-09-22 12:45:08 -0600 | [diff] [blame] | 132 | /** |
| 133 | * cpu_get_coord_type() - Get the type of coordination for P-State transition |
| 134 | * |
| 135 | * See ACPI spec v6.3 section 8.4.6.5 _PSD (P-State Dependency) |
| 136 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 137 | * Return: HW_ALL (always) |
Simon Glass | 6c0da2d | 2020-09-22 12:45:08 -0600 | [diff] [blame] | 138 | */ |
| 139 | int cpu_get_coord_type(void); |
| 140 | |
| 141 | /** |
| 142 | * cpu_get_min_ratio() - get minimum support frequency ratio for CPU |
| 143 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 144 | * Return: minimum ratio |
Simon Glass | 6c0da2d | 2020-09-22 12:45:08 -0600 | [diff] [blame] | 145 | */ |
| 146 | int cpu_get_min_ratio(void); |
| 147 | |
| 148 | /** |
| 149 | * cpu_get_max_ratio() - get nominal TDP ration or max non-turbo ratio |
| 150 | * |
| 151 | * If a nominal TDP ratio is available, it is returned. Otherwise this returns |
| 152 | * the maximum non-turbo frequency ratio for this processor |
| 153 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 154 | * Return: max ratio |
Simon Glass | 6c0da2d | 2020-09-22 12:45:08 -0600 | [diff] [blame] | 155 | */ |
| 156 | int cpu_get_max_ratio(void); |
| 157 | |
| 158 | /** |
| 159 | * cpu_get_bus_clock_khz() - Get the bus clock frequency in KHz |
| 160 | * |
| 161 | * This is the value the clock ratio is multiplied with |
| 162 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 163 | * Return: bus-block frequency in KHz |
Simon Glass | 6c0da2d | 2020-09-22 12:45:08 -0600 | [diff] [blame] | 164 | */ |
| 165 | int cpu_get_bus_clock_khz(void); |
| 166 | |
| 167 | /** |
| 168 | * cpu_get_power_max() - Get maximum CPU TDP |
| 169 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 170 | * Return: maximum CPU TDP (Thermal-design power) in mW |
Simon Glass | 6c0da2d | 2020-09-22 12:45:08 -0600 | [diff] [blame] | 171 | */ |
| 172 | int cpu_get_power_max(void); |
| 173 | |
| 174 | /** |
| 175 | * cpu_get_max_turbo_ratio() - Get maximum turbo ratio |
| 176 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 177 | * Return: maximum ratio |
Simon Glass | 6c0da2d | 2020-09-22 12:45:08 -0600 | [diff] [blame] | 178 | */ |
| 179 | int cpu_get_max_turbo_ratio(void); |
| 180 | |
Simon Glass | 9b3e6d4 | 2020-09-22 12:45:14 -0600 | [diff] [blame] | 181 | /** |
| 182 | * cpu_get_cores_per_package() - Get the number of CPU cores in each package |
| 183 | * |
Heinrich Schuchardt | 185f812 | 2022-01-19 18:05:50 +0100 | [diff] [blame^] | 184 | * Return: number of cores |
Simon Glass | 9b3e6d4 | 2020-09-22 12:45:14 -0600 | [diff] [blame] | 185 | */ |
| 186 | int cpu_get_cores_per_package(void); |
| 187 | |
Simon Glass | 6571d87 | 2020-11-04 09:57:15 -0700 | [diff] [blame] | 188 | /** |
| 189 | * cpu_mca_configure() - Set up machine-check exceptions ready for use |
| 190 | * |
| 191 | * These allow the SoC to report errors while running. See here for details: |
| 192 | * |
| 193 | * https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/machine-check-exceptions-debug-paper.pdf |
| 194 | */ |
| 195 | void cpu_mca_configure(void); |
| 196 | |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 197 | #endif |