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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2001
3 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
4 *
5 * Based on code by:
6 *
wdenkdb2f721f2003-03-06 00:58:30 +00007 * Kenneth Johansson ,Ericsson AB.
8 * kenneth.johansson@etx.ericsson.se
wdenkfe8c2802002-11-03 00:38:21 +00009 *
10 * hacked up by bill hunter. fixed so we could run before
11 * serial_init and console_init. previous version avoided this by
12 * running out of cache memory during serial/console init, then running
13 * this code later.
14 *
15 * (C) Copyright 2002
16 * Jun Gu, Artesyn Technology, jung@artesyncp.com
17 * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
18 *
Stefan Roesec157d8e2005-08-01 16:41:48 +020019 * (C) Copyright 2005
20 * Stefan Roese, DENX Software Engineering, sr@denx.de.
21 *
wdenkfe8c2802002-11-03 00:38:21 +000022 * See file CREDITS for list of people who contributed to this
23 * project.
24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License as
27 * published by the Free Software Foundation; either version 2 of
28 * the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 * MA 02111-1307 USA
39 */
40
41#include <common.h>
42#include <asm/processor.h>
43#include <i2c.h>
44#include <ppc4xx.h>
45
46#ifdef CONFIG_SPD_EEPROM
47
48/*
49 * Set default values
50 */
51#ifndef CFG_I2C_SPEED
52#define CFG_I2C_SPEED 50000
53#endif
54
55#ifndef CFG_I2C_SLAVE
56#define CFG_I2C_SLAVE 0xFE
57#endif
58
Stefan Roesec157d8e2005-08-01 16:41:48 +020059#define ONE_BILLION 1000000000
60
61#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */
wdenkfe8c2802002-11-03 00:38:21 +000062
63#define SDRAM0_CFG_DCE 0x80000000
64#define SDRAM0_CFG_SRE 0x40000000
65#define SDRAM0_CFG_PME 0x20000000
66#define SDRAM0_CFG_MEMCHK 0x10000000
67#define SDRAM0_CFG_REGEN 0x08000000
68#define SDRAM0_CFG_ECCDD 0x00400000
69#define SDRAM0_CFG_EMDULR 0x00200000
70#define SDRAM0_CFG_DRW_SHIFT (31-6)
71#define SDRAM0_CFG_BRPF_SHIFT (31-8)
72
73#define SDRAM0_TR_CASL_SHIFT (31-8)
74#define SDRAM0_TR_PTA_SHIFT (31-13)
75#define SDRAM0_TR_CTP_SHIFT (31-15)
76#define SDRAM0_TR_LDF_SHIFT (31-17)
77#define SDRAM0_TR_RFTA_SHIFT (31-29)
78#define SDRAM0_TR_RCD_SHIFT (31-31)
79
80#define SDRAM0_RTR_SHIFT (31-15)
81#define SDRAM0_ECCCFG_SHIFT (31-11)
82
83/* SDRAM0_CFG enable macro */
84#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
85
86#define SDRAM0_BXCR_SZ_MASK 0x000e0000
87#define SDRAM0_BXCR_AM_MASK 0x0000e000
88
89#define SDRAM0_BXCR_SZ_SHIFT (31-14)
90#define SDRAM0_BXCR_AM_SHIFT (31-18)
91
92#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
93#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
94
wdenkdb2f721f2003-03-06 00:58:30 +000095#ifdef CONFIG_SPDDRAM_SILENT
wdenkfe8c2802002-11-03 00:38:21 +000096# define SPD_ERR(x) do { return 0; } while (0)
97#else
wdenkdb2f721f2003-03-06 00:58:30 +000098# define SPD_ERR(x) do { printf(x); return(0); } while (0)
wdenkfe8c2802002-11-03 00:38:21 +000099#endif
100
wdenkfe8c2802002-11-03 00:38:21 +0000101#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
102
103/* function prototypes */
wdenkdb2f721f2003-03-06 00:58:30 +0000104int spd_read(uint addr);
wdenkfe8c2802002-11-03 00:38:21 +0000105
106
107/*
108 * This function is reading data from the DIMM module EEPROM over the SPD bus
109 * and uses that to program the sdram controller.
110 *
111 * This works on boards that has the same schematics that the IBM walnut has.
112 *
wdenkdb2f721f2003-03-06 00:58:30 +0000113 * Input: null for default I2C spd functions or a pointer to a custom function
114 * returning spd_data.
wdenkfe8c2802002-11-03 00:38:21 +0000115 */
116
wdenkdb2f721f2003-03-06 00:58:30 +0000117long int spd_sdram(int(read_spd)(uint addr))
wdenkfe8c2802002-11-03 00:38:21 +0000118{
Stefan Roesec157d8e2005-08-01 16:41:48 +0200119 int tmp,row,col;
wdenkfe8c2802002-11-03 00:38:21 +0000120 int total_size,bank_size,bank_code;
121 int ecc_on;
wdenkdb2f721f2003-03-06 00:58:30 +0000122 int mode;
123 int bank_cnt;
wdenkfe8c2802002-11-03 00:38:21 +0000124
125 int sdram0_pmit=0x07c00000;
stroeseb867d702003-05-23 11:18:02 +0000126#ifndef CONFIG_405EP /* not on PPC405EP */
wdenkfe8c2802002-11-03 00:38:21 +0000127 int sdram0_besr0=-1;
128 int sdram0_besr1=-1;
129 int sdram0_eccesr=-1;
stroeseb867d702003-05-23 11:18:02 +0000130#endif
wdenkfe8c2802002-11-03 00:38:21 +0000131 int sdram0_ecccfg;
132
133 int sdram0_rtr=0;
134 int sdram0_tr=0;
135
136 int sdram0_b0cr;
137 int sdram0_b1cr;
138 int sdram0_b2cr;
139 int sdram0_b3cr;
140
141 int sdram0_cfg=0;
142
143 int t_rp;
144 int t_rcd;
wdenkdb2f721f2003-03-06 00:58:30 +0000145 int t_ras;
146 int t_rc;
147 int min_cas;
wdenkfe8c2802002-11-03 00:38:21 +0000148
Stefan Roesec157d8e2005-08-01 16:41:48 +0200149 PPC405_SYS_INFO sys_info;
150 unsigned long bus_period_x_10;
151
wdenkfe8c2802002-11-03 00:38:21 +0000152 /*
Stefan Roesec157d8e2005-08-01 16:41:48 +0200153 * get the board info
wdenkfe8c2802002-11-03 00:38:21 +0000154 */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200155 get_sys_info(&sys_info);
156 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
157
158 if (read_spd == 0){
159 read_spd=spd_read;
160 /*
161 * Make sure I2C controller is initialized
162 * before continuing.
163 */
wdenkdb2f721f2003-03-06 00:58:30 +0000164 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
165 }
166
Stefan Roesec157d8e2005-08-01 16:41:48 +0200167 /* Make shure we are using SDRAM */
168 if (read_spd(2) != 0x04) {
169 SPD_ERR("SDRAM - non SDRAM memory module found\n");
170 }
171
172 /* ------------------------------------------------------------------
173 * configure memory timing register
174 *
175 * data from DIMM:
176 * 27 IN Row Precharge Time ( t RP)
177 * 29 MIN RAS to CAS Delay ( t RCD)
178 * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
179 * -------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000180
181 /*
Stefan Roesec157d8e2005-08-01 16:41:48 +0200182 * first figure out which cas latency mode to use
183 * use the min supported mode
wdenkfe8c2802002-11-03 00:38:21 +0000184 */
wdenkfe8c2802002-11-03 00:38:21 +0000185
wdenkdb2f721f2003-03-06 00:58:30 +0000186 tmp = read_spd(127) & 0x6;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200187 if (tmp == 0x02){ /* only cas = 2 supported */
188 min_cas = 2;
wdenkdb2f721f2003-03-06 00:58:30 +0000189/* t_ck = read_spd(9); */
190/* t_ac = read_spd(10); */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200191 } else if (tmp == 0x04) { /* only cas = 3 supported */
192 min_cas = 3;
wdenkdb2f721f2003-03-06 00:58:30 +0000193/* t_ck = read_spd(9); */
194/* t_ac = read_spd(10); */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200195 } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
196 min_cas = 2;
wdenkdb2f721f2003-03-06 00:58:30 +0000197/* t_ck = read_spd(23); */
198/* t_ac = read_spd(24); */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200199 } else {
200 SPD_ERR("SDRAM - unsupported CAS latency \n");
wdenkfe8c2802002-11-03 00:38:21 +0000201 }
202
Stefan Roesec157d8e2005-08-01 16:41:48 +0200203 /* get some timing values, t_rp,t_rcd,t_ras,t_rc
204 */
205 t_rp = read_spd(27);
206 t_rcd = read_spd(29);
207 t_ras = read_spd(30);
208 t_rc = t_ras + t_rp;
wdenkfe8c2802002-11-03 00:38:21 +0000209
Stefan Roesec157d8e2005-08-01 16:41:48 +0200210 /* The following timing calcs subtract 1 before deviding.
211 * this has effect of using ceiling instead of floor rounding,
212 * and also subtracting 1 to convert number to reg value
213 */
214 /* set up CASL */
215 sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
216 /* set up PTA */
217 sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
218 /* set up CTP */
219 tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
220 if (tmp < 1)
221 tmp = 1;
222 sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
223 /* set LDF = 2 cycles, reg value = 1 */
224 sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
225 /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
226 tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
227 if (tmp < 0)
228 tmp = 0;
229 if (tmp > 6)
230 tmp = 6;
wdenkfe8c2802002-11-03 00:38:21 +0000231 sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200232 /* set RCD = t_rcd/bus_period*/
233 sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
wdenkfe8c2802002-11-03 00:38:21 +0000234
235
Stefan Roesec157d8e2005-08-01 16:41:48 +0200236 /*------------------------------------------------------------------
237 * configure RTR register
238 * -------------------------------------------------------------------*/
239 row = read_spd(3);
240 col = read_spd(4);
241 tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
242 switch (tmp) {
wdenkfe8c2802002-11-03 00:38:21 +0000243 case 0x00:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200244 tmp = 15625;
245 break;
wdenkfe8c2802002-11-03 00:38:21 +0000246 case 0x01:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200247 tmp = 15625 / 4;
248 break;
wdenkfe8c2802002-11-03 00:38:21 +0000249 case 0x02:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200250 tmp = 15625 / 2;
251 break;
wdenkfe8c2802002-11-03 00:38:21 +0000252 case 0x03:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200253 tmp = 15625 * 2;
254 break;
wdenkfe8c2802002-11-03 00:38:21 +0000255 case 0x04:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200256 tmp = 15625 * 4;
257 break;
wdenkfe8c2802002-11-03 00:38:21 +0000258 case 0x05:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200259 tmp = 15625 * 8;
260 break;
wdenkfe8c2802002-11-03 00:38:21 +0000261 default:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200262 SPD_ERR("SDRAM - Bad refresh period \n");
wdenkfe8c2802002-11-03 00:38:21 +0000263 }
264 /* convert from nsec to bus cycles */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200265 tmp = (tmp * 10) / bus_period_x_10;
266 sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
wdenkfe8c2802002-11-03 00:38:21 +0000267
Stefan Roesec157d8e2005-08-01 16:41:48 +0200268 /*------------------------------------------------------------------
269 * determine the number of banks used
270 * -------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000271 /* byte 7:6 is module data width */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200272 if (read_spd(7) != 0)
273 SPD_ERR("SDRAM - unsupported module width\n");
wdenkdb2f721f2003-03-06 00:58:30 +0000274 tmp = read_spd(6);
wdenkfe8c2802002-11-03 00:38:21 +0000275 if (tmp < 32)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200276 SPD_ERR("SDRAM - unsupported module width\n");
wdenkfe8c2802002-11-03 00:38:21 +0000277 else if (tmp < 64)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200278 bank_cnt = 1; /* one bank per sdram side */
wdenkfe8c2802002-11-03 00:38:21 +0000279 else if (tmp < 73)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200280 bank_cnt = 2; /* need two banks per side */
wdenkfe8c2802002-11-03 00:38:21 +0000281 else if (tmp < 161)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200282 bank_cnt = 4; /* need four banks per side */
wdenkfe8c2802002-11-03 00:38:21 +0000283 else
Stefan Roesec157d8e2005-08-01 16:41:48 +0200284 SPD_ERR("SDRAM - unsupported module width\n");
wdenkfe8c2802002-11-03 00:38:21 +0000285
286 /* byte 5 is the module row count (refered to as dimm "sides") */
wdenkdb2f721f2003-03-06 00:58:30 +0000287 tmp = read_spd(5);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200288 if (tmp == 1)
289 ;
290 else if (tmp==2)
291 bank_cnt *= 2;
292 else if (tmp==4)
293 bank_cnt *= 4;
294 else
295 bank_cnt = 8; /* 8 is an error code */
wdenkfe8c2802002-11-03 00:38:21 +0000296
Stefan Roesec157d8e2005-08-01 16:41:48 +0200297 if (bank_cnt > 4) /* we only have 4 banks to work with */
298 SPD_ERR("SDRAM - unsupported module rows for this width\n");
wdenkfe8c2802002-11-03 00:38:21 +0000299
300 /* now check for ECC ability of module. We only support ECC
301 * on 32 bit wide devices with 8 bit ECC.
302 */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200303 if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
304 sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
305 ecc_on = 1;
306 } else {
307 sdram0_ecccfg = 0;
308 ecc_on = 0;
wdenk8bde7f72003-06-27 21:31:46 +0000309 }
wdenkfe8c2802002-11-03 00:38:21 +0000310
Stefan Roesec157d8e2005-08-01 16:41:48 +0200311 /*------------------------------------------------------------------
312 * calculate total size
313 * -------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000314 /* calculate total size and do sanity check */
wdenkdb2f721f2003-03-06 00:58:30 +0000315 tmp = read_spd(31);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200316 total_size = 1 << 22; /* total_size = 4MB */
wdenkdb2f721f2003-03-06 00:58:30 +0000317 /* now multiply 4M by the smallest device row density */
wdenkfe8c2802002-11-03 00:38:21 +0000318 /* note that we don't support asymetric rows */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200319 while (((tmp & 0x0001) == 0) && (tmp != 0)) {
320 total_size = total_size << 1;
321 tmp = tmp >> 1;
322 }
wdenkdb2f721f2003-03-06 00:58:30 +0000323 total_size *= read_spd(5); /* mult by module rows (dimm sides) */
wdenkfe8c2802002-11-03 00:38:21 +0000324
Stefan Roesec157d8e2005-08-01 16:41:48 +0200325 /*------------------------------------------------------------------
326 * map rows * cols * banks to a mode
327 * -------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000328
Stefan Roesec157d8e2005-08-01 16:41:48 +0200329 switch (row) {
wdenkfe8c2802002-11-03 00:38:21 +0000330 case 11:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200331 switch (col) {
wdenkfe8c2802002-11-03 00:38:21 +0000332 case 8:
333 mode=4; /* mode 5 */
334 break;
335 case 9:
336 case 10:
337 mode=0; /* mode 1 */
338 break;
339 default:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200340 SPD_ERR("SDRAM - unsupported mode\n");
wdenkfe8c2802002-11-03 00:38:21 +0000341 }
342 break;
343 case 12:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200344 switch (col) {
wdenkfe8c2802002-11-03 00:38:21 +0000345 case 8:
346 mode=3; /* mode 4 */
347 break;
348 case 9:
349 case 10:
350 mode=1; /* mode 2 */
351 break;
352 default:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200353 SPD_ERR("SDRAM - unsupported mode\n");
wdenkfe8c2802002-11-03 00:38:21 +0000354 }
355 break;
356 case 13:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200357 switch (col) {
wdenkfe8c2802002-11-03 00:38:21 +0000358 case 8:
359 mode=5; /* mode 6 */
360 break;
361 case 9:
362 case 10:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200363 if (read_spd(17) == 2)
364 mode = 6; /* mode 7 */
wdenkfe8c2802002-11-03 00:38:21 +0000365 else
Stefan Roesec157d8e2005-08-01 16:41:48 +0200366 mode = 2; /* mode 3 */
wdenkfe8c2802002-11-03 00:38:21 +0000367 break;
368 case 11:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200369 mode = 2; /* mode 3 */
wdenkfe8c2802002-11-03 00:38:21 +0000370 break;
371 default:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200372 SPD_ERR("SDRAM - unsupported mode\n");
wdenkfe8c2802002-11-03 00:38:21 +0000373 }
374 break;
375 default:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200376 SPD_ERR("SDRAM - unsupported mode\n");
wdenkfe8c2802002-11-03 00:38:21 +0000377 }
378
Stefan Roesec157d8e2005-08-01 16:41:48 +0200379 /*------------------------------------------------------------------
380 * using the calculated values, compute the bank
381 * config register values.
382 * -------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000383 sdram0_b1cr = 0;
384 sdram0_b2cr = 0;
385 sdram0_b3cr = 0;
386
387 /* compute the size of each bank */
388 bank_size = total_size / bank_cnt;
389 /* convert bank size to bank size code for ppc4xx
Stefan Roesec157d8e2005-08-01 16:41:48 +0200390 by takeing log2(bank_size) - 22 */
391 tmp = bank_size; /* start with tmp = bank_size */
392 bank_code = 0; /* and bank_code = 0 */
393 while (tmp > 1) { /* this takes log2 of tmp */
wdenkfe8c2802002-11-03 00:38:21 +0000394 bank_code++; /* and stores result in bank_code */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200395 tmp = tmp >> 1;
396 } /* bank_code is now log2(bank_size) */
397 bank_code -= 22; /* subtract 22 to get the code */
wdenkfe8c2802002-11-03 00:38:21 +0000398
399 tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200400 sdram0_b0cr = (bank_size * 0) | tmp;
stroese939403b2003-12-09 14:56:24 +0000401#ifndef CONFIG_405EP /* not on PPC405EP */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200402 if (bank_cnt > 1)
403 sdram0_b2cr = (bank_size * 1) | tmp;
404 if (bank_cnt > 2)
405 sdram0_b1cr = (bank_size * 2) | tmp;
406 if (bank_cnt > 3)
407 sdram0_b3cr = (bank_size * 3) | tmp;
stroese939403b2003-12-09 14:56:24 +0000408#else
409 /* PPC405EP chip only supports two SDRAM banks */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200410 if (bank_cnt > 1)
411 sdram0_b1cr = (bank_size * 1) | tmp;
412 if (bank_cnt > 2)
413 total_size = 2 * bank_size;
stroese939403b2003-12-09 14:56:24 +0000414#endif
wdenkfe8c2802002-11-03 00:38:21 +0000415
wdenkfe8c2802002-11-03 00:38:21 +0000416 /*
417 * enable sdram controller DCE=1
418 * enable burst read prefetch to 32 bytes BRPF=2
419 * leave other functions off
420 */
421
Stefan Roesec157d8e2005-08-01 16:41:48 +0200422 /*------------------------------------------------------------------
423 * now that we've done our calculations, we are ready to
424 * program all the registers.
425 * -------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000426
427#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
428 /* disable memcontroller so updates work */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200429 mtsdram0( mem_mcopt1, 0 );
wdenkfe8c2802002-11-03 00:38:21 +0000430
stroeseb867d702003-05-23 11:18:02 +0000431#ifndef CONFIG_405EP /* not on PPC405EP */
wdenkfe8c2802002-11-03 00:38:21 +0000432 mtsdram0( mem_besra , sdram0_besr0 );
433 mtsdram0( mem_besrb , sdram0_besr1 );
stroeseb867d702003-05-23 11:18:02 +0000434 mtsdram0( mem_ecccf , sdram0_ecccfg );
435 mtsdram0( mem_eccerr, sdram0_eccesr );
436#endif
wdenkfe8c2802002-11-03 00:38:21 +0000437 mtsdram0( mem_rtr , sdram0_rtr );
438 mtsdram0( mem_pmit , sdram0_pmit );
439 mtsdram0( mem_mb0cf , sdram0_b0cr );
440 mtsdram0( mem_mb1cf , sdram0_b1cr );
stroese939403b2003-12-09 14:56:24 +0000441#ifndef CONFIG_405EP /* not on PPC405EP */
wdenkfe8c2802002-11-03 00:38:21 +0000442 mtsdram0( mem_mb2cf , sdram0_b2cr );
443 mtsdram0( mem_mb3cf , sdram0_b3cr );
stroese939403b2003-12-09 14:56:24 +0000444#endif
wdenkfe8c2802002-11-03 00:38:21 +0000445 mtsdram0( mem_sdtr1 , sdram0_tr );
wdenkfe8c2802002-11-03 00:38:21 +0000446
447 /* SDRAM have a power on delay, 500 micro should do */
448 udelay(500);
449 sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200450 if (ecc_on)
451 sdram0_cfg |= SDRAM0_CFG_MEMCHK;
452 mtsdram0(mem_mcopt1, sdram0_cfg);
wdenkfe8c2802002-11-03 00:38:21 +0000453
wdenkfe8c2802002-11-03 00:38:21 +0000454 return (total_size);
455}
456
457int spd_read(uint addr)
458{
459 char data[2];
460
461 if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
462 return (int)data[0];
463 else
464 return 0;
465}
466
467#else /* CONFIG_440 */
468
469/*-----------------------------------------------------------------------------
Stefan Roesec157d8e2005-08-01 16:41:48 +0200470 | Memory Controller Options 0
471 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000472#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
473#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
474#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
475#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
476#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
477#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
478#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
479#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
480#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
481#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
482#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
483#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
484
485/*-----------------------------------------------------------------------------
Stefan Roesec157d8e2005-08-01 16:41:48 +0200486 | Memory Controller Options 1
487 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000488#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
489#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
490
491/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200492 | SDRAM DEVPOT Options
493 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000494#define SDRAM_DEVOPT_DLL 0x80000000
495#define SDRAM_DEVOPT_DS 0x40000000
496
497/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200498 | SDRAM MCSTS Options
499 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000500#define SDRAM_MCSTS_MRSC 0x80000000
501#define SDRAM_MCSTS_SRMS 0x40000000
502#define SDRAM_MCSTS_CIS 0x20000000
503
504/*-----------------------------------------------------------------------------
Stefan Roesec157d8e2005-08-01 16:41:48 +0200505 | SDRAM Refresh Timer Register
506 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000507#define SDRAM_RTR_RINT_MASK 0xFFFF0000
508#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
509#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
510
511/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200512 | SDRAM UABus Base Address Reg
513 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000514#define SDRAM_UABBA_UBBA_MASK 0x0000000F
515
516/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200517 | Memory Bank 0-7 configuration
518 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000519#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
520#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
521#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
522#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
523#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
524#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
525#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
526#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
527#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
528#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
529#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
530#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
531#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
532#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
533#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
534
535/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200536 | SDRAM TR0 Options
537 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000538#define SDRAM_TR0_SDWR_MASK 0x80000000
539#define SDRAM_TR0_SDWR_2_CLK 0x00000000
540#define SDRAM_TR0_SDWR_3_CLK 0x80000000
541#define SDRAM_TR0_SDWD_MASK 0x40000000
542#define SDRAM_TR0_SDWD_0_CLK 0x00000000
543#define SDRAM_TR0_SDWD_1_CLK 0x40000000
544#define SDRAM_TR0_SDCL_MASK 0x01800000
545#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
546#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
547#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
548#define SDRAM_TR0_SDPA_MASK 0x000C0000
549#define SDRAM_TR0_SDPA_2_CLK 0x00040000
550#define SDRAM_TR0_SDPA_3_CLK 0x00080000
551#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
552#define SDRAM_TR0_SDCP_MASK 0x00030000
553#define SDRAM_TR0_SDCP_2_CLK 0x00000000
554#define SDRAM_TR0_SDCP_3_CLK 0x00010000
555#define SDRAM_TR0_SDCP_4_CLK 0x00020000
556#define SDRAM_TR0_SDCP_5_CLK 0x00030000
557#define SDRAM_TR0_SDLD_MASK 0x0000C000
558#define SDRAM_TR0_SDLD_1_CLK 0x00000000
559#define SDRAM_TR0_SDLD_2_CLK 0x00004000
560#define SDRAM_TR0_SDRA_MASK 0x0000001C
561#define SDRAM_TR0_SDRA_6_CLK 0x00000000
562#define SDRAM_TR0_SDRA_7_CLK 0x00000004
563#define SDRAM_TR0_SDRA_8_CLK 0x00000008
564#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
565#define SDRAM_TR0_SDRA_10_CLK 0x00000010
566#define SDRAM_TR0_SDRA_11_CLK 0x00000014
567#define SDRAM_TR0_SDRA_12_CLK 0x00000018
568#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
569#define SDRAM_TR0_SDRD_MASK 0x00000003
570#define SDRAM_TR0_SDRD_2_CLK 0x00000001
571#define SDRAM_TR0_SDRD_3_CLK 0x00000002
572#define SDRAM_TR0_SDRD_4_CLK 0x00000003
573
574/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200575 | SDRAM TR1 Options
576 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000577#define SDRAM_TR1_RDSS_MASK 0xC0000000
578#define SDRAM_TR1_RDSS_TR0 0x00000000
579#define SDRAM_TR1_RDSS_TR1 0x40000000
580#define SDRAM_TR1_RDSS_TR2 0x80000000
581#define SDRAM_TR1_RDSS_TR3 0xC0000000
582#define SDRAM_TR1_RDSL_MASK 0x00C00000
583#define SDRAM_TR1_RDSL_STAGE1 0x00000000
584#define SDRAM_TR1_RDSL_STAGE2 0x00400000
585#define SDRAM_TR1_RDSL_STAGE3 0x00800000
586#define SDRAM_TR1_RDCD_MASK 0x00000800
587#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
588#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
589#define SDRAM_TR1_RDCT_MASK 0x000001FF
590#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
591#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
592#define SDRAM_TR1_RDCT_MIN 0x00000000
593#define SDRAM_TR1_RDCT_MAX 0x000001FF
594
595/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200596 | SDRAM WDDCTR Options
597 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000598#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
599#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
600#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
601#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
602#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
603
604/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200605 | SDRAM CLKTR Options
606 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000607#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
608#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
609#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
610#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
611#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
612
613/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200614 | SDRAM DLYCAL Options
615 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000616#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
617#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
618#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
619
620/*-----------------------------------------------------------------------------+
Stefan Roesec157d8e2005-08-01 16:41:48 +0200621 | General Definition
622 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000623#define DEFAULT_SPD_ADDR1 0x53
624#define DEFAULT_SPD_ADDR2 0x52
wdenkfe8c2802002-11-03 00:38:21 +0000625#define MAXBANKS 4 /* at most 4 dimm banks */
626#define MAX_SPD_BYTES 256
627#define NUMHALFCYCLES 4
628#define NUMMEMTESTS 8
629#define NUMMEMWORDS 8
630#define MAXBXCR 4
631#define TRUE 1
632#define FALSE 0
633
634const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
Stefan Roesec157d8e2005-08-01 16:41:48 +0200635 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
636 0xFFFFFFFF, 0xFFFFFFFF},
637 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
638 0x00000000, 0x00000000},
639 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
640 0x55555555, 0x55555555},
641 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
642 0xAAAAAAAA, 0xAAAAAAAA},
643 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
644 0x5A5A5A5A, 0x5A5A5A5A},
645 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
646 0xA5A5A5A5, 0xA5A5A5A5},
647 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
648 0x55AA55AA, 0x55AA55AA},
649 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
650 0xAA55AA55, 0xAA55AA55}
wdenkfe8c2802002-11-03 00:38:21 +0000651};
652
653
654unsigned char spd_read(uchar chip, uint addr);
655
656void get_spd_info(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000657 unsigned char* iic0_dimm_addr,
658 unsigned long num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000659
660void check_mem_type
Stefan Roesec157d8e2005-08-01 16:41:48 +0200661(unsigned long* dimm_populated,
662 unsigned char* iic0_dimm_addr,
663 unsigned long num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000664
665void check_volt_type
Stefan Roesec157d8e2005-08-01 16:41:48 +0200666(unsigned long* dimm_populated,
667 unsigned char* iic0_dimm_addr,
668 unsigned long num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000669
670void program_cfg0(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000671 unsigned char* iic0_dimm_addr,
672 unsigned long num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000673
674void program_cfg1(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000675 unsigned char* iic0_dimm_addr,
676 unsigned long num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000677
678void program_rtr (unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000679 unsigned char* iic0_dimm_addr,
680 unsigned long num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000681
682void program_tr0 (unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000683 unsigned char* iic0_dimm_addr,
684 unsigned long num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000685
686void program_tr1 (void);
687
688void program_ecc (unsigned long num_bytes);
689
690unsigned
691long program_bxcr(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000692 unsigned char* iic0_dimm_addr,
693 unsigned long num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000694
695/*
696 * This function is reading data from the DIMM module EEPROM over the SPD bus
697 * and uses that to program the sdram controller.
698 *
699 * This works on boards that has the same schematics that the IBM walnut has.
700 *
701 * BUG: Don't handle ECC memory
702 * BUG: A few values in the TR register is currently hardcoded
703 */
704
705long int spd_sdram(void) {
Stefan Roesec157d8e2005-08-01 16:41:48 +0200706 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
707 unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
708 unsigned long total_size;
709 unsigned long cfg0;
710 unsigned long mcsts;
711 unsigned long num_dimm_banks; /* on board dimm banks */
wdenkfe8c2802002-11-03 00:38:21 +0000712
Stefan Roesec157d8e2005-08-01 16:41:48 +0200713 num_dimm_banks = sizeof(iic0_dimm_addr);
wdenkfe8c2802002-11-03 00:38:21 +0000714
715 /*
716 * Make sure I2C controller is initialized
717 * before continuing.
718 */
719 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
720
Stefan Roesec157d8e2005-08-01 16:41:48 +0200721 /*
722 * Read the SPD information using I2C interface. Check to see if the
723 * DIMM slots are populated.
724 */
725 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000726
Stefan Roesec157d8e2005-08-01 16:41:48 +0200727 /*
728 * Check the memory type for the dimms plugged.
729 */
730 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000731
Stefan Roesec157d8e2005-08-01 16:41:48 +0200732 /*
733 * Check the voltage type for the dimms plugged.
734 */
735 check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000736
wdenk63153492005-04-03 20:55:38 +0000737#if defined(CONFIG_440_GX)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200738 /*
739 * Soft-reset SDRAM controller.
740 */
741 mtsdr(sdr_srst, SDR0_SRST_DMC);
742 mtsdr(sdr_srst, 0x00000000);
wdenk63153492005-04-03 20:55:38 +0000743#endif
744
Stefan Roesec157d8e2005-08-01 16:41:48 +0200745 /*
746 * program 440GP SDRAM controller options (SDRAM0_CFG0)
747 */
748 program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000749
Stefan Roesec157d8e2005-08-01 16:41:48 +0200750 /*
751 * program 440GP SDRAM controller options (SDRAM0_CFG1)
752 */
753 program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000754
Stefan Roesec157d8e2005-08-01 16:41:48 +0200755 /*
756 * program SDRAM refresh register (SDRAM0_RTR)
757 */
758 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000759
Stefan Roesec157d8e2005-08-01 16:41:48 +0200760 /*
761 * program SDRAM Timing Register 0 (SDRAM0_TR0)
762 */
763 program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000764
Stefan Roesec157d8e2005-08-01 16:41:48 +0200765 /*
766 * program the BxCR registers to find out total sdram installed
767 */
768 total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
769 num_dimm_banks);
wdenkfe8c2802002-11-03 00:38:21 +0000770
Stefan Roesec157d8e2005-08-01 16:41:48 +0200771 /*
772 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
773 */
774 mtsdram(mem_clktr, 0x40000000);
wdenkfe8c2802002-11-03 00:38:21 +0000775
Stefan Roesec157d8e2005-08-01 16:41:48 +0200776 /*
777 * delay to ensure 200 usec has elapsed
778 */
779 udelay(400);
wdenkfe8c2802002-11-03 00:38:21 +0000780
Stefan Roesec157d8e2005-08-01 16:41:48 +0200781 /*
782 * enable the memory controller
783 */
784 mfsdram(mem_cfg0, cfg0);
785 mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
wdenkfe8c2802002-11-03 00:38:21 +0000786
Stefan Roesec157d8e2005-08-01 16:41:48 +0200787 /*
788 * wait for SDRAM_CFG0_DC_EN to complete
789 */
790 while (1) {
791 mfsdram(mem_mcsts, mcsts);
792 if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
793 break;
794 }
wdenk8bde7f72003-06-27 21:31:46 +0000795 }
wdenkfe8c2802002-11-03 00:38:21 +0000796
Stefan Roesec157d8e2005-08-01 16:41:48 +0200797 /*
798 * program SDRAM Timing Register 1, adding some delays
799 */
800 program_tr1();
wdenkfe8c2802002-11-03 00:38:21 +0000801
Stefan Roesec157d8e2005-08-01 16:41:48 +0200802 /*
803 * if ECC is enabled, initialize parity bits
804 */
wdenkfe8c2802002-11-03 00:38:21 +0000805
806 return total_size;
807}
808
809unsigned char spd_read(uchar chip, uint addr) {
810 unsigned char data[2];
811
Stefan Roesec157d8e2005-08-01 16:41:48 +0200812 if (i2c_probe(chip) == 0) {
813 if (i2c_read(chip, addr, 1, data, 1) == 0) {
814 return data[0];
815 }
816 }
817
818 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000819}
820
821void get_spd_info(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000822 unsigned char* iic0_dimm_addr,
823 unsigned long num_dimm_banks)
wdenkfe8c2802002-11-03 00:38:21 +0000824{
Stefan Roesec157d8e2005-08-01 16:41:48 +0200825 unsigned long dimm_num;
826 unsigned long dimm_found;
827 unsigned char num_of_bytes;
828 unsigned char total_size;
wdenkfe8c2802002-11-03 00:38:21 +0000829
Stefan Roesec157d8e2005-08-01 16:41:48 +0200830 dimm_found = FALSE;
831 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
832 num_of_bytes = 0;
833 total_size = 0;
wdenkfe8c2802002-11-03 00:38:21 +0000834
Stefan Roesec157d8e2005-08-01 16:41:48 +0200835 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
836 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
wdenkfe8c2802002-11-03 00:38:21 +0000837
Stefan Roesec157d8e2005-08-01 16:41:48 +0200838 if ((num_of_bytes != 0) && (total_size != 0)) {
839 dimm_populated[dimm_num] = TRUE;
840 dimm_found = TRUE;
wdenkfe8c2802002-11-03 00:38:21 +0000841#if 0
Stefan Roesec157d8e2005-08-01 16:41:48 +0200842 printf("DIMM slot %lu: populated\n", dimm_num);
wdenkfe8c2802002-11-03 00:38:21 +0000843#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200844 } else {
845 dimm_populated[dimm_num] = FALSE;
wdenkfe8c2802002-11-03 00:38:21 +0000846#if 0
Stefan Roesec157d8e2005-08-01 16:41:48 +0200847 printf("DIMM slot %lu: Not populated\n", dimm_num);
wdenkfe8c2802002-11-03 00:38:21 +0000848#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200849 }
wdenk8bde7f72003-06-27 21:31:46 +0000850 }
wdenkfe8c2802002-11-03 00:38:21 +0000851
Stefan Roesec157d8e2005-08-01 16:41:48 +0200852 if (dimm_found == FALSE) {
853 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
854 hang();
855 }
wdenkfe8c2802002-11-03 00:38:21 +0000856}
857
858void check_mem_type(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000859 unsigned char* iic0_dimm_addr,
860 unsigned long num_dimm_banks)
wdenkfe8c2802002-11-03 00:38:21 +0000861{
Stefan Roesec157d8e2005-08-01 16:41:48 +0200862 unsigned long dimm_num;
863 unsigned char dimm_type;
wdenkfe8c2802002-11-03 00:38:21 +0000864
Stefan Roesec157d8e2005-08-01 16:41:48 +0200865 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
866 if (dimm_populated[dimm_num] == TRUE) {
867 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
868 switch (dimm_type) {
869 case 7:
wdenkfe8c2802002-11-03 00:38:21 +0000870#if 0
Stefan Roesec157d8e2005-08-01 16:41:48 +0200871 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
wdenkfe8c2802002-11-03 00:38:21 +0000872#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200873 break;
874 default:
875 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
876 dimm_num);
877 printf("Only DDR SDRAM DIMMs are supported.\n");
878 printf("Replace the DIMM module with a supported DIMM.\n\n");
879 hang();
880 break;
881 }
882 }
wdenk8bde7f72003-06-27 21:31:46 +0000883 }
wdenkfe8c2802002-11-03 00:38:21 +0000884}
885
886
887void check_volt_type(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000888 unsigned char* iic0_dimm_addr,
889 unsigned long num_dimm_banks)
wdenkfe8c2802002-11-03 00:38:21 +0000890{
Stefan Roesec157d8e2005-08-01 16:41:48 +0200891 unsigned long dimm_num;
892 unsigned long voltage_type;
wdenkfe8c2802002-11-03 00:38:21 +0000893
Stefan Roesec157d8e2005-08-01 16:41:48 +0200894 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
895 if (dimm_populated[dimm_num] == TRUE) {
896 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
897 if (voltage_type != 0x04) {
898 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
899 dimm_num);
900 hang();
901 } else {
wdenkfe8c2802002-11-03 00:38:21 +0000902#if 0
Stefan Roesec157d8e2005-08-01 16:41:48 +0200903 printf("DIMM %lu voltage level supported.\n", dimm_num);
wdenkfe8c2802002-11-03 00:38:21 +0000904#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200905 }
906 break;
907 }
wdenk8bde7f72003-06-27 21:31:46 +0000908 }
wdenkfe8c2802002-11-03 00:38:21 +0000909}
910
911void program_cfg0(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +0000912 unsigned char* iic0_dimm_addr,
913 unsigned long num_dimm_banks)
wdenkfe8c2802002-11-03 00:38:21 +0000914{
Stefan Roesec157d8e2005-08-01 16:41:48 +0200915 unsigned long dimm_num;
916 unsigned long cfg0;
917 unsigned long ecc_enabled;
918 unsigned char ecc;
919 unsigned char attributes;
920 unsigned long data_width;
921 unsigned long dimm_32bit;
922 unsigned long dimm_64bit;
wdenkfe8c2802002-11-03 00:38:21 +0000923
Stefan Roesec157d8e2005-08-01 16:41:48 +0200924 /*
925 * get Memory Controller Options 0 data
926 */
927 mfsdram(mem_cfg0, cfg0);
wdenkfe8c2802002-11-03 00:38:21 +0000928
Stefan Roesec157d8e2005-08-01 16:41:48 +0200929 /*
930 * clear bits
931 */
932 cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
933 SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
934 SDRAM_CFG0_DMWD_MASK |
935 SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
wdenkfe8c2802002-11-03 00:38:21 +0000936
937
Stefan Roesec157d8e2005-08-01 16:41:48 +0200938 /*
939 * FIXME: assume the DDR SDRAMs in both banks are the same
940 */
941 ecc_enabled = TRUE;
942 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
943 if (dimm_populated[dimm_num] == TRUE) {
944 ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
945 if (ecc != 0x02) {
946 ecc_enabled = FALSE;
947 }
wdenkfe8c2802002-11-03 00:38:21 +0000948
Stefan Roesec157d8e2005-08-01 16:41:48 +0200949 /*
950 * program Registered DIMM Enable
951 */
952 attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
953 if ((attributes & 0x02) != 0x00) {
954 cfg0 |= SDRAM_CFG0_RDEN;
955 }
wdenkfe8c2802002-11-03 00:38:21 +0000956
Stefan Roesec157d8e2005-08-01 16:41:48 +0200957 /*
958 * program DDR SDRAM Data Width
959 */
960 data_width =
961 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
962 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
963 if (data_width == 64 || data_width == 72) {
964 dimm_64bit = TRUE;
965 cfg0 |= SDRAM_CFG0_DMWD_64;
966 } else if (data_width == 32 || data_width == 40) {
967 dimm_32bit = TRUE;
968 cfg0 |= SDRAM_CFG0_DMWD_32;
969 } else {
970 printf("WARNING: DIMM with datawidth of %lu bits.\n",
971 data_width);
972 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
973 hang();
974 }
975 break;
976 }
wdenk8bde7f72003-06-27 21:31:46 +0000977 }
wdenkfe8c2802002-11-03 00:38:21 +0000978
Stefan Roesec157d8e2005-08-01 16:41:48 +0200979 /*
980 * program Memory Data Error Checking
981 */
982 if (ecc_enabled == TRUE) {
983 cfg0 |= SDRAM_CFG0_MCHK_GEN;
984 } else {
985 cfg0 |= SDRAM_CFG0_MCHK_NON;
986 }
wdenkfe8c2802002-11-03 00:38:21 +0000987
Stefan Roesec157d8e2005-08-01 16:41:48 +0200988 /*
989 * program Page Management Unit
990 */
991 cfg0 |= SDRAM_CFG0_PMUD;
wdenkfe8c2802002-11-03 00:38:21 +0000992
Stefan Roesec157d8e2005-08-01 16:41:48 +0200993 /*
994 * program Memory Controller Options 0
995 * Note: DCEN must be enabled after all DDR SDRAM controller
996 * configuration registers get initialized.
997 */
998 mtsdram(mem_cfg0, cfg0);
wdenkfe8c2802002-11-03 00:38:21 +0000999}
1000
1001void program_cfg1(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +00001002 unsigned char* iic0_dimm_addr,
1003 unsigned long num_dimm_banks)
wdenkfe8c2802002-11-03 00:38:21 +00001004{
Stefan Roesec157d8e2005-08-01 16:41:48 +02001005 unsigned long cfg1;
1006 mfsdram(mem_cfg1, cfg1);
wdenkfe8c2802002-11-03 00:38:21 +00001007
Stefan Roesec157d8e2005-08-01 16:41:48 +02001008 /*
1009 * Self-refresh exit, disable PM
1010 */
1011 cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
wdenkfe8c2802002-11-03 00:38:21 +00001012
Stefan Roesec157d8e2005-08-01 16:41:48 +02001013 /*
1014 * program Memory Controller Options 1
1015 */
1016 mtsdram(mem_cfg1, cfg1);
wdenkfe8c2802002-11-03 00:38:21 +00001017}
1018
1019void program_rtr (unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +00001020 unsigned char* iic0_dimm_addr,
1021 unsigned long num_dimm_banks)
wdenkfe8c2802002-11-03 00:38:21 +00001022{
Stefan Roesec157d8e2005-08-01 16:41:48 +02001023 unsigned long dimm_num;
1024 unsigned long bus_period_x_10;
1025 unsigned long refresh_rate = 0;
1026 unsigned char refresh_rate_type;
1027 unsigned long refresh_interval;
1028 unsigned long sdram_rtr;
1029 PPC440_SYS_INFO sys_info;
wdenkfe8c2802002-11-03 00:38:21 +00001030
Stefan Roesec157d8e2005-08-01 16:41:48 +02001031 /*
1032 * get the board info
1033 */
1034 get_sys_info(&sys_info);
1035 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
wdenkfe8c2802002-11-03 00:38:21 +00001036
1037
Stefan Roesec157d8e2005-08-01 16:41:48 +02001038 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1039 if (dimm_populated[dimm_num] == TRUE) {
1040 refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
1041 switch (refresh_rate_type) {
1042 case 0x00:
1043 refresh_rate = 15625;
1044 break;
1045 case 0x01:
1046 refresh_rate = 15625/4;
1047 break;
1048 case 0x02:
1049 refresh_rate = 15625/2;
1050 break;
1051 case 0x03:
1052 refresh_rate = 15626*2;
1053 break;
1054 case 0x04:
1055 refresh_rate = 15625*4;
1056 break;
1057 case 0x05:
1058 refresh_rate = 15625*8;
1059 break;
1060 default:
1061 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
1062 dimm_num);
1063 printf("Replace the DIMM module with a supported DIMM.\n");
1064 break;
1065 }
wdenkfe8c2802002-11-03 00:38:21 +00001066
Stefan Roesec157d8e2005-08-01 16:41:48 +02001067 break;
1068 }
wdenk8bde7f72003-06-27 21:31:46 +00001069 }
wdenkfe8c2802002-11-03 00:38:21 +00001070
Stefan Roesec157d8e2005-08-01 16:41:48 +02001071 refresh_interval = refresh_rate * 10 / bus_period_x_10;
1072 sdram_rtr = (refresh_interval & 0x3ff8) << 16;
wdenkfe8c2802002-11-03 00:38:21 +00001073
Stefan Roesec157d8e2005-08-01 16:41:48 +02001074 /*
1075 * program Refresh Timer Register (SDRAM0_RTR)
1076 */
1077 mtsdram(mem_rtr, sdram_rtr);
wdenkfe8c2802002-11-03 00:38:21 +00001078}
1079
1080void program_tr0 (unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +00001081 unsigned char* iic0_dimm_addr,
1082 unsigned long num_dimm_banks)
wdenkfe8c2802002-11-03 00:38:21 +00001083{
Stefan Roesec157d8e2005-08-01 16:41:48 +02001084 unsigned long dimm_num;
1085 unsigned long tr0;
1086 unsigned char wcsbc;
1087 unsigned char t_rp_ns;
1088 unsigned char t_rcd_ns;
1089 unsigned char t_ras_ns;
1090 unsigned long t_rp_clk;
1091 unsigned long t_ras_rcd_clk;
1092 unsigned long t_rcd_clk;
1093 unsigned long t_rfc_clk;
1094 unsigned long plb_check;
1095 unsigned char cas_bit;
1096 unsigned long cas_index;
1097 unsigned char cas_2_0_available;
1098 unsigned char cas_2_5_available;
1099 unsigned char cas_3_0_available;
1100 unsigned long cycle_time_ns_x_10[3];
1101 unsigned long tcyc_3_0_ns_x_10;
1102 unsigned long tcyc_2_5_ns_x_10;
1103 unsigned long tcyc_2_0_ns_x_10;
1104 unsigned long tcyc_reg;
1105 unsigned long bus_period_x_10;
1106 PPC440_SYS_INFO sys_info;
1107 unsigned long residue;
wdenkfe8c2802002-11-03 00:38:21 +00001108
Stefan Roesec157d8e2005-08-01 16:41:48 +02001109 /*
1110 * get the board info
1111 */
1112 get_sys_info(&sys_info);
1113 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
wdenkfe8c2802002-11-03 00:38:21 +00001114
Stefan Roesec157d8e2005-08-01 16:41:48 +02001115 /*
1116 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1117 */
1118 mfsdram(mem_tr0, tr0);
1119 tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
1120 SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
1121 SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
1122 SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
wdenkfe8c2802002-11-03 00:38:21 +00001123
Stefan Roesec157d8e2005-08-01 16:41:48 +02001124 /*
1125 * initialization
1126 */
1127 wcsbc = 0;
1128 t_rp_ns = 0;
1129 t_rcd_ns = 0;
1130 t_ras_ns = 0;
1131 cas_2_0_available = TRUE;
1132 cas_2_5_available = TRUE;
1133 cas_3_0_available = TRUE;
1134 tcyc_2_0_ns_x_10 = 0;
1135 tcyc_2_5_ns_x_10 = 0;
1136 tcyc_3_0_ns_x_10 = 0;
wdenkfe8c2802002-11-03 00:38:21 +00001137
Stefan Roesec157d8e2005-08-01 16:41:48 +02001138 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1139 if (dimm_populated[dimm_num] == TRUE) {
1140 wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
1141 t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
1142 t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
1143 t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
1144 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
wdenkfe8c2802002-11-03 00:38:21 +00001145
Stefan Roesec157d8e2005-08-01 16:41:48 +02001146 for (cas_index = 0; cas_index < 3; cas_index++) {
1147 switch (cas_index) {
1148 case 0:
1149 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1150 break;
1151 case 1:
1152 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1153 break;
1154 default:
1155 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1156 break;
1157 }
1158
1159 if ((tcyc_reg & 0x0F) >= 10) {
1160 printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
1161 dimm_num);
1162 hang();
1163 }
1164
1165 cycle_time_ns_x_10[cas_index] =
1166 (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
1167 }
1168
1169 cas_index = 0;
1170
1171 if ((cas_bit & 0x80) != 0) {
1172 cas_index += 3;
1173 } else if ((cas_bit & 0x40) != 0) {
1174 cas_index += 2;
1175 } else if ((cas_bit & 0x20) != 0) {
1176 cas_index += 1;
1177 }
1178
1179 if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
1180 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1181 cas_index++;
1182 } else {
1183 if (cas_index != 0) {
1184 cas_index++;
1185 }
1186 cas_3_0_available = FALSE;
1187 }
1188
1189 if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
1190 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
1191 cas_index++;
1192 } else {
1193 if (cas_index != 0) {
1194 cas_index++;
1195 }
1196 cas_2_5_available = FALSE;
1197 }
1198
1199 if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
1200 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1201 cas_index++;
1202 } else {
1203 if (cas_index != 0) {
1204 cas_index++;
1205 }
1206 cas_2_0_available = FALSE;
1207 }
1208
1209 break;
wdenk8bde7f72003-06-27 21:31:46 +00001210 }
wdenk8bde7f72003-06-27 21:31:46 +00001211 }
wdenkfe8c2802002-11-03 00:38:21 +00001212
Stefan Roesec157d8e2005-08-01 16:41:48 +02001213 /*
1214 * Program SD_WR and SD_WCSBC fields
1215 */
1216 tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
1217 switch (wcsbc) {
1218 case 0:
1219 tr0 |= SDRAM_TR0_SDWD_0_CLK;
1220 break;
1221 default:
1222 tr0 |= SDRAM_TR0_SDWD_1_CLK;
1223 break;
1224 }
wdenkfe8c2802002-11-03 00:38:21 +00001225
Stefan Roesec157d8e2005-08-01 16:41:48 +02001226 /*
1227 * Program SD_CASL field
1228 */
1229 if ((cas_2_0_available == TRUE) &&
1230 (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
1231 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
1232 } else if ((cas_2_5_available == TRUE) &&
1233 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
1234 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
1235 } else if ((cas_3_0_available == TRUE) &&
1236 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
1237 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
1238 } else {
1239 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
1240 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1241 printf("Make sure the PLB speed is within the supported range.\n");
1242 hang();
1243 }
wdenkfe8c2802002-11-03 00:38:21 +00001244
Stefan Roesec157d8e2005-08-01 16:41:48 +02001245 /*
1246 * Calculate Trp in clock cycles and round up if necessary
1247 * Program SD_PTA field
1248 */
1249 t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
1250 plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
1251 if (sys_info.freqPLB != plb_check) {
1252 t_rp_clk++;
1253 }
1254 switch ((unsigned long)t_rp_clk) {
1255 case 0:
1256 case 1:
1257 case 2:
1258 tr0 |= SDRAM_TR0_SDPA_2_CLK;
1259 break;
1260 case 3:
1261 tr0 |= SDRAM_TR0_SDPA_3_CLK;
1262 break;
1263 default:
1264 tr0 |= SDRAM_TR0_SDPA_4_CLK;
1265 break;
1266 }
wdenkfe8c2802002-11-03 00:38:21 +00001267
Stefan Roesec157d8e2005-08-01 16:41:48 +02001268 /*
1269 * Program SD_CTP field
1270 */
1271 t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
1272 plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
1273 if (sys_info.freqPLB != plb_check) {
1274 t_ras_rcd_clk++;
1275 }
1276 switch (t_ras_rcd_clk) {
1277 case 0:
1278 case 1:
1279 case 2:
1280 tr0 |= SDRAM_TR0_SDCP_2_CLK;
1281 break;
1282 case 3:
1283 tr0 |= SDRAM_TR0_SDCP_3_CLK;
1284 break;
1285 case 4:
1286 tr0 |= SDRAM_TR0_SDCP_4_CLK;
1287 break;
1288 default:
1289 tr0 |= SDRAM_TR0_SDCP_5_CLK;
1290 break;
1291 }
wdenkfe8c2802002-11-03 00:38:21 +00001292
Stefan Roesec157d8e2005-08-01 16:41:48 +02001293 /*
1294 * Program SD_LDF field
1295 */
1296 tr0 |= SDRAM_TR0_SDLD_2_CLK;
wdenkfe8c2802002-11-03 00:38:21 +00001297
Stefan Roesec157d8e2005-08-01 16:41:48 +02001298 /*
1299 * Program SD_RFTA field
1300 * FIXME tRFC hardcoded as 75 nanoseconds
1301 */
1302 t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
1303 residue = sys_info.freqPLB % (ONE_BILLION / 75);
1304 if (residue >= (ONE_BILLION / 150)) {
1305 t_rfc_clk++;
1306 }
1307 switch (t_rfc_clk) {
1308 case 0:
1309 case 1:
1310 case 2:
1311 case 3:
1312 case 4:
1313 case 5:
1314 case 6:
1315 tr0 |= SDRAM_TR0_SDRA_6_CLK;
1316 break;
1317 case 7:
1318 tr0 |= SDRAM_TR0_SDRA_7_CLK;
1319 break;
1320 case 8:
1321 tr0 |= SDRAM_TR0_SDRA_8_CLK;
1322 break;
1323 case 9:
1324 tr0 |= SDRAM_TR0_SDRA_9_CLK;
1325 break;
1326 case 10:
1327 tr0 |= SDRAM_TR0_SDRA_10_CLK;
1328 break;
1329 case 11:
1330 tr0 |= SDRAM_TR0_SDRA_11_CLK;
1331 break;
1332 case 12:
1333 tr0 |= SDRAM_TR0_SDRA_12_CLK;
1334 break;
1335 default:
1336 tr0 |= SDRAM_TR0_SDRA_13_CLK;
1337 break;
1338 }
wdenkfe8c2802002-11-03 00:38:21 +00001339
Stefan Roesec157d8e2005-08-01 16:41:48 +02001340 /*
1341 * Program SD_RCD field
1342 */
1343 t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
1344 plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
1345 if (sys_info.freqPLB != plb_check) {
1346 t_rcd_clk++;
1347 }
1348 switch (t_rcd_clk) {
1349 case 0:
1350 case 1:
1351 case 2:
1352 tr0 |= SDRAM_TR0_SDRD_2_CLK;
1353 break;
1354 case 3:
1355 tr0 |= SDRAM_TR0_SDRD_3_CLK;
1356 break;
1357 default:
1358 tr0 |= SDRAM_TR0_SDRD_4_CLK;
1359 break;
1360 }
wdenkfe8c2802002-11-03 00:38:21 +00001361
1362#if 0
Stefan Roesec157d8e2005-08-01 16:41:48 +02001363 printf("tr0: %x\n", tr0);
wdenkfe8c2802002-11-03 00:38:21 +00001364#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +02001365 mtsdram(mem_tr0, tr0);
wdenkfe8c2802002-11-03 00:38:21 +00001366}
1367
1368void program_tr1 (void)
1369{
Stefan Roesec157d8e2005-08-01 16:41:48 +02001370 unsigned long tr0;
1371 unsigned long tr1;
1372 unsigned long cfg0;
1373 unsigned long ecc_temp;
1374 unsigned long dlycal;
1375 unsigned long dly_val;
1376 unsigned long i, j, k;
1377 unsigned long bxcr_num;
1378 unsigned long max_pass_length;
1379 unsigned long current_pass_length;
1380 unsigned long current_fail_length;
1381 unsigned long current_start;
1382 unsigned long rdclt;
1383 unsigned long rdclt_offset;
1384 long max_start;
1385 long max_end;
1386 long rdclt_average;
1387 unsigned char window_found;
1388 unsigned char fail_found;
1389 unsigned char pass_found;
1390 unsigned long * membase;
1391 PPC440_SYS_INFO sys_info;
wdenkfe8c2802002-11-03 00:38:21 +00001392
Stefan Roesec157d8e2005-08-01 16:41:48 +02001393 /*
1394 * get the board info
1395 */
1396 get_sys_info(&sys_info);
wdenkfe8c2802002-11-03 00:38:21 +00001397
Stefan Roesec157d8e2005-08-01 16:41:48 +02001398 /*
1399 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1400 */
1401 mfsdram(mem_tr1, tr1);
1402 tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1403 SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
wdenkfe8c2802002-11-03 00:38:21 +00001404
Stefan Roesec157d8e2005-08-01 16:41:48 +02001405 mfsdram(mem_tr0, tr0);
1406 if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1407 (sys_info.freqPLB > 100000000)) {
1408 tr1 |= SDRAM_TR1_RDSS_TR2;
1409 tr1 |= SDRAM_TR1_RDSL_STAGE3;
1410 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1411 } else {
1412 tr1 |= SDRAM_TR1_RDSS_TR1;
1413 tr1 |= SDRAM_TR1_RDSL_STAGE2;
1414 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
wdenk8bde7f72003-06-27 21:31:46 +00001415 }
wdenkfe8c2802002-11-03 00:38:21 +00001416
Stefan Roesec157d8e2005-08-01 16:41:48 +02001417 /*
1418 * save CFG0 ECC setting to a temporary variable and turn ECC off
1419 */
1420 mfsdram(mem_cfg0, cfg0);
1421 ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1422 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1423
1424 /*
1425 * get the delay line calibration register value
1426 */
1427 mfsdram(mem_dlycal, dlycal);
1428 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1429
1430 max_pass_length = 0;
1431 max_start = 0;
1432 max_end = 0;
1433 current_pass_length = 0;
1434 current_fail_length = 0;
1435 current_start = 0;
1436 rdclt_offset = 0;
1437 window_found = FALSE;
1438 fail_found = FALSE;
1439 pass_found = FALSE;
wdenkfe8c2802002-11-03 00:38:21 +00001440#ifdef DEBUG
Stefan Roesec157d8e2005-08-01 16:41:48 +02001441 printf("Starting memory test ");
1442#endif
1443 for (k = 0; k < NUMHALFCYCLES; k++) {
1444 for (rdclt = 0; rdclt < dly_val; rdclt++) {
1445 /*
1446 * Set the timing reg for the test.
1447 */
1448 mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1449
1450 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1451 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1452 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1453 /* Bank is enabled */
1454 membase = (unsigned long*)
1455 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1456
1457 /*
1458 * Run the short memory test
1459 */
1460 for (i = 0; i < NUMMEMTESTS; i++) {
1461 for (j = 0; j < NUMMEMWORDS; j++) {
1462 membase[j] = test[i][j];
1463 ppcDcbf((unsigned long)&(membase[j]));
1464 }
1465
1466 for (j = 0; j < NUMMEMWORDS; j++) {
1467 if (membase[j] != test[i][j]) {
1468 ppcDcbf((unsigned long)&(membase[j]));
1469 break;
1470 }
1471 ppcDcbf((unsigned long)&(membase[j]));
1472 }
1473
1474 if (j < NUMMEMWORDS) {
1475 break;
1476 }
1477 }
1478
1479 /*
1480 * see if the rdclt value passed
1481 */
1482 if (i < NUMMEMTESTS) {
1483 break;
1484 }
1485 }
1486 }
1487
1488 if (bxcr_num == MAXBXCR) {
1489 if (fail_found == TRUE) {
1490 pass_found = TRUE;
1491 if (current_pass_length == 0) {
1492 current_start = rdclt_offset + rdclt;
1493 }
1494
1495 current_fail_length = 0;
1496 current_pass_length++;
1497
1498 if (current_pass_length > max_pass_length) {
1499 max_pass_length = current_pass_length;
1500 max_start = current_start;
1501 max_end = rdclt_offset + rdclt;
1502 }
1503 }
1504 } else {
1505 current_pass_length = 0;
1506 current_fail_length++;
1507
1508 if (current_fail_length >= (dly_val>>2)) {
1509 if (fail_found == FALSE) {
1510 fail_found = TRUE;
1511 } else if (pass_found == TRUE) {
1512 window_found = TRUE;
1513 break;
1514 }
1515 }
1516 }
1517 }
1518#ifdef DEBUG
1519 printf(".");
1520#endif
1521 if (window_found == TRUE) {
1522 break;
1523 }
1524
1525 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1526 rdclt_offset += dly_val;
1527 }
1528#ifdef DEBUG
1529 printf("\n");
wdenkfe8c2802002-11-03 00:38:21 +00001530#endif
1531
Stefan Roesec157d8e2005-08-01 16:41:48 +02001532 /*
1533 * make sure we find the window
1534 */
1535 if (window_found == FALSE) {
1536 printf("ERROR: Cannot determine a common read delay.\n");
1537 hang();
1538 }
wdenkfe8c2802002-11-03 00:38:21 +00001539
Stefan Roesec157d8e2005-08-01 16:41:48 +02001540 /*
1541 * restore the orignal ECC setting
1542 */
1543 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
wdenkfe8c2802002-11-03 00:38:21 +00001544
Stefan Roesec157d8e2005-08-01 16:41:48 +02001545 /*
1546 * set the SDRAM TR1 RDCD value
1547 */
1548 tr1 &= ~SDRAM_TR1_RDCD_MASK;
1549 if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1550 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1551 } else {
1552 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1553 }
wdenkfe8c2802002-11-03 00:38:21 +00001554
Stefan Roesec157d8e2005-08-01 16:41:48 +02001555 /*
1556 * set the SDRAM TR1 RDCLT value
1557 */
1558 tr1 &= ~SDRAM_TR1_RDCT_MASK;
1559 while (max_end >= (dly_val << 1)) {
1560 max_end -= (dly_val << 1);
1561 max_start -= (dly_val << 1);
1562 }
wdenkfe8c2802002-11-03 00:38:21 +00001563
Stefan Roesec157d8e2005-08-01 16:41:48 +02001564 rdclt_average = ((max_start + max_end) >> 1);
1565 if (rdclt_average >= 0x60)
1566 while (1)
1567 ;
wdenkfe8c2802002-11-03 00:38:21 +00001568
Stefan Roesec157d8e2005-08-01 16:41:48 +02001569 if (rdclt_average < 0) {
1570 rdclt_average = 0;
1571 }
wdenkfe8c2802002-11-03 00:38:21 +00001572
Stefan Roesec157d8e2005-08-01 16:41:48 +02001573 if (rdclt_average >= dly_val) {
1574 rdclt_average -= dly_val;
1575 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1576 }
1577 tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
wdenkfe8c2802002-11-03 00:38:21 +00001578
1579#if 0
Stefan Roesec157d8e2005-08-01 16:41:48 +02001580 printf("tr1: %x\n", tr1);
wdenkfe8c2802002-11-03 00:38:21 +00001581#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +02001582 /*
1583 * program SDRAM Timing Register 1 TR1
1584 */
1585 mtsdram(mem_tr1, tr1);
wdenkfe8c2802002-11-03 00:38:21 +00001586}
1587
1588unsigned long program_bxcr(unsigned long* dimm_populated,
wdenk8bde7f72003-06-27 21:31:46 +00001589 unsigned char* iic0_dimm_addr,
1590 unsigned long num_dimm_banks)
wdenkfe8c2802002-11-03 00:38:21 +00001591{
Stefan Roesec157d8e2005-08-01 16:41:48 +02001592 unsigned long dimm_num;
Stefan Roesec157d8e2005-08-01 16:41:48 +02001593 unsigned long bank_base_addr;
1594 unsigned long bank_size_bytes;
1595 unsigned long cr;
1596 unsigned long i;
1597 unsigned long temp;
1598 unsigned char num_row_addr;
1599 unsigned char num_col_addr;
1600 unsigned char num_banks;
1601 unsigned char bank_size_id;
wdenkfe8c2802002-11-03 00:38:21 +00001602
Stefan Roese17f50f222005-08-04 17:09:16 +02001603#ifndef CONFIG_BAMBOO
1604 unsigned long bxcr_num;
wdenkfe8c2802002-11-03 00:38:21 +00001605
Stefan Roesec157d8e2005-08-01 16:41:48 +02001606 /*
1607 * Set the BxCR regs. First, wipe out the bank config registers.
1608 */
1609 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1610 mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1611 mtdcr(memcfgd, 0x00000000);
wdenk8bde7f72003-06-27 21:31:46 +00001612 }
Stefan Roese17f50f222005-08-04 17:09:16 +02001613#endif
wdenkfe8c2802002-11-03 00:38:21 +00001614
Stefan Roesec157d8e2005-08-01 16:41:48 +02001615 /*
1616 * reset the bank_base address
1617 */
Stefan Roese17f50f222005-08-04 17:09:16 +02001618#ifndef CONFIG_BAMBOO
Stefan Roesec157d8e2005-08-01 16:41:48 +02001619 bank_base_addr = CFG_SDRAM_BASE;
Stefan Roese17f50f222005-08-04 17:09:16 +02001620#else
1621 bank_base_addr = CFG_SDRAM_ONBOARD_SIZE;
1622#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +02001623
1624 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1625 if (dimm_populated[dimm_num] == TRUE) {
1626 num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1627 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1628 num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
1629 bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1630
1631 /*
1632 * Set the SDRAM0_BxCR regs
1633 */
1634 cr = 0;
1635 bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
1636 switch (bank_size_id) {
1637 case 0x02:
1638 cr |= SDRAM_BXCR_SDSZ_8;
1639 break;
1640 case 0x04:
1641 cr |= SDRAM_BXCR_SDSZ_16;
1642 break;
1643 case 0x08:
1644 cr |= SDRAM_BXCR_SDSZ_32;
1645 break;
1646 case 0x10:
1647 cr |= SDRAM_BXCR_SDSZ_64;
1648 break;
1649 case 0x20:
1650 cr |= SDRAM_BXCR_SDSZ_128;
1651 break;
1652 case 0x40:
1653 cr |= SDRAM_BXCR_SDSZ_256;
1654 break;
1655 case 0x80:
1656 cr |= SDRAM_BXCR_SDSZ_512;
1657 break;
1658 default:
1659 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1660 dimm_num);
1661 printf("ERROR: Unsupported value for the banksize: %d.\n",
1662 bank_size_id);
1663 printf("Replace the DIMM module with a supported DIMM.\n\n");
1664 hang();
1665 }
1666
1667 switch (num_col_addr) {
1668 case 0x08:
1669 cr |= SDRAM_BXCR_SDAM_1;
1670 break;
1671 case 0x09:
1672 cr |= SDRAM_BXCR_SDAM_2;
1673 break;
1674 case 0x0A:
1675 cr |= SDRAM_BXCR_SDAM_3;
1676 break;
1677 case 0x0B:
1678 cr |= SDRAM_BXCR_SDAM_4;
1679 break;
1680 default:
1681 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1682 dimm_num);
1683 printf("ERROR: Unsupported value for number of "
1684 "column addresses: %d.\n", num_col_addr);
1685 printf("Replace the DIMM module with a supported DIMM.\n\n");
1686 hang();
1687 }
1688
1689 /*
1690 * enable the bank
1691 */
1692 cr |= SDRAM_BXCR_SDBE;
1693
1694 /*------------------------------------------------------------------
1695 | This next section is hardware dependent and must be programmed
1696 | to match the hardware.
1697 +-----------------------------------------------------------------*/
1698 if (dimm_num == 0) {
1699 for (i = 0; i < num_banks; i++) {
Stefan Roese17f50f222005-08-04 17:09:16 +02001700#ifndef CONFIG_BAMBOO
Stefan Roesec157d8e2005-08-01 16:41:48 +02001701 mtdcr(memcfga, mem_b0cr + (i << 2));
Stefan Roese17f50f222005-08-04 17:09:16 +02001702#else
1703 mtdcr(memcfga, mem_b1cr + (i << 2));
1704#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +02001705 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1706 SDRAM_BXCR_SDSZ_MASK |
1707 SDRAM_BXCR_SDAM_MASK |
1708 SDRAM_BXCR_SDBE);
1709 cr |= temp;
1710 cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1711 mtdcr(memcfgd, cr);
1712 bank_base_addr += bank_size_bytes;
1713 }
1714 } else {
1715 for (i = 0; i < num_banks; i++) {
Stefan Roese17f50f222005-08-04 17:09:16 +02001716#ifndef CONFIG_BAMBOO
Stefan Roesec157d8e2005-08-01 16:41:48 +02001717 mtdcr(memcfga, mem_b2cr + (i << 2));
Stefan Roese17f50f222005-08-04 17:09:16 +02001718#else
1719 mtdcr(memcfga, mem_b3cr + (i << 2));
1720#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +02001721 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1722 SDRAM_BXCR_SDSZ_MASK |
1723 SDRAM_BXCR_SDAM_MASK |
1724 SDRAM_BXCR_SDBE);
1725 cr |= temp;
1726 cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1727 mtdcr(memcfgd, cr);
1728 bank_base_addr += bank_size_bytes;
1729 }
1730 }
1731 }
1732 }
1733
1734 return(bank_base_addr);
wdenkfe8c2802002-11-03 00:38:21 +00001735}
1736
1737void program_ecc (unsigned long num_bytes)
1738{
Stefan Roesec157d8e2005-08-01 16:41:48 +02001739 unsigned long bank_base_addr;
1740 unsigned long current_address;
1741 unsigned long end_address;
1742 unsigned long address_increment;
1743 unsigned long cfg0;
wdenkfe8c2802002-11-03 00:38:21 +00001744
Stefan Roesec157d8e2005-08-01 16:41:48 +02001745 /*
1746 * get Memory Controller Options 0 data
1747 */
1748 mfsdram(mem_cfg0, cfg0);
wdenkfe8c2802002-11-03 00:38:21 +00001749
Stefan Roesec157d8e2005-08-01 16:41:48 +02001750 /*
1751 * reset the bank_base address
1752 */
1753 bank_base_addr = CFG_SDRAM_BASE;
wdenkfe8c2802002-11-03 00:38:21 +00001754
Stefan Roesec157d8e2005-08-01 16:41:48 +02001755 if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1756 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1757 SDRAM_CFG0_MCHK_GEN);
wdenkfe8c2802002-11-03 00:38:21 +00001758
Stefan Roesec157d8e2005-08-01 16:41:48 +02001759 if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1760 address_increment = 4;
1761 } else {
1762 address_increment = 8;
1763 }
1764
1765 current_address = (unsigned long)(bank_base_addr);
1766 end_address = (unsigned long)(bank_base_addr) + num_bytes;
1767
1768 while (current_address < end_address) {
1769 *((unsigned long*)current_address) = 0x00000000;
1770 current_address += address_increment;
1771 }
1772
1773 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1774 SDRAM_CFG0_MCHK_CHK);
wdenk8bde7f72003-06-27 21:31:46 +00001775 }
wdenkfe8c2802002-11-03 00:38:21 +00001776}
1777
1778#endif /* CONFIG_440 */
1779
1780#endif /* CONFIG_SPD_EEPROM */