Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 1 | /* |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 2 | * Copyright 2004, 2007 Freescale Semiconductor. |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * mpc8548cds board configuration file |
| 25 | * |
| 26 | * Please refer to doc/README.mpc85xxcds for more info. |
| 27 | * |
| 28 | */ |
| 29 | #ifndef __CONFIG_H |
| 30 | #define __CONFIG_H |
| 31 | |
| 32 | /* High Level Configuration Options */ |
| 33 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 34 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 35 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
| 36 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ |
| 37 | #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ |
| 38 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 39 | #define CONFIG_PCI /* enable any pci type devices */ |
| 40 | #define CONFIG_PCI1 /* PCI controller 1 */ |
| 41 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ |
| 42 | #undef CONFIG_RIO |
| 43 | #undef CONFIG_PCI2 |
| 44 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Kumar Gala | 8ff3de6 | 2007-12-07 12:17:34 -0600 | [diff] [blame] | 45 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 46 | |
| 47 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 48 | #define CONFIG_ENV_OVERWRITE |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 49 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
Kumar Gala | 2cfaa1a | 2008-01-16 01:45:10 -0600 | [diff] [blame] | 50 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 51 | |
Jon Loeliger | 25eedb2 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 52 | #define CONFIG_FSL_VIA |
Jon Loeliger | 25eedb2 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 53 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 54 | /* |
| 55 | * When initializing flash, if we cannot find the manufacturer ID, |
| 56 | * assume this is the AMD flash associated with the CDS board. |
| 57 | * This allows booting from a promjet. |
| 58 | */ |
| 59 | #define CONFIG_ASSUME_AMD_FLASH |
| 60 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 61 | #ifndef __ASSEMBLY__ |
| 62 | extern unsigned long get_clock_freq(void); |
| 63 | #endif |
| 64 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ |
| 65 | |
| 66 | /* |
| 67 | * These can be toggled for performance analysis, otherwise use default. |
| 68 | */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 69 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 70 | #define CONFIG_BTB /* toggle branch predition */ |
| 71 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
| 72 | #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 73 | |
| 74 | /* |
| 75 | * Only possible on E500 Version 2 or newer cores. |
| 76 | */ |
| 77 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 78 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 79 | #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ |
| 80 | #define CFG_MEMTEST_END 0x00400000 |
| 81 | |
| 82 | /* |
| 83 | * Base addresses -- Note these are effective addresses where the |
| 84 | * actual resources get mapped (not physical addresses) |
| 85 | */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 86 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 87 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
Kumar Gala | f69766e | 2008-01-30 14:55:14 -0600 | [diff] [blame] | 88 | #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 89 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
| 90 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 91 | #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) |
| 92 | #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) |
| 93 | #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) |
| 94 | |
Jon Loeliger | e31d2c1 | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 95 | /* DDR Setup */ |
| 96 | #define CONFIG_FSL_DDR2 |
| 97 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 98 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 99 | #define CONFIG_DDR_SPD |
| 100 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
| 101 | |
| 102 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 103 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 104 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 105 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 106 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
| 107 | |
Jon Loeliger | e31d2c1 | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 108 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 109 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 110 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 111 | |
Jon Loeliger | e31d2c1 | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 112 | /* I2C addresses of SPD EEPROMs */ |
| 113 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
| 114 | |
| 115 | /* Make sure required options are set */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 116 | #ifndef CONFIG_SPD_EEPROM |
| 117 | #error ("CONFIG_SPD_EEPROM is required") |
| 118 | #endif |
| 119 | |
| 120 | #undef CONFIG_CLOCKS_IN_MHZ |
| 121 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 122 | /* |
| 123 | * Local Bus Definitions |
| 124 | */ |
| 125 | |
| 126 | /* |
| 127 | * FLASH on the Local Bus |
| 128 | * Two banks, 8M each, using the CFI driver. |
| 129 | * Boot from BR0/OR0 bank at 0xff00_0000 |
| 130 | * Alternate BR1/OR1 bank at 0xff80_0000 |
| 131 | * |
| 132 | * BR0, BR1: |
| 133 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 |
| 134 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 |
| 135 | * Port Size = 16 bits = BRx[19:20] = 10 |
| 136 | * Use GPCM = BRx[24:26] = 000 |
| 137 | * Valid = BRx[31] = 1 |
| 138 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 139 | * 0 4 8 12 16 20 24 28 |
| 140 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 |
| 141 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 142 | * |
| 143 | * OR0, OR1: |
| 144 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 |
| 145 | * Reserved ORx[17:18] = 11, confusion here? |
| 146 | * CSNT = ORx[20] = 1 |
| 147 | * ACS = half cycle delay = ORx[21:22] = 11 |
| 148 | * SCY = 6 = ORx[24:27] = 0110 |
| 149 | * TRLX = use relaxed timing = ORx[29] = 1 |
| 150 | * EAD = use external address latch delay = OR[31] = 1 |
| 151 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 152 | * 0 4 8 12 16 20 24 28 |
| 153 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 154 | */ |
| 155 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 156 | #define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */ |
| 157 | #define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 158 | |
| 159 | #define CFG_BR0_PRELIM 0xff801001 |
| 160 | #define CFG_BR1_PRELIM 0xff001001 |
| 161 | |
| 162 | #define CFG_OR0_PRELIM 0xff806e65 |
| 163 | #define CFG_OR1_PRELIM 0xff806e65 |
| 164 | |
| 165 | #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} |
| 166 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ |
| 167 | #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
| 168 | #undef CFG_FLASH_CHECKSUM |
| 169 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 170 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 171 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 172 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 173 | |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 174 | #define CONFIG_FLASH_CFI_DRIVER |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 175 | #define CFG_FLASH_CFI |
| 176 | #define CFG_FLASH_EMPTY_INFO |
| 177 | |
| 178 | |
| 179 | /* |
| 180 | * SDRAM on the Local Bus |
| 181 | */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 182 | #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ |
| 183 | #define CFG_LBC_CACHE_SIZE 64 |
| 184 | #define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ |
| 185 | #define CFG_LBC_NONCACHE_SIZE 64 |
| 186 | |
| 187 | #define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 188 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
| 189 | |
| 190 | /* |
| 191 | * Base Register 2 and Option Register 2 configure SDRAM. |
| 192 | * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
| 193 | * |
| 194 | * For BR2, need: |
| 195 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 196 | * port-size = 32-bits = BR2[19:20] = 11 |
| 197 | * no parity checking = BR2[21:22] = 00 |
| 198 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 199 | * Valid = BR[31] = 1 |
| 200 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 201 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 202 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 203 | * |
| 204 | * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
| 205 | * FIXME: the top 17 bits of BR2. |
| 206 | */ |
| 207 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 208 | #define CFG_BR2_PRELIM 0xf0001861 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 209 | |
| 210 | /* |
| 211 | * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
| 212 | * |
| 213 | * For OR2, need: |
| 214 | * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| 215 | * XAM, OR2[17:18] = 11 |
| 216 | * 9 columns OR2[19-21] = 010 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 217 | * 13 rows OR2[23-25] = 100 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 218 | * EAD set for extra time OR[31] = 1 |
| 219 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 220 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 221 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| 222 | */ |
| 223 | |
| 224 | #define CFG_OR2_PRELIM 0xfc006901 |
| 225 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 226 | #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
| 227 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ |
| 228 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 229 | #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 230 | |
| 231 | /* |
| 232 | * LSDMR masks |
| 233 | */ |
| 234 | #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) |
| 235 | #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
| 236 | #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
| 237 | #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
| 238 | #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
| 239 | #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
| 240 | #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
| 241 | #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) |
| 242 | #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
| 243 | #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) |
| 244 | |
| 245 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
| 246 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
| 247 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
| 248 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
| 249 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
| 250 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
| 251 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
| 252 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
| 253 | |
| 254 | /* |
| 255 | * Common settings for all Local Bus SDRAM commands. |
| 256 | * At run time, either BSMA1516 (for CPU 1.1) |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 257 | * or BSMA1617 (for CPU 1.0) (old) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 258 | * is OR'ed in too. |
| 259 | */ |
| 260 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ |
| 261 | | CFG_LBC_LSDMR_PRETOACT7 \ |
| 262 | | CFG_LBC_LSDMR_ACTTORW7 \ |
| 263 | | CFG_LBC_LSDMR_BL8 \ |
| 264 | | CFG_LBC_LSDMR_WRC4 \ |
| 265 | | CFG_LBC_LSDMR_CL3 \ |
| 266 | | CFG_LBC_LSDMR_RFEN \ |
| 267 | ) |
| 268 | |
| 269 | /* |
| 270 | * The CADMUS registers are connected to CS3 on CDS. |
| 271 | * The new memory map places CADMUS at 0xf8000000. |
| 272 | * |
| 273 | * For BR3, need: |
| 274 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 |
| 275 | * port-size = 8-bits = BR[19:20] = 01 |
| 276 | * no parity checking = BR[21:22] = 00 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 277 | * GPMC for MSEL = BR[24:26] = 000 |
| 278 | * Valid = BR[31] = 1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 279 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 280 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 281 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
| 282 | * |
| 283 | * For OR3, need: |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 284 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 285 | * disable buffer ctrl OR[19] = 0 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 286 | * CSNT OR[20] = 1 |
| 287 | * ACS OR[21:22] = 11 |
| 288 | * XACS OR[23] = 1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 289 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 290 | * SETA OR[28] = 0 |
| 291 | * TRLX OR[29] = 1 |
| 292 | * EHTR OR[30] = 1 |
| 293 | * EAD extra time OR[31] = 1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 294 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 295 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 296 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
| 297 | */ |
| 298 | |
Jon Loeliger | 25eedb2 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 299 | #define CONFIG_FSL_CADMUS |
| 300 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 301 | #define CADMUS_BASE_ADDR 0xf8000000 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 302 | #define CFG_BR3_PRELIM 0xf8000801 |
| 303 | #define CFG_OR3_PRELIM 0xfff00ff7 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 304 | |
| 305 | #define CONFIG_L1_INIT_RAM |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 306 | #define CFG_INIT_RAM_LOCK 1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 307 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 308 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 309 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 310 | #define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
| 311 | |
| 312 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 313 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 314 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 315 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 316 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 317 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 318 | |
| 319 | /* Serial Port */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 320 | #define CONFIG_CONS_INDEX 2 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 321 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 322 | #define CFG_NS16550 |
| 323 | #define CFG_NS16550_SERIAL |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 324 | #define CFG_NS16550_REG_SIZE 1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 325 | #define CFG_NS16550_CLK get_bus_freq(0) |
| 326 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 327 | #define CFG_BAUDRATE_TABLE \ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 328 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 329 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 330 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
| 331 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 332 | |
| 333 | /* Use the HUSH parser */ |
| 334 | #define CFG_HUSH_PARSER |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 335 | #ifdef CFG_HUSH_PARSER |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 336 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 337 | #endif |
| 338 | |
Matthew McClintock | 40d5fa3 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 339 | /* pass open firmware flat tree */ |
Kumar Gala | b90d254 | 2007-11-29 00:11:44 -0600 | [diff] [blame] | 340 | #define CONFIG_OF_LIBFDT 1 |
| 341 | #define CONFIG_OF_BOARD_SETUP 1 |
| 342 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
Matthew McClintock | 40d5fa3 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 343 | |
Jon Loeliger | e31d2c1 | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 344 | #define CFG_64BIT_VSPRINTF 1 |
| 345 | #define CFG_64BIT_STRTOUL 1 |
| 346 | |
Jon Loeliger | 2047672 | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 347 | /* |
| 348 | * I2C |
| 349 | */ |
| 350 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 351 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 352 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 353 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 354 | #define CFG_I2C_SLAVE 0x7F |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 355 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
Jon Loeliger | 2047672 | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 356 | #define CFG_I2C_OFFSET 0x3000 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 357 | |
Timur Tabi | e8d1854 | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 358 | /* EEPROM */ |
| 359 | #define CONFIG_ID_EEPROM |
| 360 | #define CFG_I2C_EEPROM_CCID |
| 361 | #define CFG_ID_EEPROM |
| 362 | #define CFG_I2C_EEPROM_ADDR 0x57 |
| 363 | #define CFG_I2C_EEPROM_ADDR_LEN 2 |
| 364 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 365 | /* |
| 366 | * General PCI |
Sergei Shtylyov | 362dd83 | 2006-12-27 22:07:15 +0300 | [diff] [blame] | 367 | * Memory space is mapped 1-1, but I/O space must start from 0. |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 368 | */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 369 | #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
| 370 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 371 | #define CFG_PCI1_MEM_BASE 0x80000000 |
| 372 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 373 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
Matthew McClintock | cbfc7ce | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 374 | #define CFG_PCI1_IO_BASE 0x00000000 |
| 375 | #define CFG_PCI1_IO_PHYS 0xe2000000 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 376 | #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 377 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 378 | #ifdef CONFIG_PCI2 |
| 379 | #define CFG_PCI2_MEM_BASE 0xa0000000 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 380 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 381 | #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
Andy Fleming | ffa621a | 2007-02-24 01:08:13 -0600 | [diff] [blame] | 382 | #define CFG_PCI2_IO_BASE 0x00000000 |
Zang Roy-r61911 | 41fb7e0 | 2006-12-14 14:14:55 +0800 | [diff] [blame] | 383 | #define CFG_PCI2_IO_PHYS 0xe2800000 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 384 | #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ |
| 385 | #endif |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 386 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 387 | #ifdef CONFIG_PCIE1 |
| 388 | #define CFG_PCIE1_MEM_BASE 0xa0000000 |
| 389 | #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE |
| 390 | #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 391 | #define CFG_PCIE1_IO_BASE 0x00000000 |
| 392 | #define CFG_PCIE1_IO_PHYS 0xe3000000 |
| 393 | #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
| 394 | #endif |
Zang Roy-r61911 | 41fb7e0 | 2006-12-14 14:14:55 +0800 | [diff] [blame] | 395 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 396 | #ifdef CONFIG_RIO |
Zang Roy-r61911 | 41fb7e0 | 2006-12-14 14:14:55 +0800 | [diff] [blame] | 397 | /* |
| 398 | * RapidIO MMU |
| 399 | */ |
| 400 | #define CFG_RIO_MEM_BASE 0xC0000000 |
| 401 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 402 | #endif |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 403 | |
Randy Vinson | 7f3f2bd | 2007-02-27 19:42:22 -0700 | [diff] [blame] | 404 | #ifdef CONFIG_LEGACY |
| 405 | #define BRIDGE_ID 17 |
| 406 | #define VIA_ID 2 |
| 407 | #else |
| 408 | #define BRIDGE_ID 28 |
| 409 | #define VIA_ID 4 |
| 410 | #endif |
| 411 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 412 | #if defined(CONFIG_PCI) |
| 413 | |
| 414 | #define CONFIG_NET_MULTI |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 415 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 416 | |
| 417 | #undef CONFIG_EEPRO100 |
| 418 | #undef CONFIG_TULIP |
| 419 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 420 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 421 | |
| 422 | /* PCI view of System Memory */ |
| 423 | #define CFG_PCI_MEMORY_BUS 0x00000000 |
| 424 | #define CFG_PCI_MEMORY_PHYS 0x00000000 |
| 425 | #define CFG_PCI_MEMORY_SIZE 0x80000000 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 426 | |
| 427 | #endif /* CONFIG_PCI */ |
| 428 | |
| 429 | |
| 430 | #if defined(CONFIG_TSEC_ENET) |
| 431 | |
| 432 | #ifndef CONFIG_NET_MULTI |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 433 | #define CONFIG_NET_MULTI 1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 434 | #endif |
| 435 | |
| 436 | #define CONFIG_MII 1 /* MII PHY management */ |
Kim Phillips | 255a3577 | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 437 | #define CONFIG_TSEC1 1 |
| 438 | #define CONFIG_TSEC1_NAME "eTSEC0" |
| 439 | #define CONFIG_TSEC2 1 |
| 440 | #define CONFIG_TSEC2_NAME "eTSEC1" |
| 441 | #define CONFIG_TSEC3 1 |
| 442 | #define CONFIG_TSEC3_NAME "eTSEC2" |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 443 | #define CONFIG_TSEC4 |
Kim Phillips | 255a3577 | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 444 | #define CONFIG_TSEC4_NAME "eTSEC3" |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 445 | #undef CONFIG_MPC85XX_FEC |
| 446 | |
| 447 | #define TSEC1_PHY_ADDR 0 |
| 448 | #define TSEC2_PHY_ADDR 1 |
| 449 | #define TSEC3_PHY_ADDR 2 |
| 450 | #define TSEC4_PHY_ADDR 3 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 451 | |
| 452 | #define TSEC1_PHYIDX 0 |
| 453 | #define TSEC2_PHYIDX 0 |
| 454 | #define TSEC3_PHYIDX 0 |
| 455 | #define TSEC4_PHYIDX 0 |
Andy Fleming | 3a79013 | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 456 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 457 | #define TSEC2_FLAGS TSEC_GIGABIT |
| 458 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 459 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 460 | |
| 461 | /* Options are: eTSEC[0-3] */ |
| 462 | #define CONFIG_ETHPRIME "eTSEC0" |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 463 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 464 | #endif /* CONFIG_TSEC_ENET */ |
| 465 | |
| 466 | /* |
| 467 | * Environment |
| 468 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 469 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 470 | #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
| 471 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
| 472 | #define CONFIG_ENV_SIZE 0x2000 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 473 | |
| 474 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 475 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 476 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 477 | /* |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 478 | * BOOTP options |
| 479 | */ |
| 480 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 481 | #define CONFIG_BOOTP_BOOTPATH |
| 482 | #define CONFIG_BOOTP_GATEWAY |
| 483 | #define CONFIG_BOOTP_HOSTNAME |
| 484 | |
| 485 | |
| 486 | /* |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 487 | * Command line configuration. |
| 488 | */ |
| 489 | #include <config_cmd_default.h> |
| 490 | |
| 491 | #define CONFIG_CMD_PING |
| 492 | #define CONFIG_CMD_I2C |
| 493 | #define CONFIG_CMD_MII |
Kumar Gala | 82ac8c9 | 2007-12-07 12:04:30 -0600 | [diff] [blame] | 494 | #define CONFIG_CMD_ELF |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 495 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 496 | #if defined(CONFIG_PCI) |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 497 | #define CONFIG_CMD_PCI |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 498 | #endif |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 499 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 500 | |
| 501 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 502 | |
| 503 | /* |
| 504 | * Miscellaneous configurable options |
| 505 | */ |
| 506 | #define CFG_LONGHELP /* undef to save memory */ |
Kumar Gala | 22abb2d | 2007-11-29 10:34:28 -0600 | [diff] [blame] | 507 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 508 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
| 509 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 510 | #if defined(CONFIG_CMD_KGDB) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 511 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 512 | #else |
| 513 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 514 | #endif |
| 515 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 516 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 517 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 518 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 519 | |
| 520 | /* |
| 521 | * For booting Linux, the board info and command line data |
| 522 | * have to be in the first 8 MB of memory, since this is |
| 523 | * the maximum mapped by the Linux kernel during initialization. |
| 524 | */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 525 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 526 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 527 | /* |
| 528 | * Internal Definitions |
| 529 | * |
| 530 | * Boot Flags |
| 531 | */ |
| 532 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 533 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 534 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 535 | #if defined(CONFIG_CMD_KGDB) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 536 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 537 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 538 | #endif |
| 539 | |
| 540 | /* |
| 541 | * Environment Configuration |
| 542 | */ |
| 543 | |
| 544 | /* The mac addresses for all ethernet interface */ |
| 545 | #if defined(CONFIG_TSEC_ENET) |
Andy Fleming | 10327dc | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 546 | #define CONFIG_HAS_ETH0 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 547 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 548 | #define CONFIG_HAS_ETH1 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 549 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 550 | #define CONFIG_HAS_ETH2 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 551 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
Andy Fleming | 09f3e09 | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 552 | #define CONFIG_HAS_ETH3 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 553 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 554 | #endif |
| 555 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 556 | #define CONFIG_IPADDR 192.168.1.253 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 557 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 558 | #define CONFIG_HOSTNAME unknown |
| 559 | #define CONFIG_ROOTPATH /nfsroot |
| 560 | #define CONFIG_BOOTFILE 8548cds/uImage.uboot |
| 561 | #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 562 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 563 | #define CONFIG_SERVERIP 192.168.1.1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 564 | #define CONFIG_GATEWAYIP 192.168.1.1 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 565 | #define CONFIG_NETMASK 255.255.255.0 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 566 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 567 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 568 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 569 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
| 570 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 571 | |
| 572 | #define CONFIG_BAUDRATE 115200 |
| 573 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 574 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 575 | "netdev=eth0\0" \ |
| 576 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ |
| 577 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 578 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 579 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 580 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ |
| 581 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 582 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ |
| 583 | "consoledev=ttyS1\0" \ |
| 584 | "ramdiskaddr=2000000\0" \ |
Andy Fleming | 6c54359 | 2007-08-13 14:38:06 -0500 | [diff] [blame] | 585 | "ramdiskfile=ramdisk.uboot\0" \ |
Ed Swarthout | 4bf4abb | 2007-08-21 09:38:59 -0500 | [diff] [blame] | 586 | "fdtaddr=c00000\0" \ |
Kumar Gala | 22abb2d | 2007-11-29 10:34:28 -0600 | [diff] [blame] | 587 | "fdtfile=mpc8548cds.dtb\0" |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 588 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 589 | #define CONFIG_NFSBOOTCOMMAND \ |
| 590 | "setenv bootargs root=/dev/nfs rw " \ |
| 591 | "nfsroot=$serverip:$rootpath " \ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 592 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 593 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 594 | "tftp $loadaddr $bootfile;" \ |
Ed Swarthout | 4bf4abb | 2007-08-21 09:38:59 -0500 | [diff] [blame] | 595 | "tftp $fdtaddr $fdtfile;" \ |
| 596 | "bootm $loadaddr - $fdtaddr" |
Andy Fleming | 8272dc2 | 2006-09-13 10:33:35 -0500 | [diff] [blame] | 597 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 598 | |
| 599 | #define CONFIG_RAMBOOTCOMMAND \ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 600 | "setenv bootargs root=/dev/ram rw " \ |
| 601 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 602 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 603 | "tftp $loadaddr $bootfile;" \ |
Ed Swarthout | 4bf4abb | 2007-08-21 09:38:59 -0500 | [diff] [blame] | 604 | "tftp $fdtaddr $fdtfile;" \ |
| 605 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 606 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 607 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 608 | |
| 609 | #endif /* __CONFIG_H */ |