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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +08002/*
3 * Copyright (C) 2015 Freescale Semiconductor
Yangbo Lu34f39ce2021-06-03 10:51:19 +08004 * Copyright 2019-2021 NXP
Mingkai Huf3a8e2b2015-10-26 19:47:52 +08005 */
6
7#ifndef __LS1043A_COMMON_H
8#define __LS1043A_COMMON_H
9
Sumit Garg4139b172017-03-30 09:52:38 +053010/* SPL build */
11#ifdef CONFIG_SPL_BUILD
12#define SPL_NO_FMAN
13#define SPL_NO_DSPI
14#define SPL_NO_PCIE
15#define SPL_NO_ENV
16#define SPL_NO_MISC
17#define SPL_NO_USB
18#define SPL_NO_SATA
19#define SPL_NO_QE
20#define SPL_NO_EEPROM
21#endif
22#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
23#define SPL_NO_MMC
24#endif
Yangbo Lu3c7d6472017-09-15 09:51:58 +080025#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
Sumit Garg4139b172017-03-30 09:52:38 +053026#define SPL_NO_IFC
27#endif
28
Bharat Bhushan5344c7b2017-03-22 12:06:27 +053029#include <asm/arch/stream_id_lsch2.h>
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080030#include <asm/arch/config.h>
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080031
32/* Link Definitions */
Rajesh Bhagatf71b5f12018-11-05 18:02:44 +000033#ifdef CONFIG_TFABOOT
34#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
35#else
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080036#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
Rajesh Bhagatf71b5f12018-11-05 18:02:44 +000037#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080038
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080039#define CONFIG_VERY_BIG_RAM
40#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
41#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
42#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shaohui Xiee994ddd2015-11-23 15:23:48 +080043#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080044
Michael Walle3d3fe8b2020-06-01 21:53:26 +020045#define CPU_RELEASE_ADDR secondary_boot_addr
Hou Zhiqiang831c0682015-10-26 19:47:57 +080046
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080047/* Generic Timer Definitions */
48#define COUNTER_FREQUENCY 25000000 /* 25MHz */
49
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080050/* Serial Port */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080051#define CONFIG_SYS_NS16550_SERIAL
52#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang904110c2017-01-10 16:44:15 +080053#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080054
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080055/* SD boot SPL */
56#ifdef CONFIG_SD_BOOT
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080057
Ruchika Gupta70f96612017-04-17 18:07:17 +053058#define CONFIG_SPL_MAX_SIZE 0x17000
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080059#define CONFIG_SPL_STACK 0x1001e000
60#define CONFIG_SPL_PAD_TO 0x1d000
61
York Sun23af4842017-09-28 08:42:16 -070062#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
63 CONFIG_SPL_BSS_MAX_SIZE)
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080064#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
York Sun23af4842017-09-28 08:42:16 -070065#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080066#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Ruchika Gupta70f96612017-04-17 18:07:17 +053067
Udit Agarwal5536c3c2019-11-07 16:11:32 +000068#ifdef CONFIG_NXP_ESBC
Ruchika Gupta70f96612017-04-17 18:07:17 +053069#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
70/*
71 * HDR would be appended at end of image and copied to DDR along
72 * with U-Boot image. Here u-boot max. size is 512K. So if binary
73 * size increases then increase this size in case of secure boot as
74 * it uses raw u-boot image instead of fit image.
75 */
76#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
77#else
78#define CONFIG_SYS_MONITOR_LEN 0x100000
Udit Agarwal5536c3c2019-11-07 16:11:32 +000079#endif /* ifdef CONFIG_NXP_ESBC */
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080080#endif
81
Gong Qianyu3ad44722015-10-26 19:47:53 +080082/* NAND SPL */
83#ifdef CONFIG_NAND_BOOT
84#define CONFIG_SPL_PBL_PAD
Gong Qianyu3ad44722015-10-26 19:47:53 +080085#define CONFIG_SPL_MAX_SIZE 0x1a000
86#define CONFIG_SPL_STACK 0x1001d000
87#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
88#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
89#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
90#define CONFIG_SPL_BSS_START_ADDR 0x80100000
91#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
92#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Ruchika Gupta762f92a2017-04-17 18:07:18 +053093
Udit Agarwal5536c3c2019-11-07 16:11:32 +000094#ifdef CONFIG_NXP_ESBC
Ruchika Gupta762f92a2017-04-17 18:07:18 +053095#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Udit Agarwal5536c3c2019-11-07 16:11:32 +000096#endif /* ifdef CONFIG_NXP_ESBC */
Ruchika Gupta762f92a2017-04-17 18:07:18 +053097
98#ifdef CONFIG_U_BOOT_HDR_SIZE
99/*
100 * HDR would be appended at end of image and copied to DDR along
101 * with U-Boot image. Here u-boot max. size is 512K. So if binary
102 * size increases then increase this size in case of secure boot as
103 * it uses raw u-boot image instead of fit image.
104 */
105#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
106#else
107#define CONFIG_SYS_MONITOR_LEN 0x100000
108#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
109
Gong Qianyu3ad44722015-10-26 19:47:53 +0800110#endif
111
Biwen Libe7b6d52021-02-05 19:01:56 +0800112/* GPIO */
Biwen Libe7b6d52021-02-05 19:01:56 +0800113
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800114/* IFC */
Sumit Garg4139b172017-03-30 09:52:38 +0530115#ifndef SPL_NO_IFC
Rajesh Bhagatf71b5f12018-11-05 18:02:44 +0000116#if defined(CONFIG_TFABOOT) || \
117 (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800118/*
119 * CONFIG_SYS_FLASH_BASE has the final address (core view)
120 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
121 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
122 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
123 */
124#define CONFIG_SYS_FLASH_BASE 0x60000000
125#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
126#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
127
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900128#ifdef CONFIG_MTD_NOR_FLASH
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800129#define CONFIG_SYS_FLASH_QUIET_TEST
130#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
131#endif
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800132#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530133#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800134
135/* I2C */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800136
137/* PCIe */
Sumit Garg4139b172017-03-30 09:52:38 +0530138#ifndef SPL_NO_PCIE
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800139#define CONFIG_PCIE1 /* PCIE controller 1 */
140#define CONFIG_PCIE2 /* PCIE controller 2 */
141#define CONFIG_PCIE3 /* PCIE controller 3 */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800142
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800143#ifdef CONFIG_PCI
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800144#define CONFIG_PCI_SCAN_SHOW
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800145#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530146#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800147
Gong Qianyue0579a52016-01-25 15:16:05 +0800148/* DSPI */
Gong Qianyue0579a52016-01-25 15:16:05 +0800149
Shaohui Xiee8297342015-10-26 19:47:54 +0800150/* FMan ucode */
Sumit Garg4139b172017-03-30 09:52:38 +0530151#ifndef SPL_NO_FMAN
Shaohui Xiee8297342015-10-26 19:47:54 +0800152#define CONFIG_SYS_DPAA_FMAN
153#ifdef CONFIG_SYS_DPAA_FMAN
154#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
155
Shaohui Xiee8297342015-10-26 19:47:54 +0800156#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
157#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530158#endif
Shaohui Xiee8297342015-10-26 19:47:54 +0800159
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800160/* Miscellaneous configurable options */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800161
162#define CONFIG_HWCONFIG
163#define HWCONFIG_BUFFER_SIZE 128
164
Sumit Garg4139b172017-03-30 09:52:38 +0530165#ifndef SPL_NO_MISC
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800166#ifndef CONFIG_SPL_BUILD
167#define BOOT_TARGET_DEVICES(func) \
168 func(MMC, mmc, 0) \
Mian Yousaf Kaukab688cdf42019-01-29 16:38:40 +0100169 func(USB, usb, 0) \
170 func(DHCP, dhcp, na)
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800171#include <config_distro_bootcmd.h>
172#endif
173
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800174/* Initial environment variables */
175#define CONFIG_EXTRA_ENV_SETTINGS \
176 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800177 "fdt_high=0xffffffffffffffff\0" \
178 "initrd_high=0xffffffffffffffff\0" \
Wolfgang Denk0cf207e2021-09-27 17:42:39 +0200179 "fdt_addr=0x64f00000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530180 "kernel_addr=0x61000000\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800181 "scriptaddr=0x80000000\0" \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530182 "scripthdraddr=0x80080000\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800183 "fdtheader_addr_r=0x80100000\0" \
184 "kernelheader_addr_r=0x80200000\0" \
185 "kernel_addr_r=0x81000000\0" \
Wen Heeb967b92018-11-20 16:55:25 +0800186 "kernel_start=0x1000000\0" \
187 "kernelheader_start=0x800000\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800188 "fdt_addr_r=0x90000000\0" \
189 "load_addr=0xa0000000\0" \
Manish Tomar507103f2020-11-05 14:08:55 +0530190 "kernelheader_addr=0x60600000\0" \
Qianyu Gongad6767b2016-03-15 16:35:57 +0800191 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530192 "kernelheader_size=0x40000\0" \
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800193 "kernel_addr_sd=0x8000\0" \
194 "kernel_size_sd=0x14000\0" \
Manish Tomar507103f2020-11-05 14:08:55 +0530195 "kernelhdr_addr_sd=0x3000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530196 "kernelhdr_size_sd=0x10\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800197 "console=ttyS0,115200\0" \
York Sun23af4842017-09-28 08:42:16 -0700198 "boot_os=y\0" \
Tom Rini43ede0b2017-10-22 17:55:07 -0400199 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800200 BOOTENV \
201 "boot_scripts=ls1043ardb_boot.scr\0" \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530202 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800203 "scan_dev_for_boot_part=" \
204 "part list ${devtype} ${devnum} devplist; " \
205 "env exists devplist || setenv devplist 1; " \
206 "for distro_bootpart in ${devplist}; do " \
207 "if fstype ${devtype} " \
208 "${devnum}:${distro_bootpart} " \
209 "bootfstype; then " \
210 "run scan_dev_for_boot; " \
211 "fi; " \
212 "done\0" \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530213 "boot_a_script=" \
214 "load ${devtype} ${devnum}:${distro_bootpart} " \
215 "${scriptaddr} ${prefix}${script}; " \
216 "env exists secureboot && load ${devtype} " \
217 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai78c58082019-04-23 05:52:17 +0000218 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
219 "env exists secureboot " \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530220 "&& esbc_validate ${scripthdraddr};" \
221 "source ${scriptaddr}\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800222 "qspi_bootcmd=echo Trying load from qspi..;" \
223 "sf probe && sf read $load_addr " \
Wen He283e4ab2019-11-14 15:08:15 +0800224 "$kernel_start $kernel_size; env exists secureboot " \
225 "&& sf read $kernelheader_addr_r $kernelheader_start " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530226 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
227 "bootm $load_addr#$board\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800228 "nor_bootcmd=echo Trying load from nor..;" \
229 "cp.b $kernel_addr $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530230 "$kernel_size; env exists secureboot " \
231 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
232 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
233 "bootm $load_addr#$board\0" \
Wen Heeb967b92018-11-20 16:55:25 +0800234 "nand_bootcmd=echo Trying load from NAND..;" \
235 "nand info; nand read $load_addr " \
236 "$kernel_start $kernel_size; env exists secureboot " \
237 "&& nand read $kernelheader_addr_r $kernelheader_start " \
238 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
239 "bootm $load_addr#$board\0" \
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800240 "sd_bootcmd=echo Trying load from SD ..;" \
241 "mmcinfo; mmc read $load_addr " \
242 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530243 "env exists secureboot && mmc read $kernelheader_addr_r " \
244 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
245 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800246 "bootm $load_addr#$board\0"
247
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800248
Rajesh Bhagatf71b5f12018-11-05 18:02:44 +0000249#ifdef CONFIG_TFABOOT
250#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
251 "env exists secureboot && esbc_halt;"
252#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
253 "env exists secureboot && esbc_halt;"
254#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
255 "env exists secureboot && esbc_halt;"
Pankit Garg1f3d7392018-12-27 04:37:53 +0000256#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
257 "env exists secureboot && esbc_halt;"
Sumit Garg4139b172017-03-30 09:52:38 +0530258#endif
Rajesh Bhagatf71b5f12018-11-05 18:02:44 +0000259#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800260
261/* Monitor Command Prompt */
262#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Sumit Garg4139b172017-03-30 09:52:38 +0530263
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800264#define CONFIG_SYS_MAXARGS 64 /* max command args */
265
266#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
267
Simon Glass457e51c2017-05-17 08:23:10 -0600268#include <asm/arch/soc.h>
269
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800270#endif /* __LS1043A_COMMON_H */