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Timur Tabi2ad6b512006-10-31 18:44:42 -06001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
Timur Tabi7a78f142007-01-31 15:54:29 -060024 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Timur Tabi2ad6b512006-10-31 18:44:42 -060025
26 Memory map:
27
28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
Timur Tabi7a78f142007-01-31 15:54:29 -060034 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060035 0xF001_0000-0xF001_FFFF Local bus expansion slot
Timur Tabi7a78f142007-01-31 15:54:29 -060036 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060039
40 I2C address list:
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010041 Align. Board
42 Bus Addr Part No. Description Length Location
Timur Tabi2ad6b512006-10-31 18:44:42 -060043 ----------------------------------------------------------------
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010044 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
Timur Tabi2ad6b512006-10-31 18:44:42 -060045
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010046 I2C1 0x20 PCF8574 I2C Expander 0 U8
47 I2C1 0x21 PCF8574 I2C Expander 0 U10
48 I2C1 0x38 PCF8574A I2C Expander 0 U8
49 I2C1 0x39 PCF8574A I2C Expander 0 U10
50 I2C1 0x51 (DDR) DDR EEPROM 1 U1
51 I2C1 0x68 DS1339 RTC 1 U68
Timur Tabi2ad6b512006-10-31 18:44:42 -060052
53 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
54*/
55
56#ifndef __CONFIG_H
57#define __CONFIG_H
58
Timur Tabi7a78f142007-01-31 15:54:29 -060059#if (TEXT_BASE == 0xFE000000)
60#define CFG_LOWBOOT
61#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -060062
63/*
64 * High Level Configuration Options
65 */
66#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */
67#define CONFIG_MPC8349 /* MPC8349 specific */
68
Timur Tabi7a78f142007-01-31 15:54:29 -060069#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */
Timur Tabi2ad6b512006-10-31 18:44:42 -060070
Timur Tabi7a78f142007-01-31 15:54:29 -060071
72/* On-board devices */
73
74#ifdef CONFIG_MPC8349ITX
Timur Tabi2ad6b512006-10-31 18:44:42 -060075#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
Timur Tabi7a78f142007-01-31 15:54:29 -060076#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */
77#endif
78
79#define CONFIG_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -060080#define CONFIG_RTC_DS1337
Timur Tabi7a78f142007-01-31 15:54:29 -060081#define CONFIG_HARD_I2C
82#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
83
84/*
85 * Device configurations
86 */
Timur Tabi2ad6b512006-10-31 18:44:42 -060087
88/* I2C */
Timur Tabi2ad6b512006-10-31 18:44:42 -060089#ifdef CONFIG_HARD_I2C
90
91#define CONFIG_MISC_INIT_F
92#define CONFIG_MISC_INIT_R
93
Timur Tabibe5e6182006-11-03 19:15:00 -060094#define CONFIG_FSL_I2C
Timur Tabi2ad6b512006-10-31 18:44:42 -060095#define CONFIG_I2C_MULTI_BUS
96#define CONFIG_I2C_CMD_TREE
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010097#define CFG_I2C_OFFSET 0x3000
98#define CFG_I2C2_OFFSET 0x3100
Timur Tabibe5e6182006-11-03 19:15:00 -060099#define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600100
Timur Tabibe5e6182006-11-03 19:15:00 -0600101#define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
102#define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
103#define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
104#define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100105#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
Timur Tabibe5e6182006-11-03 19:15:00 -0600106#define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
107#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600108
109#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
110#define CFG_I2C_SLAVE 0x7F
111
112/* Don't probe these addresses: */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100113#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \
Timur Tabi2ad6b512006-10-31 18:44:42 -0600114 {1, CFG_I2C_8574_ADDR2}, \
115 {1, CFG_I2C_8574A_ADDR1}, \
116 {1, CFG_I2C_8574A_ADDR2}}
117/* Bit definitions for the 8574[A] I2C expander */
118#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
119#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
120#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
121#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
122#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
123
124#undef CONFIG_SOFT_I2C
125
126#endif
127
Timur Tabi7a78f142007-01-31 15:54:29 -0600128/* Compact Flash */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600129#ifdef CONFIG_COMPACT_FLASH
130
Timur Tabi2ad6b512006-10-31 18:44:42 -0600131#define CFG_IDE_MAXBUS 1
132#define CFG_IDE_MAXDEVICE 1
133
134#define CFG_ATA_IDE0_OFFSET 0x0000
135#define CFG_ATA_BASE_ADDR CFG_CF_BASE
136#define CFG_ATA_DATA_OFFSET 0x0000
137#define CFG_ATA_REG_OFFSET 0
138#define CFG_ATA_ALT_OFFSET 0x0200
139#define CFG_ATA_STRIDE 2
140
141#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
142
Timur Tabi2ad6b512006-10-31 18:44:42 -0600143#define CONFIG_DOS_PARTITION
144
Timur Tabi7a78f142007-01-31 15:54:29 -0600145#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600146
Timur Tabi7a78f142007-01-31 15:54:29 -0600147/*
148 * DDR Setup
149 */
150#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
151#define CFG_SDRAM_BASE CFG_DDR_BASE
152#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
153#define CFG_83XX_DDR_USES_CS0
154#define CFG_MEMTEST_START 0x1000 /* memtest region */
155#define CFG_MEMTEST_END 0x2000
156
Timur Tabif64702b2007-04-30 13:59:50 -0500157#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
158 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
159
Timur Tabi7a78f142007-01-31 15:54:29 -0600160#ifdef CONFIG_HARD_I2C
161#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
162#endif
163
164#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */
165 #define CFG_DDR_SIZE 256 /* Mb */
166 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
167
168 #define CFG_DDR_TIMING_1 0x26242321
169 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
170#endif
171
172/*
173 *Flash on the Local Bus
174 */
175
176#define CFG_FLASH_CFI /* use the Common Flash Interface */
177#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
178#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
179#define CFG_FLASH_EMPTY_INFO
180#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */
181#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
182#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
183#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
184
185/* The ITX has two flash chips, but the ITX-GP has only one. To support both
186boards, we say we have two, but don't display a message if we find only one. */
187#define CFG_FLASH_QUIET_TEST
188#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
189#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
190#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
191#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
192
193/*
194 * BRx, ORx, LBLAWBARx, and LBLAWARx
195 */
196
197/* Flash */
198
199#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
200#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
201 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
202 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
203#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
204#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
205
206/* Vitesse 7385 */
207
208#ifdef CONFIG_VSC7385
209
210#define CFG_VSC7385_BASE 0xF8000000
211
212#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
213#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
214 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
215 OR_GPCM_EHTR | OR_GPCM_EAD)
216
217#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE
218#define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
219
220#endif
221
222/* LED */
223
224#define CFG_LED_BASE 0xF9000000
225#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V)
226#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
227 OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
228 OR_GPCM_EHTR | OR_GPCM_EAD)
229
230/* Compact Flash */
231
232#ifdef CONFIG_COMPACT_FLASH
233
234#define CFG_CF_BASE 0xF0000000
235
236#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
237#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
238
239#define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE
240#define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
241
242#endif
243
244/*
245 * U-Boot memory configuration
246 */
247#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600248
249#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
250#define CFG_RAMBOOT
251#else
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100252#undef CFG_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600253#endif
254
255#define CONFIG_L1_INIT_RAM
256#define CFG_INIT_RAM_LOCK
Timur Tabi7a78f142007-01-31 15:54:29 -0600257#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
258#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600259
Timur Tabi7a78f142007-01-31 15:54:29 -0600260#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600261#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
262#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
263
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100264#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
265#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600266
267/*
268 * Local Bus LCRR and LBCR regs
269 * LCRR: DLL bypass, Clock divider is 4
270 * External Local Bus rate is
271 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
272 */
273#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
274#define CFG_LBC_LBCR 0x00000000
275
Timur Tabi2ad6b512006-10-31 18:44:42 -0600276#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
277#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
278
279/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600280 * Serial Port
281 */
282#define CONFIG_CONS_INDEX 1
283#undef CONFIG_SERIAL_SOFTWARE_FIFO
284#define CFG_NS16550
285#define CFG_NS16550_SERIAL
286#define CFG_NS16550_REG_SIZE 1
287#define CFG_NS16550_CLK get_bus_freq(0)
288
289#define CFG_BAUDRATE_TABLE \
Timur Tabi7a78f142007-01-31 15:54:29 -0600290 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
291
292#define CONFIG_BAUDRATE 115200
Timur Tabi2ad6b512006-10-31 18:44:42 -0600293
Timur Tabid239d742006-11-03 12:00:28 -0600294#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
295#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600296
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600297/* pass open firmware flat tree */
Timur Tabi7a78f142007-01-31 15:54:29 -0600298#define CONFIG_OF_FLAT_TREE
299#define CONFIG_OF_BOARD_SETUP
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600300
301/* maximum size of the flat tree (8K) */
302#define OF_FLAT_TREE_MAX_SIZE 8192
303
304#define OF_CPU "PowerPC,8349@0"
305#define OF_SOC "soc8349@e0000000"
306#define OF_TBCLK (bd->bi_busfreq / 4)
307#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600308
Timur Tabi7a78f142007-01-31 15:54:29 -0600309/*
310 * PCI
311 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600312#ifdef CONFIG_PCI
313
314#define CONFIG_MPC83XX_PCI2
315
316/*
317 * General PCI
318 * Addresses are mapped 1-1.
319 */
320#define CFG_PCI1_MEM_BASE 0x80000000
321#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
322#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
323#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE)
324#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
325#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
326#define CFG_PCI1_IO_BASE 0x00000000
327#define CFG_PCI1_IO_PHYS 0xE2000000
328#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
329
330#ifdef CONFIG_MPC83XX_PCI2
331#define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE)
332#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
333#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
334#define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE)
335#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
336#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
337#define CFG_PCI2_IO_BASE 0x00000000
338#define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE)
339#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
340#endif
341
342#define _IO_BASE 0x00000000 /* points to PCI I/O space */
343
344#define CONFIG_NET_MULTI
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100345#define CONFIG_PCI_PNP /* do pci plug-and-play */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600346
347#ifdef CONFIG_RTL8139
348/* This macro is used by RTL8139 but not defined in PPC architecture */
349#define KSEG1ADDR(x) (x)
350#endif
351
352#ifndef CONFIG_PCI_PNP
353 #define PCI_ENET0_IOADDR 0x00000000
354 #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE
355 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
356#endif
357
358#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
359
360#endif
361
Timur Tabi7a78f142007-01-31 15:54:29 -0600362#define PCI_66M
363#ifdef PCI_66M
364#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
365#else
366#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
367#endif
368
Timur Tabi2ad6b512006-10-31 18:44:42 -0600369/* TSEC */
370
371#ifdef CONFIG_TSEC_ENET
372
Timur Tabi2ad6b512006-10-31 18:44:42 -0600373#define CONFIG_NET_MULTI
Timur Tabi2ad6b512006-10-31 18:44:42 -0600374#define CONFIG_MII
375#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
376
Kim Phillips255a35772007-05-16 16:52:19 -0500377#define CONFIG_TSEC1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600378
Kim Phillips255a35772007-05-16 16:52:19 -0500379#ifdef CONFIG_TSEC1
380#define CONFIG_TSEC1_NAME "TSEC0"
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100381#define CFG_TSEC1_OFFSET 0x24000
382#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600383#define TSEC1_PHYIDX 0
384#endif
385
Kim Phillips255a35772007-05-16 16:52:19 -0500386#ifdef CONFIG_TSEC2
Timur Tabi7a78f142007-01-31 15:54:29 -0600387#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500388#define CONFIG_TSEC2_NAME "TSEC1"
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100389#define CFG_TSEC2_OFFSET 0x25000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600390#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
391#define TSEC2_PHY_ADDR 4
392#define TSEC2_PHYIDX 0
393#endif
394
395#define CONFIG_ETHPRIME "Freescale TSEC"
396
397#endif
398
Timur Tabi2ad6b512006-10-31 18:44:42 -0600399/*
400 * Environment
401 */
Timur Tabi7a78f142007-01-31 15:54:29 -0600402#define CONFIG_ENV_OVERWRITE
403
Timur Tabi2ad6b512006-10-31 18:44:42 -0600404#ifndef CFG_RAMBOOT
405 #define CFG_ENV_IS_IN_FLASH
Timur Tabi7a78f142007-01-31 15:54:29 -0600406 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
407 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE))
Timur Tabi2ad6b512006-10-31 18:44:42 -0600408 #define CFG_ENV_SIZE 0x2000
409#else
410 #define CFG_NO_FLASH /* Flash is not usable now */
411 #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */
412 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
413 #define CFG_ENV_SIZE 0x2000
414#endif
415
416#define CONFIG_LOADS_ECHO /* echo on for serial download */
417#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
418
Jon Loeliger8ea54992007-07-04 22:30:06 -0500419/*
420 * Command line configuration.
421 */
422#include <config_cmd_default.h>
423
424#define CONFIG_CMD_CACHE
425#define CONFIG_CMD_DATE
426#define CONFIG_CMD_IRQ
427#define CONFIG_CMD_NET
428#define CONFIG_CMD_PING
429#define CONFIG_CMD_SDRAM
Timur Tabi2ad6b512006-10-31 18:44:42 -0600430
431#ifdef CONFIG_COMPACT_FLASH
Jon Loeliger8ea54992007-07-04 22:30:06 -0500432 #define CONFIG_CMD_IDE
433 #define CONFIG_CMD_FAT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600434#endif
435
436#ifdef CONFIG_PCI
Jon Loeliger8ea54992007-07-04 22:30:06 -0500437 #define CONFIG_CMD_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -0600438#endif
439
440#ifdef CONFIG_HARD_I2C
Jon Loeliger8ea54992007-07-04 22:30:06 -0500441 #define CONFIG_CMD_I2C
Timur Tabi2ad6b512006-10-31 18:44:42 -0600442#endif
443
Timur Tabi2ad6b512006-10-31 18:44:42 -0600444
445/* Watchdog */
446
447#undef CONFIG_WATCHDOG /* watchdog disabled */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600448
449/*
450 * Miscellaneous configurable options
451 */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100452#define CFG_LONGHELP /* undef to save memory */
Timur Tabi7a78f142007-01-31 15:54:29 -0600453#define CONFIG_CMDLINE_EDITING /* Command-line editing */
454#define CFG_HUSH_PARSER /* Use the HUSH parser */
455#define CFG_PROMPT_HUSH_PS2 "> "
456
Timur Tabi2ad6b512006-10-31 18:44:42 -0600457#define CFG_LOAD_ADDR 0x2000000 /* default load address */
Timur Tabi7a78f142007-01-31 15:54:29 -0600458#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
459
460#ifdef CONFIG_MPC8349ITX
461#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
462#else
463#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
464#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600465
Jon Loeliger8ea54992007-07-04 22:30:06 -0500466#if defined(CONFIG_CMD_KGDB)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600467 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
468#else
469 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
470#endif
471
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100472#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600473#define CFG_MAXARGS 16 /* max number of command args */
474#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
475#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
476
477/*
478 * For booting Linux, the board info and command line data
479 * have to be in the first 8 MB of memory, since this is
480 * the maximum mapped by the Linux kernel during initialization.
481 */
482#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
483
Timur Tabi7a78f142007-01-31 15:54:29 -0600484/*
485 * Cache Configuration
486 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600487#define CFG_DCACHE_SIZE 32768
488#define CFG_CACHELINE_SIZE 32
Jon Loeliger8ea54992007-07-04 22:30:06 -0500489#if defined(CONFIG_CMD_KGDB)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600490#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */
491#endif
492
Timur Tabi2ad6b512006-10-31 18:44:42 -0600493#define CFG_HRCW_LOW (\
494 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
495 HRCWL_DDR_TO_SCB_CLK_1X1 |\
496 HRCWL_CSB_TO_CLKIN_4X1 |\
497 HRCWL_VCO_1X2 |\
498 HRCWL_CORE_TO_CSB_2X1)
499
Timur Tabi7a78f142007-01-31 15:54:29 -0600500#ifdef CFG_LOWBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600501#define CFG_HRCW_HIGH (\
502 HRCWH_PCI_HOST |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600503 HRCWH_32_BIT_PCI |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600504 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600505 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600506 HRCWH_CORE_ENABLE |\
507 HRCWH_FROM_0X00000100 |\
508 HRCWH_BOOTSEQ_DISABLE |\
509 HRCWH_SW_WATCHDOG_DISABLE |\
510 HRCWH_ROM_LOC_LOCAL_16BIT |\
511 HRCWH_TSEC1M_IN_GMII |\
512 HRCWH_TSEC2M_IN_GMII )
513#else
514#define CFG_HRCW_HIGH (\
515 HRCWH_PCI_HOST |\
516 HRCWH_32_BIT_PCI |\
517 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600518 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600519 HRCWH_CORE_ENABLE |\
520 HRCWH_FROM_0XFFF00100 |\
521 HRCWH_BOOTSEQ_DISABLE |\
522 HRCWH_SW_WATCHDOG_DISABLE |\
523 HRCWH_ROM_LOC_LOCAL_16BIT |\
524 HRCWH_TSEC1M_IN_GMII |\
525 HRCWH_TSEC2M_IN_GMII )
526#endif
527
Timur Tabi7a78f142007-01-31 15:54:29 -0600528/*
529 * System performance
530 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600531#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
532#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
533#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
534#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
535#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
Timur Tabibe5e6182006-11-03 19:15:00 -0600536#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600537
Timur Tabi7a78f142007-01-31 15:54:29 -0600538/*
539 * System IO Config
540 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600541#define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
Timur Tabi98883332006-10-31 19:14:41 -0600542#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600543
Timur Tabi7a78f142007-01-31 15:54:29 -0600544#define CFG_HID0_INIT 0x000000000
545#define CFG_HID0_FINAL CFG_HID0_INIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600546
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100547#define CFG_HID2 HID2_HBE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600548
Timur Tabi7a78f142007-01-31 15:54:29 -0600549/* DDR */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600550#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
551#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
552
Timur Tabi7a78f142007-01-31 15:54:29 -0600553/* PCI */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600554#ifdef CONFIG_PCI
555#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
556#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
557#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
558#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
559#else
560#define CFG_IBAT1L 0
561#define CFG_IBAT1U 0
562#define CFG_IBAT2L 0
563#define CFG_IBAT2U 0
564#endif
565
566#ifdef CONFIG_MPC83XX_PCI2
567#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
568#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
569#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
570#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
571#else
572#define CFG_IBAT3L 0
573#define CFG_IBAT3U 0
574#define CFG_IBAT4L 0
575#define CFG_IBAT4U 0
576#endif
577
578/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Timur Tabid239d742006-11-03 12:00:28 -0600579#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
580#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600581
582/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
583#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
584#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
585
586#define CFG_IBAT7L 0
587#define CFG_IBAT7U 0
588
589#define CFG_DBAT0L CFG_IBAT0L
590#define CFG_DBAT0U CFG_IBAT0U
591#define CFG_DBAT1L CFG_IBAT1L
592#define CFG_DBAT1U CFG_IBAT1U
593#define CFG_DBAT2L CFG_IBAT2L
594#define CFG_DBAT2U CFG_IBAT2U
595#define CFG_DBAT3L CFG_IBAT3L
596#define CFG_DBAT3U CFG_IBAT3U
597#define CFG_DBAT4L CFG_IBAT4L
598#define CFG_DBAT4U CFG_IBAT4U
599#define CFG_DBAT5L CFG_IBAT5L
600#define CFG_DBAT5U CFG_IBAT5U
601#define CFG_DBAT6L CFG_IBAT6L
602#define CFG_DBAT6U CFG_IBAT6U
603#define CFG_DBAT7L CFG_IBAT7L
604#define CFG_DBAT7U CFG_IBAT7U
605
606/*
607 * Internal Definitions
608 *
609 * Boot Flags
610 */
611#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
612#define BOOTFLAG_WARM 0x02 /* Software reboot */
613
Jon Loeliger8ea54992007-07-04 22:30:06 -0500614#if defined(CONFIG_CMD_KGDB)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600615#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
616#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
617#endif
618
619
620/*
621 * Environment Configuration
622 */
623#define CONFIG_ENV_OVERWRITE
624
Kim Phillips255a35772007-05-16 16:52:19 -0500625#ifdef CONFIG_TSEC1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600626#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
627#endif
628
Kim Phillips255a35772007-05-16 16:52:19 -0500629#ifdef CONFIG_TSEC2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600630#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
631#endif
632
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600633#define CONFIG_IPADDR 192.168.1.253
634#define CONFIG_SERVERIP 192.168.1.1
635#define CONFIG_GATEWAYIP 192.168.1.1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600636#define CONFIG_NETMASK 255.255.252.0
Timur Tabi98883332006-10-31 19:14:41 -0600637#define CONFIG_NETDEV eth0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600638
Timur Tabi7a78f142007-01-31 15:54:29 -0600639#ifdef CONFIG_MPC8349ITX
Timur Tabi2ad6b512006-10-31 18:44:42 -0600640#define CONFIG_HOSTNAME mpc8349emitx
Timur Tabi7a78f142007-01-31 15:54:29 -0600641#else
642#define CONFIG_HOSTNAME mpc8349emitxgp
643#endif
644
645/* Default path and filenames */
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600646#define CONFIG_ROOTPATH /nfsroot/rootfs
647#define CONFIG_BOOTFILE uImage
Timur Tabi7a78f142007-01-31 15:54:29 -0600648#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600649
Timur Tabi7a78f142007-01-31 15:54:29 -0600650#ifdef CONFIG_MPC8349ITX
651#define CONFIG_FDTFILE mpc8349emitx.dtb
Timur Tabi2ad6b512006-10-31 18:44:42 -0600652#else
Timur Tabi7a78f142007-01-31 15:54:29 -0600653#define CONFIG_FDTFILE mpc8349emitxgp.dtb
Timur Tabi2ad6b512006-10-31 18:44:42 -0600654#endif
655
Timur Tabi7a78f142007-01-31 15:54:29 -0600656#define CONFIG_BOOTDELAY 0
657
Timur Tabi2ad6b512006-10-31 18:44:42 -0600658#define XMK_STR(x) #x
659#define MK_STR(x) XMK_STR(x)
660
Timur Tabi98883332006-10-31 19:14:41 -0600661#define CONFIG_BOOTARGS \
662 "root=/dev/nfs rw" \
663 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
Timur Tabi7a78f142007-01-31 15:54:29 -0600664 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
Timur Tabi98883332006-10-31 19:14:41 -0600665 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
666 MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
667 " console=ttyS0," MK_STR(CONFIG_BAUDRATE)
668
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100669#define CONFIG_EXTRA_ENV_SETTINGS \
Timur Tabi7a78f142007-01-31 15:54:29 -0600670 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
671 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
672 "tftpflash=tftpboot $loadaddr $uboot; " \
673 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
674 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
675 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
676 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
677 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100678 "fdtaddr=400000\0" \
Timur Tabi7a78f142007-01-31 15:54:29 -0600679 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600680
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100681#define CONFIG_NFSBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600682 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
683 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
684 " console=$console,$baudrate $othbootargs; " \
685 "tftp $loadaddr $bootfile;" \
686 "tftp $fdtaddr $fdtfile;" \
687 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600688
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100689#define CONFIG_RAMBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600690 "setenv bootargs root=/dev/ram rw" \
691 " console=$console,$baudrate $othbootargs; " \
692 "tftp $ramdiskaddr $ramdiskfile;" \
693 "tftp $loadaddr $bootfile;" \
694 "tftp $fdtaddr $fdtfile;" \
695 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600696
697#undef MK_STR
698#undef XMK_STR
699
700#endif