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Sascha Hauercdace062008-03-26 20:40:49 +01001/*
Marek Vasutdb841402011-09-22 09:22:12 +00002 * i2c driver for Freescale i.MX series
Sascha Hauercdace062008-03-26 20:40:49 +01003 *
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
Marek Vasutdb841402011-09-22 09:22:12 +00005 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
12 *
Sascha Hauercdace062008-03-26 20:40:49 +010013 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Sascha Hauercdace062008-03-26 20:40:49 +010015 */
16
17#include <common.h>
Liu Hui-R64343127cec12011-01-03 22:27:39 +000018#include <asm/arch/clock.h>
Stefano Babic86271112011-03-14 15:43:56 +010019#include <asm/arch/imx-regs.h>
Troy Kiskycea60b02012-07-19 08:18:04 +000020#include <asm/errno.h>
Troy Kisky24cd7382012-07-19 08:18:03 +000021#include <asm/io.h>
Marek Vasutbf0783d2011-10-26 00:05:44 +000022#include <i2c.h>
Troy Kisky7aa57a02012-07-19 08:18:09 +000023#include <watchdog.h>
Sascha Hauercdace062008-03-26 20:40:49 +010024
York Sundec18612014-02-10 14:02:52 -080025DECLARE_GLOBAL_DATA_PTR;
26
Alison Wang30ea41a2013-06-17 15:30:39 +080027#ifdef I2C_QUIRK_REG
28struct mxc_i2c_regs {
29 uint8_t iadr;
30 uint8_t ifdr;
31 uint8_t i2cr;
32 uint8_t i2sr;
33 uint8_t i2dr;
34};
35#else
Marek Vasutdb841402011-09-22 09:22:12 +000036struct mxc_i2c_regs {
37 uint32_t iadr;
38 uint32_t ifdr;
39 uint32_t i2cr;
40 uint32_t i2sr;
41 uint32_t i2dr;
42};
Alison Wang30ea41a2013-06-17 15:30:39 +080043#endif
Sascha Hauercdace062008-03-26 20:40:49 +010044
Sascha Hauercdace062008-03-26 20:40:49 +010045#define I2CR_IIEN (1 << 6)
46#define I2CR_MSTA (1 << 5)
47#define I2CR_MTX (1 << 4)
48#define I2CR_TX_NO_AK (1 << 3)
49#define I2CR_RSTA (1 << 2)
50
51#define I2SR_ICF (1 << 7)
52#define I2SR_IBB (1 << 5)
Troy Kiskyd5383a62012-07-19 08:18:15 +000053#define I2SR_IAL (1 << 4)
Sascha Hauercdace062008-03-26 20:40:49 +010054#define I2SR_IIF (1 << 1)
55#define I2SR_RX_NO_AK (1 << 0)
56
Alison Wang30ea41a2013-06-17 15:30:39 +080057#ifdef I2C_QUIRK_REG
58#define I2CR_IEN (0 << 7)
59#define I2CR_IDIS (1 << 7)
60#define I2SR_IIF_CLEAR (1 << 1)
61#else
62#define I2CR_IEN (1 << 7)
63#define I2CR_IDIS (0 << 7)
64#define I2SR_IIF_CLEAR (0 << 1)
65#endif
66
Troy Kiskye4ff5252012-07-19 08:18:18 +000067#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
Troy Kiskyde6f6042012-04-24 17:33:25 +000068#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
Sascha Hauercdace062008-03-26 20:40:49 +010069#endif
70
Alison Wang30ea41a2013-06-17 15:30:39 +080071#ifdef I2C_QUIRK_REG
72static u16 i2c_clk_div[60][2] = {
73 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
74 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
75 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
76 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
77 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
78 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
79 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
80 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
81 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
82 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
83 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
84 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
85 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
86 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
87 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
88};
89#else
Marek Vasutdb841402011-09-22 09:22:12 +000090static u16 i2c_clk_div[50][2] = {
91 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
92 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
93 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
94 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
95 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
96 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
97 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
98 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
99 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
100 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
101 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
102 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
103 { 3072, 0x1E }, { 3840, 0x1F }
104};
Alison Wang30ea41a2013-06-17 15:30:39 +0800105#endif
Sascha Hauercdace062008-03-26 20:40:49 +0100106
tremfac96402013-09-21 18:13:35 +0200107
108#ifndef CONFIG_SYS_MXC_I2C1_SPEED
109#define CONFIG_SYS_MXC_I2C1_SPEED 100000
110#endif
111#ifndef CONFIG_SYS_MXC_I2C2_SPEED
112#define CONFIG_SYS_MXC_I2C2_SPEED 100000
113#endif
114#ifndef CONFIG_SYS_MXC_I2C3_SPEED
115#define CONFIG_SYS_MXC_I2C3_SPEED 100000
116#endif
York Sunf8cb1012015-03-20 10:20:40 -0700117#ifndef CONFIG_SYS_MXC_I2C4_SPEED
118#define CONFIG_SYS_MXC_I2C4_SPEED 100000
119#endif
tremfac96402013-09-21 18:13:35 +0200120
121#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
122#define CONFIG_SYS_MXC_I2C1_SLAVE 0
123#endif
124#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
125#define CONFIG_SYS_MXC_I2C2_SLAVE 0
126#endif
127#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
128#define CONFIG_SYS_MXC_I2C3_SLAVE 0
129#endif
York Sunf8cb1012015-03-20 10:20:40 -0700130#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
131#define CONFIG_SYS_MXC_I2C4_SLAVE 0
132#endif
tremfac96402013-09-21 18:13:35 +0200133
134
Marek Vasutdb841402011-09-22 09:22:12 +0000135/*
136 * Calculate and set proper clock divider
137 */
Marek Vasutbf0783d2011-10-26 00:05:44 +0000138static uint8_t i2c_imx_get_clk(unsigned int rate)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000139{
Marek Vasutdb841402011-09-22 09:22:12 +0000140 unsigned int i2c_clk_rate;
141 unsigned int div;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000142 u8 clk_div;
Sascha Hauercdace062008-03-26 20:40:49 +0100143
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000144#if defined(CONFIG_MX31)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000145 struct clock_control_regs *sc_regs =
146 (struct clock_control_regs *)CCM_BASE;
Marek Vasutdb841402011-09-22 09:22:12 +0000147
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100148 /* start the required I2C clock */
Troy Kiskyde6f6042012-04-24 17:33:25 +0000149 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
Stefano Babic1d549ad2011-01-20 07:50:44 +0000150 &sc_regs->cgr0);
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000151#endif
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100152
Marek Vasutdb841402011-09-22 09:22:12 +0000153 /* Divider value calculation */
Matthias Weissere7bed5c2012-09-24 02:46:53 +0000154 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
Marek Vasutdb841402011-09-22 09:22:12 +0000155 div = (i2c_clk_rate + rate - 1) / rate;
156 if (div < i2c_clk_div[0][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000157 clk_div = 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000158 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000159 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
Marek Vasutdb841402011-09-22 09:22:12 +0000160 else
Marek Vasutb567b8f2011-09-27 06:34:11 +0000161 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
Marek Vasutdb841402011-09-22 09:22:12 +0000162 ;
Sascha Hauercdace062008-03-26 20:40:49 +0100163
Marek Vasutdb841402011-09-22 09:22:12 +0000164 /* Store divider value */
Marek Vasutbf0783d2011-10-26 00:05:44 +0000165 return clk_div;
Marek Vasutdb841402011-09-22 09:22:12 +0000166}
Sascha Hauercdace062008-03-26 20:40:49 +0100167
Marek Vasutdb841402011-09-22 09:22:12 +0000168/*
Troy Kiskye4ff5252012-07-19 08:18:18 +0000169 * Set I2C Bus speed
Marek Vasutdb841402011-09-22 09:22:12 +0000170 */
Marek Vasut7f86bd52012-11-12 14:34:26 +0000171static int bus_i2c_set_bus_speed(void *base, int speed)
Marek Vasutdb841402011-09-22 09:22:12 +0000172{
Troy Kiskye4ff5252012-07-19 08:18:18 +0000173 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000174 u8 clk_idx = i2c_imx_get_clk(speed);
175 u8 idx = i2c_clk_div[clk_idx][1];
176
177 /* Store divider value */
178 writeb(idx, &i2c_regs->ifdr);
179
Troy Kisky83a1a192012-07-19 08:18:12 +0000180 /* Reset module */
Alison Wang30ea41a2013-06-17 15:30:39 +0800181 writeb(I2CR_IDIS, &i2c_regs->i2cr);
Troy Kisky83a1a192012-07-19 08:18:12 +0000182 writeb(0, &i2c_regs->i2sr);
Marek Vasutb567b8f2011-09-27 06:34:11 +0000183 return 0;
184}
185
Troy Kisky7aa57a02012-07-19 08:18:09 +0000186#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
187#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
188#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
189
190static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
Stefano Babic81687212011-01-20 07:51:31 +0000191{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000192 unsigned sr;
193 ulong elapsed;
194 ulong start_time = get_timer(0);
195 for (;;) {
196 sr = readb(&i2c_regs->i2sr);
Troy Kiskyd5383a62012-07-19 08:18:15 +0000197 if (sr & I2SR_IAL) {
Alison Wang30ea41a2013-06-17 15:30:39 +0800198#ifdef I2C_QUIRK_REG
199 writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
200#else
Troy Kiskyd5383a62012-07-19 08:18:15 +0000201 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
Alison Wang30ea41a2013-06-17 15:30:39 +0800202#endif
Troy Kiskyd5383a62012-07-19 08:18:15 +0000203 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
204 __func__, sr, readb(&i2c_regs->i2cr), state);
205 return -ERESTART;
206 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000207 if ((sr & (state >> 8)) == (unsigned char)state)
208 return sr;
209 WATCHDOG_RESET();
210 elapsed = get_timer(start_time);
211 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
212 break;
Stefano Babic81687212011-01-20 07:51:31 +0000213 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000214 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
215 sr, readb(&i2c_regs->i2cr), state);
Troy Kiskycea60b02012-07-19 08:18:04 +0000216 return -ETIMEDOUT;
Stefano Babic81687212011-01-20 07:51:31 +0000217}
218
Troy Kiskycea60b02012-07-19 08:18:04 +0000219static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
Sascha Hauercdace062008-03-26 20:40:49 +0100220{
Troy Kiskycea60b02012-07-19 08:18:04 +0000221 int ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100222
Alison Wang30ea41a2013-06-17 15:30:39 +0800223 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
Troy Kiskycea60b02012-07-19 08:18:04 +0000224 writeb(byte, &i2c_regs->i2dr);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000225 ret = wait_for_sr_state(i2c_regs, ST_IIF);
Troy Kiskycea60b02012-07-19 08:18:04 +0000226 if (ret < 0)
227 return ret;
Troy Kiskycea60b02012-07-19 08:18:04 +0000228 if (ret & I2SR_RX_NO_AK)
229 return -ENODEV;
230 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000231}
232
233/*
Troy Kisky90a5b702012-07-19 08:18:13 +0000234 * Stop I2C transaction
Marek Vasutdb841402011-09-22 09:22:12 +0000235 */
Troy Kisky27a5da02012-07-19 08:18:17 +0000236static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
Sascha Hauercdace062008-03-26 20:40:49 +0100237{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000238 int ret;
Troy Kisky90a5b702012-07-19 08:18:13 +0000239 unsigned int temp = readb(&i2c_regs->i2cr);
Sascha Hauercdace062008-03-26 20:40:49 +0100240
Troy Kisky1c076db2012-07-19 08:18:02 +0000241 temp &= ~(I2CR_MSTA | I2CR_MTX);
Marek Vasutdb841402011-09-22 09:22:12 +0000242 writeb(temp, &i2c_regs->i2cr);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000243 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
244 if (ret < 0)
245 printf("%s:trigger stop failed\n", __func__);
Sascha Hauercdace062008-03-26 20:40:49 +0100246}
247
Marek Vasutdb841402011-09-22 09:22:12 +0000248/*
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000249 * Send start signal, chip address and
250 * write register address
Marek Vasutdb841402011-09-22 09:22:12 +0000251 */
Troy Kiskya7f1a002012-07-19 08:18:16 +0000252static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000253 uchar chip, uint addr, int alen)
Sascha Hauercdace062008-03-26 20:40:49 +0100254{
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000255 unsigned int temp;
256 int ret;
257
258 /* Enable I2C controller */
Alison Wang30ea41a2013-06-17 15:30:39 +0800259#ifdef I2C_QUIRK_REG
260 if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
261#else
Troy Kisky90a5b702012-07-19 08:18:13 +0000262 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
Alison Wang30ea41a2013-06-17 15:30:39 +0800263#endif
Troy Kisky90a5b702012-07-19 08:18:13 +0000264 writeb(I2CR_IEN, &i2c_regs->i2cr);
265 /* Wait for controller to be stable */
266 udelay(50);
267 }
Troy Kiskyca741da2012-07-19 08:18:14 +0000268 if (readb(&i2c_regs->iadr) == (chip << 1))
269 writeb((chip << 1) ^ 2, &i2c_regs->iadr);
Alison Wang30ea41a2013-06-17 15:30:39 +0800270 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
Troy Kisky90a5b702012-07-19 08:18:13 +0000271 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
272 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000273 return ret;
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000274
275 /* Start I2C transaction */
276 temp = readb(&i2c_regs->i2cr);
277 temp |= I2CR_MSTA;
278 writeb(temp, &i2c_regs->i2cr);
279
280 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
281 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000282 return ret;
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000283
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000284 temp |= I2CR_MTX | I2CR_TX_NO_AK;
285 writeb(temp, &i2c_regs->i2cr);
286
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000287 /* write slave address */
288 ret = tx_byte(i2c_regs, chip << 1);
289 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000290 return ret;
Marek Vasutdb841402011-09-22 09:22:12 +0000291
Marek Vasutbf0783d2011-10-26 00:05:44 +0000292 while (alen--) {
Troy Kiskycea60b02012-07-19 08:18:04 +0000293 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
294 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000295 return ret;
Stefano Babic81687212011-01-20 07:51:31 +0000296 }
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000297 return 0;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000298}
299
Troy Kisky96c19bd2012-07-19 08:18:19 +0000300static int i2c_idle_bus(void *base);
301
Troy Kiskya7f1a002012-07-19 08:18:16 +0000302static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
303 uchar chip, uint addr, int alen)
304{
305 int retry;
306 int ret;
307 for (retry = 0; retry < 3; retry++) {
308 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
309 if (ret >= 0)
310 return 0;
Troy Kisky27a5da02012-07-19 08:18:17 +0000311 i2c_imx_stop(i2c_regs);
Troy Kiskya7f1a002012-07-19 08:18:16 +0000312 if (ret == -ENODEV)
313 return ret;
314
315 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
316 retry);
317 if (ret != -ERESTART)
Alison Wang30ea41a2013-06-17 15:30:39 +0800318 /* Disable controller */
319 writeb(I2CR_IDIS, &i2c_regs->i2cr);
Troy Kiskya7f1a002012-07-19 08:18:16 +0000320 udelay(100);
Troy Kisky96c19bd2012-07-19 08:18:19 +0000321 if (i2c_idle_bus(i2c_regs) < 0)
322 break;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000323 }
324 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
Marek Vasutdb841402011-09-22 09:22:12 +0000325 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100326}
327
Marek Vasutdb841402011-09-22 09:22:12 +0000328/*
Marek Vasutdb841402011-09-22 09:22:12 +0000329 * Read data from I2C device
330 */
Troy Kiskye4ff5252012-07-19 08:18:18 +0000331int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
332 int len)
Marek Vasutdb841402011-09-22 09:22:12 +0000333{
Marek Vasutdb841402011-09-22 09:22:12 +0000334 int ret;
335 unsigned int temp;
336 int i;
Troy Kiskye4ff5252012-07-19 08:18:18 +0000337 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
Marek Vasutdb841402011-09-22 09:22:12 +0000338
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000339 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
Troy Kiskycea60b02012-07-19 08:18:04 +0000340 if (ret < 0)
Marek Vasutdb841402011-09-22 09:22:12 +0000341 return ret;
342
Marek Vasutdb841402011-09-22 09:22:12 +0000343 temp = readb(&i2c_regs->i2cr);
344 temp |= I2CR_RSTA;
345 writeb(temp, &i2c_regs->i2cr);
346
Troy Kiskycea60b02012-07-19 08:18:04 +0000347 ret = tx_byte(i2c_regs, (chip << 1) | 1);
Troy Kiskyc4330d22012-07-19 08:18:07 +0000348 if (ret < 0) {
Troy Kisky27a5da02012-07-19 08:18:17 +0000349 i2c_imx_stop(i2c_regs);
Marek Vasutdb841402011-09-22 09:22:12 +0000350 return ret;
Troy Kiskyc4330d22012-07-19 08:18:07 +0000351 }
Marek Vasutdb841402011-09-22 09:22:12 +0000352
353 /* setup bus to read data */
354 temp = readb(&i2c_regs->i2cr);
355 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
356 if (len == 1)
357 temp |= I2CR_TX_NO_AK;
358 writeb(temp, &i2c_regs->i2cr);
Alison Wang30ea41a2013-06-17 15:30:39 +0800359 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
Troy Kiskyea572d82012-07-19 08:18:05 +0000360 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
Marek Vasutdb841402011-09-22 09:22:12 +0000361
362 /* read data */
363 for (i = 0; i < len; i++) {
Troy Kisky7aa57a02012-07-19 08:18:09 +0000364 ret = wait_for_sr_state(i2c_regs, ST_IIF);
365 if (ret < 0) {
Troy Kisky27a5da02012-07-19 08:18:17 +0000366 i2c_imx_stop(i2c_regs);
Marek Vasutdb841402011-09-22 09:22:12 +0000367 return ret;
Troy Kiskyc4330d22012-07-19 08:18:07 +0000368 }
Marek Vasutdb841402011-09-22 09:22:12 +0000369
370 /*
371 * It must generate STOP before read I2DR to prevent
372 * controller from generating another clock cycle
373 */
374 if (i == (len - 1)) {
Troy Kisky27a5da02012-07-19 08:18:17 +0000375 i2c_imx_stop(i2c_regs);
Marek Vasutdb841402011-09-22 09:22:12 +0000376 } else if (i == (len - 2)) {
377 temp = readb(&i2c_regs->i2cr);
378 temp |= I2CR_TX_NO_AK;
379 writeb(temp, &i2c_regs->i2cr);
380 }
Alison Wang30ea41a2013-06-17 15:30:39 +0800381 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
Marek Vasutdb841402011-09-22 09:22:12 +0000382 buf[i] = readb(&i2c_regs->i2dr);
383 }
Troy Kisky27a5da02012-07-19 08:18:17 +0000384 i2c_imx_stop(i2c_regs);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000385 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000386}
387
388/*
389 * Write data to I2C device
390 */
Troy Kiskye4ff5252012-07-19 08:18:18 +0000391int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
392 const uchar *buf, int len)
Sascha Hauercdace062008-03-26 20:40:49 +0100393{
Marek Vasutdb841402011-09-22 09:22:12 +0000394 int ret;
395 int i;
Troy Kiskye4ff5252012-07-19 08:18:18 +0000396 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
Sascha Hauercdace062008-03-26 20:40:49 +0100397
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000398 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
Troy Kiskycea60b02012-07-19 08:18:04 +0000399 if (ret < 0)
Marek Vasutdb841402011-09-22 09:22:12 +0000400 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100401
Marek Vasutdb841402011-09-22 09:22:12 +0000402 for (i = 0; i < len; i++) {
Troy Kiskycea60b02012-07-19 08:18:04 +0000403 ret = tx_byte(i2c_regs, buf[i]);
404 if (ret < 0)
Troy Kiskyc4330d22012-07-19 08:18:07 +0000405 break;
Marek Vasutdb841402011-09-22 09:22:12 +0000406 }
Troy Kisky27a5da02012-07-19 08:18:17 +0000407 i2c_imx_stop(i2c_regs);
Marek Vasutdb841402011-09-22 09:22:12 +0000408 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100409}
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000410
tremfac96402013-09-21 18:13:35 +0200411static void * const i2c_bases[] = {
412#if defined(CONFIG_MX25)
413 (void *)IMX_I2C_BASE,
414 (void *)IMX_I2C2_BASE,
415 (void *)IMX_I2C3_BASE
416#elif defined(CONFIG_MX27)
417 (void *)IMX_I2C1_BASE,
418 (void *)IMX_I2C2_BASE
419#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
420 defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
Wang Huandf0a5b82014-09-05 13:52:35 +0800421 defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
tremfac96402013-09-21 18:13:35 +0200422 (void *)I2C1_BASE_ADDR,
423 (void *)I2C2_BASE_ADDR,
424 (void *)I2C3_BASE_ADDR
425#elif defined(CONFIG_VF610)
426 (void *)I2C0_BASE_ADDR
York Sun2f78eae2014-06-23 15:15:54 -0700427#elif defined(CONFIG_FSL_LSCH3)
428 (void *)I2C1_BASE_ADDR,
429 (void *)I2C2_BASE_ADDR,
430 (void *)I2C3_BASE_ADDR,
431 (void *)I2C4_BASE_ADDR
Troy Kiskye4ff5252012-07-19 08:18:18 +0000432#else
tremfac96402013-09-21 18:13:35 +0200433#error "architecture not supported"
Troy Kiskye4ff5252012-07-19 08:18:18 +0000434#endif
tremfac96402013-09-21 18:13:35 +0200435};
436
Peng Fanc36ecf32015-01-06 14:12:51 +0800437struct i2c_parms {
438 void *base;
439 void *idle_bus_data;
440 int (*idle_bus_fn)(void *p);
441};
442
443struct sram_data {
444 unsigned curr_i2c_bus;
445 struct i2c_parms i2c_data[ARRAY_SIZE(i2c_bases)];
446};
447
tremfac96402013-09-21 18:13:35 +0200448void *i2c_get_base(struct i2c_adapter *adap)
449{
450 return i2c_bases[adap->hwadapnr];
Troy Kiskye4ff5252012-07-19 08:18:18 +0000451}
452
Troy Kisky96c19bd2012-07-19 08:18:19 +0000453static struct i2c_parms *i2c_get_parms(void *base)
454{
York Sundec18612014-02-10 14:02:52 -0800455 struct sram_data *srdata = (void *)gd->srdata;
Troy Kisky96c19bd2012-07-19 08:18:19 +0000456 int i = 0;
York Sundec18612014-02-10 14:02:52 -0800457 struct i2c_parms *p = srdata->i2c_data;
458 while (i < ARRAY_SIZE(srdata->i2c_data)) {
Troy Kisky96c19bd2012-07-19 08:18:19 +0000459 if (p->base == base)
460 return p;
461 p++;
462 i++;
463 }
464 printf("Invalid I2C base: %p\n", base);
465 return NULL;
466}
467
468static int i2c_idle_bus(void *base)
469{
470 struct i2c_parms *p = i2c_get_parms(base);
471 if (p && p->idle_bus_fn)
472 return p->idle_bus_fn(p->idle_bus_data);
473 return 0;
474}
475
tremfac96402013-09-21 18:13:35 +0200476static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
477 uint addr, int alen, uint8_t *buffer,
478 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000479{
tremfac96402013-09-21 18:13:35 +0200480 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kisky98153262012-07-19 08:18:20 +0000481}
482
tremfac96402013-09-21 18:13:35 +0200483static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
484 uint addr, int alen, uint8_t *buffer,
485 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000486{
tremfac96402013-09-21 18:13:35 +0200487 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000488}
489
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000490/*
491 * Test if a chip at a given address responds (probe the chip)
492 */
tremfac96402013-09-21 18:13:35 +0200493static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000494{
tremfac96402013-09-21 18:13:35 +0200495 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000496}
497
498void bus_i2c_init(void *base, int speed, int unused,
499 int (*idle_bus_fn)(void *p), void *idle_bus_data)
500{
York Sundec18612014-02-10 14:02:52 -0800501 struct sram_data *srdata = (void *)gd->srdata;
Troy Kiskye4ff5252012-07-19 08:18:18 +0000502 int i = 0;
York Sundec18612014-02-10 14:02:52 -0800503 struct i2c_parms *p = srdata->i2c_data;
Troy Kiskye4ff5252012-07-19 08:18:18 +0000504 if (!base)
505 return;
506 for (;;) {
507 if (!p->base || (p->base == base)) {
508 p->base = base;
509 if (idle_bus_fn) {
510 p->idle_bus_fn = idle_bus_fn;
511 p->idle_bus_data = idle_bus_data;
512 }
513 break;
514 }
515 p++;
516 i++;
York Sundec18612014-02-10 14:02:52 -0800517 if (i >= ARRAY_SIZE(srdata->i2c_data))
Troy Kiskye4ff5252012-07-19 08:18:18 +0000518 return;
519 }
520 bus_i2c_set_bus_speed(base, speed);
521}
522
523/*
524 * Init I2C Bus
525 */
tremfac96402013-09-21 18:13:35 +0200526static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000527{
tremfac96402013-09-21 18:13:35 +0200528 bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000529}
530
531/*
532 * Set I2C Speed
533 */
tremfac96402013-09-21 18:13:35 +0200534static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000535{
tremfac96402013-09-21 18:13:35 +0200536 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000537}
538
539/*
tremfac96402013-09-21 18:13:35 +0200540 * Register mxc i2c adapters
Troy Kiskye4ff5252012-07-19 08:18:18 +0000541 */
tremfac96402013-09-21 18:13:35 +0200542U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
543 mxc_i2c_read, mxc_i2c_write,
544 mxc_i2c_set_bus_speed,
545 CONFIG_SYS_MXC_I2C1_SPEED,
546 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
547U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
548 mxc_i2c_read, mxc_i2c_write,
549 mxc_i2c_set_bus_speed,
550 CONFIG_SYS_MXC_I2C2_SPEED,
551 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
York Sunf8cb1012015-03-20 10:20:40 -0700552#ifdef CONFIG_SYS_I2C_MXC_I2C3
tremfac96402013-09-21 18:13:35 +0200553U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
554 mxc_i2c_read, mxc_i2c_write,
555 mxc_i2c_set_bus_speed,
556 CONFIG_SYS_MXC_I2C3_SPEED,
557 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
558#endif
York Sunf8cb1012015-03-20 10:20:40 -0700559#ifdef CONFIG_SYS_I2C_MXC_I2C4
560U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
561 mxc_i2c_read, mxc_i2c_write,
562 mxc_i2c_set_bus_speed,
563 CONFIG_SYS_MXC_I2C4_SPEED,
564 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
565#endif