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gerrit.cesnet.cz / github / trini / u-boot / 1001502545ff0125c39232cf0e7f26d9213ab55f / . / arch / riscv / Kconfig
blob: 0d04d91ad49517f10962180105a0009ccfe41d4a [file] [log] [blame]
Bin Meng117a4332018-09-26 06:55:06 -0700[diff] [blame]1menu "RISC-V architecture"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]2 depends on RISCV
3
4config SYS_ARCH
5 default "riscv"
6
7choice
8 prompt "Target select"
9 optional
10
Rick Chen6f4dd622018-05-29 09:54:40 +0800[diff] [blame]11config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]13
Bin Meng510e3792018-09-26 06:55:21 -0700[diff] [blame]14config TARGET_QEMU_VIRT
15 bool "Support QEMU Virt Board"
16
Anup Patel3fda0262019-02-25 08:15:19 +0000[diff] [blame]17config TARGET_SIFIVE_FU540
18 bool "Support SiFive FU540 Board"
19
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]20endchoice
21
Trevor Woernera0aba8a2019-05-03 09:40:59 -0400[diff] [blame]22config SYS_ICACHE_OFF
23 bool "Do not enable icache"
24 default n
25 help
26 Do not enable instruction cache in U-Boot.
27
Trevor Woerner10015022019-05-03 09:41:00 -0400[diff] [blame^]28config SPL_SYS_ICACHE_OFF
29 bool "Do not enable icache in SPL"
30 depends on SPL
31 default SYS_ICACHE_OFF
32 help
33 Do not enable instruction cache in SPL.
34
Trevor Woernera0aba8a2019-05-03 09:40:59 -0400[diff] [blame]35config SYS_DCACHE_OFF
36 bool "Do not enable dcache"
37 default n
38 help
39 Do not enable data cache in U-Boot.
40
Trevor Woerner10015022019-05-03 09:41:00 -0400[diff] [blame^]41config SPL_SYS_DCACHE_OFF
42 bool "Do not enable dcache in SPL"
43 depends on SPL
44 default SYS_DCACHE_OFF
45 help
46 Do not enable data cache in SPL.
47
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]48# board-specific options below
Rick Chen6f4dd622018-05-29 09:54:40 +0800[diff] [blame]49source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng510e3792018-09-26 06:55:21 -0700[diff] [blame]50source "board/emulation/qemu-riscv/Kconfig"
Anup Patel3fda0262019-02-25 08:15:19 +0000[diff] [blame]51source "board/sifive/fu540/Kconfig"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]52
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]53# platform-specific options below
54source "arch/riscv/cpu/ax25/Kconfig"
Anup Patelfdff1f92019-02-25 08:14:10 +0000[diff] [blame]55source "arch/riscv/cpu/generic/Kconfig"
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]56
57# architecture-specific options below
58
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]59choice
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]60 prompt "Base ISA"
61 default ARCH_RV32I
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]62
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]63config ARCH_RV32I
64 bool "RV32I"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]65 select 32BIT
66 help
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]67 Choose this option to target the RV32I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]68
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]69config ARCH_RV64I
70 bool "RV64I"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]71 select 64BIT
Lukas Auer71158562018-11-22 11:26:13 +0100[diff] [blame]72 select PHYS_64BIT
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]73 help
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]74 Choose this option to target the RV64I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]75
76endchoice
77
Lukas Auer8176ea42018-12-12 06:12:23 -0800[diff] [blame]78choice
79 prompt "Code Model"
80 default CMODEL_MEDLOW
81
82config CMODEL_MEDLOW
83 bool "medium low code model"
84 help
85 U-Boot and its statically defined symbols must lie within a single 2 GiB
86 address range and must lie between absolute addresses -2 GiB and +2 GiB.
87
88config CMODEL_MEDANY
89 bool "medium any code model"
90 help
91 U-Boot and its statically defined symbols must be within any single 2 GiB
92 address range.
93
94endchoice
95
Anup Patel3cfc8252018-12-12 06:12:29 -0800[diff] [blame]96choice
97 prompt "Run Mode"
98 default RISCV_MMODE
99
100config RISCV_MMODE
101 bool "Machine"
102 help
103 Choose this option to build U-Boot for RISC-V M-Mode.
104
105config RISCV_SMODE
106 bool "Supervisor"
107 help
108 Choose this option to build U-Boot for RISC-V S-Mode.
109
110endchoice
111
Lukas Auerd57ffa62018-11-22 11:26:14 +0100[diff] [blame]112config RISCV_ISA_C
113 bool "Emit compressed instructions"
114 default y
115 help
116 Adds "C" to the ISA subsets that the toolchain is allowed to emit
117 when building U-Boot, which results in compressed instructions in the
118 U-Boot binary.
119
120config RISCV_ISA_A
121 def_bool y
122
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]123config 32BIT
124 bool
125
126config 64BIT
127 bool
128
Bin Meng644a3cd2018-12-12 06:12:30 -0800[diff] [blame]129config SIFIVE_CLINT
130 bool
131 depends on RISCV_MMODE
132 select REGMAP
133 select SYSCON
134 help
135 The SiFive CLINT block holds memory-mapped control and status registers
136 associated with software and timer interrupts.
137
Rick Chen0d389462019-04-02 15:56:39 +0800[diff] [blame]138config ANDES_PLIC
139 bool
140 depends on RISCV_MMODE
141 select REGMAP
142 select SYSCON
143 help
144 The Andes PLIC block holds memory-mapped claim and pending registers
145 associated with software interrupt.
146
Rick Chena1f24872019-04-02 15:56:40 +0800[diff] [blame]147config ANDES_PLMT
148 bool
149 depends on RISCV_MMODE
150 select REGMAP
151 select SYSCON
152 help
153 The Andes PLMT block holds memory-mapped mtime register
154 associated with timer tick.
155
Anup Patel511107d2018-12-12 06:12:31 -0800[diff] [blame]156config RISCV_RDTIME
157 bool
158 default y if RISCV_SMODE
159 help
160 The provides the riscv_get_time() API that is implemented using the
161 standard rdtime instruction. This is the case for S-mode U-Boot, and
162 is useful for processors that support rdtime in M-mode too.
163
Bin Meng92b64fe2018-12-12 06:12:33 -0800[diff] [blame]164config SYS_MALLOC_F_LEN
165 default 0x1000
166
Lukas Auerfa33f082019-03-17 19:28:32 +0100[diff] [blame]167config SMP
168 bool "Symmetric Multi-Processing"
169 help
170 This enables support for systems with more than one CPU. If
171 you say N here, U-Boot will run on single and multiprocessor
172 machines, but will use only one CPU of a multiprocessor
173 machine. If you say Y here, U-Boot will run on many, but not
174 all, single processor machines.
175
176config NR_CPUS
177 int "Maximum number of CPUs (2-32)"
178 range 2 32
179 depends on SMP
180 default 8
181 help
182 On multiprocessor machines, U-Boot sets up a stack for each CPU.
183 Stack memory is pre-allocated. U-Boot must therefore know the
184 maximum number of CPUs that may be present.
185
Lukas Auerf152feb2019-03-17 19:28:34 +0100[diff] [blame]186config SBI_IPI
187 bool
188 default y if RISCV_SMODE
189 depends on SMP
190
Rick Chenbdce3892019-04-30 13:49:33 +0800[diff] [blame]191config XIP
192 bool "XIP mode"
193 help
194 XIP (eXecute In Place) is a method for executing code directly
195 from a NOR flash memory without copying the code to ram.
196 Say yes here if U-Boot boots from flash directly.
197
Lukas Auer3dea63c2019-03-17 19:28:37 +0100[diff] [blame]198config STACK_SIZE_SHIFT
199 int
200 default 13
201
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]202endmenu