| Bin Meng | 117a433 | 2018-09-26 06:55:06 -0700 | [diff] [blame^] | 1 | menu "RISC-V architecture" |
| Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 2 | depends on RISCV |
| 3 | |||||
| 4 | config SYS_ARCH | ||||
| 5 | default "riscv" | ||||
| 6 | |||||
| 7 | choice | ||||
| 8 | prompt "Target select" | ||||
| 9 | optional | ||||
| 10 | |||||
| Rick Chen | 6f4dd62 | 2018-05-29 09:54:40 +0800 | [diff] [blame] | 11 | config TARGET_AX25_AE350 |
| 12 | bool "Support ax25-ae350" | ||||
| Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 13 | |
| 14 | endchoice | ||||
| 15 | |||||
| Rick Chen | 6f4dd62 | 2018-05-29 09:54:40 +0800 | [diff] [blame] | 16 | source "board/AndesTech/ax25-ae350/Kconfig" |
| Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 17 | |
| 18 | choice | ||||
| 19 | prompt "CPU selection" | ||||
| 20 | default CPU_RISCV_32 | ||||
| 21 | |||||
| 22 | config CPU_RISCV_32 | ||||
| Bin Meng | 117a433 | 2018-09-26 06:55:06 -0700 | [diff] [blame^] | 23 | bool "RISC-V 32-bit" |
| Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 24 | select 32BIT |
| 25 | help | ||||
| 26 | Choose this option to build an U-Boot for RISCV32 architecture. | ||||
| 27 | |||||
| 28 | config CPU_RISCV_64 | ||||
| Bin Meng | 117a433 | 2018-09-26 06:55:06 -0700 | [diff] [blame^] | 29 | bool "RISC-V 64-bit" |
| Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 30 | select 64BIT |
| 31 | help | ||||
| 32 | Choose this option to build an U-Boot for RISCV64 architecture. | ||||
| 33 | |||||
| 34 | endchoice | ||||
| 35 | |||||
| 36 | config 32BIT | ||||
| 37 | bool | ||||
| 38 | |||||
| 39 | config 64BIT | ||||
| 40 | bool | ||||
| 41 | |||||
| 42 | endmenu | ||||