blob: 2014e3770a169c9a6b69caa8c3b56a9d22286a99 [file] [log] [blame]
Heiko Schocher62ddcf02010-02-18 08:08:25 +01001/*
2 * (C) Copyright 2010
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#ifndef __CONFIG_KM83XX_H
12#define __CONFIG_KM83XX_H
13
14/* include common defines/options for all Keymile boards */
15#include "keymile-common.h"
16#include "km-powerpc.h"
17
18#define MTDIDS_DEFAULT "nor0=boot"
19#define MTDPARTS_DEFAULT "mtdparts=" \
20 "boot:" \
21 "768k(u-boot)," \
22 "128k(env)," \
23 "128k(envred)," \
24 "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
25
26#define CONFIG_MISC_INIT_R
27/*
28 * System Clock Setup
29 */
30#define CONFIG_83XX_CLKIN 66000000
31#define CONFIG_SYS_CLK_FREQ 66000000
32#define CONFIG_83XX_PCICLK 66000000
33
34/*
35 * IMMR new address
36 */
37#define CONFIG_SYS_IMMR 0xE0000000
38
39/*
40 * Bus Arbitration Configuration Register (ACR)
41 */
42#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
43#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
44#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
45#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
46
47/*
48 * DDR Setup
49 */
50#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
51#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
52#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
53#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
54 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
55
56#define CFG_83XX_DDR_USES_CS0
57
58/*
59 * Manually set up DDR parameters
60 */
61#define CONFIG_DDR_II
62#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
63
64/*
65 * The reserved memory
66 */
67#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
68#define CONFIG_SYS_FLASH_BASE 0xF0000000
69
70#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
71#define CONFIG_SYS_RAMBOOT
72#endif
73
74/* Reserve 768 kB for Mon */
75#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
76
77/*
78 * Initial RAM Base Address Setup
79 */
80#define CONFIG_SYS_INIT_RAM_LOCK
81#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
82#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
83#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
84#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
85 GENERATED_GBL_DATA_SIZE)
86
87/*
88 * Init Local Bus Memory Controller:
89 *
90 * Bank Bus Machine PortSz Size Device
91 * ---- --- ------- ------ ----- ------
92 * 0 Local GPCM 16 bit 256MB FLASH
93 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
94 *
95 */
96/*
97 * FLASH on the Local Bus
98 */
99#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
100#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
101#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
102#define CONFIG_SYS_FLASH_PROTECTION
103#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
104
105#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
106#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
107
108#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
109 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
110 BR_V)
111
112#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
113 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
114 OR_GPCM_SCY_5 | \
115 OR_GPCM_TRLX | OR_GPCM_EAD)
116
117#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
118#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
119#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
120
121/*
122 * PRIO1/PIGGY on the local bus CS1
123 */
Heiko Schocher8ed74342011-03-08 10:47:39 +0100124/* Window base at flash base */
125#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100126#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
127
Heiko Schocher8ed74342011-03-08 10:47:39 +0100128#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100129 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
130 BR_V)
Heiko Schocher8ed74342011-03-08 10:47:39 +0100131#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100132 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
133 OR_GPCM_SCY_2 | \
134 OR_GPCM_TRLX | OR_GPCM_EAD)
135
136/*
137 * Serial Port
138 */
139#define CONFIG_CONS_INDEX 1
140#define CONFIG_SYS_NS16550
141#define CONFIG_SYS_NS16550_SERIAL
142#define CONFIG_SYS_NS16550_REG_SIZE 1
143#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
144
145#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
146#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
147
148/* Pass open firmware flat tree */
149#define CONFIG_OF_LIBFDT
150#define CONFIG_OF_BOARD_SETUP
151#define CONFIG_OF_STDOUT_VIA_ALIAS
152
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100153/*
154 * QE UEC ethernet configuration
155 */
156#define CONFIG_UEC_ETH
157#define CONFIG_ETHPRIME "UEC0"
158
159#define CONFIG_UEC_ETH1 /* GETH1 */
160#define UEC_VERBOSE_DEBUG 1
161
162#ifdef CONFIG_UEC_ETH1
163#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
164#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
165#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
166#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
167#define CONFIG_SYS_UEC1_PHY_ADDR 0
168#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
169#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
170#endif
171
172/*
173 * Environment
174 */
175
176#ifndef CONFIG_SYS_RAMBOOT
177#define CONFIG_ENV_IS_IN_FLASH
178#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
179 CONFIG_SYS_MONITOR_LEN)
180#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
181#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
182
183/* Address and size of Redundant Environment Sector */
184#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
185 CONFIG_ENV_SECT_SIZE)
186#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
187
188#else /* CFG_SYS_RAMBOOT */
189#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
190#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
191#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
192#define CONFIG_ENV_SIZE 0x2000
193#endif /* CFG_SYS_RAMBOOT */
194
195/* I2C */
196#define CONFIG_HARD_I2C /* I2C with hardware support */
197#define CONFIG_FSL_I2C
198#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
199#define CONFIG_SYS_I2C_SLAVE 0x7F
200#define CONFIG_SYS_I2C_OFFSET 0x3000
201
202/* I2C SYSMON (LM75, AD7414 is almost compatible) */
203#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
204#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
205#define CONFIG_SYS_DTT_MAX_TEMP 70
206#define CONFIG_SYS_DTT_LOW_TEMP -30
207#define CONFIG_SYS_DTT_HYSTERESIS 3
208#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
209
210#if defined(CONFIG_CMD_NAND)
211#define CONFIG_NAND_KMETER1
212#define CONFIG_SYS_MAX_NAND_DEVICE 1
Heiko Schocher8ed74342011-03-08 10:47:39 +0100213#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100214#endif
215
216#if defined(CONFIG_PCI)
217#define CONFIG_CMD_PCI
218#endif
219
220/*
221 * For booting Linux, the board info and command line data
222 * have to be in the first 8 MB of memory, since this is
223 * the maximum mapped by the Linux kernel during initialization.
224 */
225#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
226
227/*
228 * Core HID Setup
229 */
230#define CONFIG_SYS_HID0_INIT 0x000000000
231#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
232 HID0_ENABLE_INSTRUCTION_CACHE)
233#define CONFIG_SYS_HID2 HID2_HBE
234
235/*
236 * MMU Setup
237 */
238
239#define CONFIG_HIGH_BATS 1 /* High BATs supported */
240
241/* DDR: cache cacheable */
242#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
243 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
244#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
245 BATU_VS | BATU_VP)
246#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
247#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
248
249/* IMMRBAR & PCI IO: cache-inhibit and guarded */
250#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
251 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
252#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
253 | BATU_VP)
254#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
255#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
256
257/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
Heiko Schocher8ed74342011-03-08 10:47:39 +0100258#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
259 BATL_MEMCOHERENCE)
260#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
261 BATU_VS | BATU_VP)
262#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100263 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
264#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
265
266/* FLASH: icache cacheable, but dcache-inhibit and guarded */
267#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
268 BATL_MEMCOHERENCE)
269#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
270 BATU_VS | BATU_VP)
271#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
272 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
273#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
274
275/* Stack in dcache: cacheable, no memory coherence */
276#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
277#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
278 BATU_VS | BATU_VP)
279#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
280#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
281
282/*
283 * Internal Definitions
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100284 */
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100285#define BOOTFLASH_START 0xF0000000
286
287#define CONFIG_KM_CONSOLE_TTY "ttyS0"
288
289/*
290 * Environment Configuration
291 */
292#define CONFIG_ENV_OVERWRITE
293#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
294#define CONFIG_KM_DEF_ENV "km-common=empty\0"
295#endif
296
Holger Brunckb648bfc2011-07-04 21:52:52 +0000297#ifndef CONFIG_KM_DEF_ARCH
298#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100299#endif
300
301#define CONFIG_EXTRA_ENV_SETTINGS \
302 CONFIG_KM_DEF_ENV \
Holger Brunckb648bfc2011-07-04 21:52:52 +0000303 CONFIG_KM_DEF_ARCH \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100304 "dtt_bus=pca9547:70:a\0" \
305 "EEprom_ivm=pca9547:70:9\0" \
306 "newenv=" \
307 "prot off 0xF00C0000 +0x40000 && " \
308 "era 0xF00C0000 +0x40000\0" \
309 "unlock=yes\0" \
310 ""
311
312#if defined(CONFIG_UEC_ETH)
313#define CONFIG_HAS_ETH0
314#endif
315
316#endif /* __CONFIG_KM83XX_H */