Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
| 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
Dinh Nguyen | 0ef44d1 | 2015-04-15 16:44:32 -0500 | [diff] [blame] | 9 | #include <asm/pl310.h> |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 10 | #include <asm/u-boot.h> |
| 11 | #include <asm/utils.h> |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 12 | #include <image.h> |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 13 | #include <asm/arch/reset_manager.h> |
| 14 | #include <spl.h> |
Chin Liang See | 5d649d2 | 2013-09-11 11:24:48 -0500 | [diff] [blame] | 15 | #include <asm/arch/system_manager.h> |
Chin Liang See | 4c54419 | 2013-12-02 12:01:39 -0600 | [diff] [blame] | 16 | #include <asm/arch/freeze_controller.h> |
Chin Liang See | 3ab019e | 2014-07-22 04:28:35 -0500 | [diff] [blame] | 17 | #include <asm/arch/clock_manager.h> |
| 18 | #include <asm/arch/scan_manager.h> |
Dinh Nguyen | 37ef0c7 | 2015-03-30 17:01:08 -0500 | [diff] [blame] | 19 | #include <asm/arch/sdram.h> |
Marek Vasut | 232fcc6 | 2015-07-09 05:15:40 +0200 | [diff] [blame] | 20 | #include <asm/arch/scu.h> |
| 21 | #include <asm/arch/nic301.h> |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 22 | |
| 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
Dinh Nguyen | 0ef44d1 | 2015-04-15 16:44:32 -0500 | [diff] [blame] | 25 | static struct pl310_regs *const pl310 = |
| 26 | (struct pl310_regs *)CONFIG_SYS_PL310_BASE; |
Marek Vasut | 232fcc6 | 2015-07-09 05:15:40 +0200 | [diff] [blame] | 27 | static struct scu_registers *scu_regs = |
| 28 | (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; |
| 29 | static struct nic301_registers *nic301_regs = |
| 30 | (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; |
Marek Vasut | 066ad14 | 2015-07-21 16:11:16 +0200 | [diff] [blame^] | 31 | static struct socfpga_system_manager *sysmgr_regs = |
| 32 | (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
Marek Vasut | 232fcc6 | 2015-07-09 05:15:40 +0200 | [diff] [blame] | 33 | |
Marek Vasut | 6473054 | 2015-07-09 05:36:23 +0200 | [diff] [blame] | 34 | u32 spl_boot_device(void) |
| 35 | { |
Marek Vasut | 066ad14 | 2015-07-21 16:11:16 +0200 | [diff] [blame^] | 36 | const u32 bsel = readl(&sysmgr_regs->bootinfo); |
| 37 | |
| 38 | switch (bsel & 0x7) { |
| 39 | case 0x1: /* FPGA (HPS2FPGA Bridge) */ |
| 40 | return BOOT_DEVICE_RAM; |
| 41 | case 0x2: /* NAND Flash (1.8V) */ |
| 42 | case 0x3: /* NAND Flash (3.0V) */ |
| 43 | return BOOT_DEVICE_NAND; |
| 44 | case 0x4: /* SD/MMC External Transceiver (1.8V) */ |
| 45 | case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ |
| 46 | socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); |
| 47 | socfpga_per_reset(SOCFPGA_RESET(DMA), 0); |
| 48 | return BOOT_DEVICE_MMC1; |
| 49 | case 0x6: /* QSPI Flash (1.8V) */ |
| 50 | case 0x7: /* QSPI Flash (3.0V) */ |
| 51 | socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); |
| 52 | return BOOT_DEVICE_SPI; |
| 53 | default: |
| 54 | printf("Invalid boot device (bsel=%08x)!\n", bsel); |
| 55 | hang(); |
| 56 | } |
Marek Vasut | 6473054 | 2015-07-09 05:36:23 +0200 | [diff] [blame] | 57 | } |
| 58 | |
Marek Vasut | d3f34e7 | 2015-07-10 00:04:23 +0200 | [diff] [blame] | 59 | #ifdef CONFIG_SPL_MMC_SUPPORT |
| 60 | u32 spl_boot_mode(void) |
| 61 | { |
| 62 | #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) |
| 63 | return MMCSD_MODE_FS; |
| 64 | #else |
| 65 | return MMCSD_MODE_RAW; |
| 66 | #endif |
| 67 | } |
| 68 | #endif |
| 69 | |
Marek Vasut | 232fcc6 | 2015-07-09 05:15:40 +0200 | [diff] [blame] | 70 | static void socfpga_nic301_slave_ns(void) |
| 71 | { |
| 72 | writel(0x1, &nic301_regs->lwhps2fpgaregs); |
| 73 | writel(0x1, &nic301_regs->hps2fpgaregs); |
| 74 | writel(0x1, &nic301_regs->acp); |
| 75 | writel(0x1, &nic301_regs->rom); |
| 76 | writel(0x1, &nic301_regs->ocram); |
| 77 | writel(0x1, &nic301_regs->sdrdata); |
| 78 | } |
Dinh Nguyen | 0ef44d1 | 2015-04-15 16:44:32 -0500 | [diff] [blame] | 79 | |
Dinh Nguyen | 0ef44d1 | 2015-04-15 16:44:32 -0500 | [diff] [blame] | 80 | void board_init_f(ulong dummy) |
| 81 | { |
Marek Vasut | 6473054 | 2015-07-09 05:36:23 +0200 | [diff] [blame] | 82 | #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET |
| 83 | const struct cm_config *cm_default_cfg = cm_get_default_config(); |
| 84 | #endif |
Marek Vasut | 6473054 | 2015-07-09 05:36:23 +0200 | [diff] [blame] | 85 | unsigned long sdram_size; |
Dinh Nguyen | 0ef44d1 | 2015-04-15 16:44:32 -0500 | [diff] [blame] | 86 | unsigned long reg; |
Marek Vasut | 6473054 | 2015-07-09 05:36:23 +0200 | [diff] [blame] | 87 | |
Dinh Nguyen | 0ef44d1 | 2015-04-15 16:44:32 -0500 | [diff] [blame] | 88 | /* |
| 89 | * First C code to run. Clear fake OCRAM ECC first as SBE |
| 90 | * and DBE might triggered during power on |
| 91 | */ |
| 92 | reg = readl(&sysmgr_regs->eccgrp_ocram); |
| 93 | if (reg & SYSMGR_ECC_OCRAM_SERR) |
| 94 | writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, |
| 95 | &sysmgr_regs->eccgrp_ocram); |
| 96 | if (reg & SYSMGR_ECC_OCRAM_DERR) |
| 97 | writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, |
| 98 | &sysmgr_regs->eccgrp_ocram); |
| 99 | |
| 100 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 101 | |
Marek Vasut | 232fcc6 | 2015-07-09 05:15:40 +0200 | [diff] [blame] | 102 | socfpga_nic301_slave_ns(); |
| 103 | |
| 104 | /* Configure ARM MPU SNSAC register. */ |
| 105 | setbits_le32(&scu_regs->sacr, 0xfff); |
| 106 | |
Dinh Nguyen | 0ef44d1 | 2015-04-15 16:44:32 -0500 | [diff] [blame] | 107 | /* Remap SDRAM to 0x0 */ |
Marek Vasut | 232fcc6 | 2015-07-09 05:15:40 +0200 | [diff] [blame] | 108 | writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ |
Dinh Nguyen | 0ef44d1 | 2015-04-15 16:44:32 -0500 | [diff] [blame] | 109 | writel(0x1, &pl310->pl310_addr_filter_start); |
| 110 | |
Chin Liang See | 5d649d2 | 2013-09-11 11:24:48 -0500 | [diff] [blame] | 111 | #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET |
Chin Liang See | 4c54419 | 2013-12-02 12:01:39 -0600 | [diff] [blame] | 112 | debug("Freezing all I/O banks\n"); |
| 113 | /* freeze all IO banks */ |
| 114 | sys_mgr_frzctrl_freeze_req(); |
| 115 | |
Marek Vasut | bd65fe3 | 2015-07-09 05:21:02 +0200 | [diff] [blame] | 116 | /* Put everything into reset but L4WD0. */ |
| 117 | socfpga_per_reset_all(); |
| 118 | /* Put FPGA bridges into reset too. */ |
| 119 | socfpga_bridges_reset(1); |
| 120 | |
Marek Vasut | a71df7a | 2015-07-09 02:51:56 +0200 | [diff] [blame] | 121 | socfpga_per_reset(SOCFPGA_RESET(SDR), 0); |
| 122 | socfpga_per_reset(SOCFPGA_RESET(UART0), 0); |
| 123 | socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); |
Dinh Nguyen | 0812a1d | 2015-03-30 17:01:05 -0500 | [diff] [blame] | 124 | |
Dinh Nguyen | 9fd565d | 2015-03-30 17:01:06 -0500 | [diff] [blame] | 125 | timer_init(); |
| 126 | |
Chin Liang See | ddfeb0a | 2014-03-04 22:13:53 -0600 | [diff] [blame] | 127 | debug("Reconfigure Clock Manager\n"); |
| 128 | /* reconfigure the PLLs */ |
Marek Vasut | 93b4abd | 2015-07-25 08:44:27 +0200 | [diff] [blame] | 129 | cm_basic_init(cm_default_cfg); |
Chin Liang See | ddfeb0a | 2014-03-04 22:13:53 -0600 | [diff] [blame] | 130 | |
Dinh Nguyen | 08e463e | 2015-03-30 17:01:07 -0500 | [diff] [blame] | 131 | /* Enable bootrom to configure IOs. */ |
Marek Vasut | 40687b4 | 2015-07-09 04:40:11 +0200 | [diff] [blame] | 132 | sysmgr_config_warmrstcfgio(1); |
Dinh Nguyen | 08e463e | 2015-03-30 17:01:07 -0500 | [diff] [blame] | 133 | |
Chin Liang See | dc4d4aa | 2014-06-10 01:17:42 -0500 | [diff] [blame] | 134 | /* configure the IOCSR / IO buffer settings */ |
| 135 | if (scan_mgr_configure_iocsr()) |
| 136 | hang(); |
| 137 | |
Marek Vasut | 4a0080d | 2015-07-09 04:48:56 +0200 | [diff] [blame] | 138 | sysmgr_config_warmrstcfgio(0); |
| 139 | |
Chin Liang See | 5d649d2 | 2013-09-11 11:24:48 -0500 | [diff] [blame] | 140 | /* configure the pin muxing through system manager */ |
Marek Vasut | 4a0080d | 2015-07-09 04:48:56 +0200 | [diff] [blame] | 141 | sysmgr_config_warmrstcfgio(1); |
Chin Liang See | 5d649d2 | 2013-09-11 11:24:48 -0500 | [diff] [blame] | 142 | sysmgr_pinmux_init(); |
Marek Vasut | 4a0080d | 2015-07-09 04:48:56 +0200 | [diff] [blame] | 143 | sysmgr_config_warmrstcfgio(0); |
| 144 | |
Chin Liang See | 5d649d2 | 2013-09-11 11:24:48 -0500 | [diff] [blame] | 145 | #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ |
| 146 | |
Marek Vasut | bd65fe3 | 2015-07-09 05:21:02 +0200 | [diff] [blame] | 147 | /* De-assert reset for peripherals and bridges based on handoff */ |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 148 | reset_deassert_peripherals_handoff(); |
Marek Vasut | bd65fe3 | 2015-07-09 05:21:02 +0200 | [diff] [blame] | 149 | socfpga_bridges_reset(0); |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 150 | |
Chin Liang See | 4c54419 | 2013-12-02 12:01:39 -0600 | [diff] [blame] | 151 | debug("Unfreezing/Thaw all I/O banks\n"); |
| 152 | /* unfreeze / thaw all IO banks */ |
| 153 | sys_mgr_frzctrl_thaw_req(); |
| 154 | |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 155 | /* enable console uart printing */ |
| 156 | preloader_console_init(); |
Dinh Nguyen | 37ef0c7 | 2015-03-30 17:01:08 -0500 | [diff] [blame] | 157 | |
| 158 | if (sdram_mmr_init_full(0xffffffff) != 0) { |
| 159 | puts("SDRAM init failed.\n"); |
| 160 | hang(); |
| 161 | } |
| 162 | |
| 163 | debug("SDRAM: Calibrating PHY\n"); |
| 164 | /* SDRAM calibration */ |
| 165 | if (sdram_calibration_full() == 0) { |
| 166 | puts("SDRAM calibration failed.\n"); |
| 167 | hang(); |
| 168 | } |
Dinh Nguyen | 89ba824 | 2015-03-30 17:01:09 -0500 | [diff] [blame] | 169 | |
| 170 | sdram_size = sdram_calculate_size(); |
| 171 | debug("SDRAM: %ld MiB\n", sdram_size >> 20); |
Dinh Nguyen | 9ad3a4a | 2015-03-30 17:01:15 -0500 | [diff] [blame] | 172 | |
| 173 | /* Sanity check ensure correct SDRAM size specified */ |
| 174 | if (get_ram_size(0, sdram_size) != sdram_size) { |
| 175 | puts("SDRAM size check failed!\n"); |
| 176 | hang(); |
| 177 | } |
Marek Vasut | bd65fe3 | 2015-07-09 05:21:02 +0200 | [diff] [blame] | 178 | |
| 179 | socfpga_bridges_reset(1); |
Marek Vasut | 6473054 | 2015-07-09 05:36:23 +0200 | [diff] [blame] | 180 | |
| 181 | board_init_r(NULL, 0); |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 182 | } |