blob: a760c5bdda68d9e8bac3893babf06f9f07d63ad2 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andrea Sciand37c6282015-03-20 16:00:25 +01002/*
3 * Xilinx Zynq GPIO device driver
4 *
5 * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
6 *
7 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
8 * Copyright (C) 2009 - 2014 Xilinx, Inc.
Andrea Sciand37c6282015-03-20 16:00:25 +01009 */
10
11#include <common.h>
12#include <asm/gpio.h>
13#include <asm/io.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090014#include <linux/errno.h>
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +053015#include <dm.h>
16#include <fdtdec.h>
17
Siva Durga Prasad Paladuguf17abca2016-03-10 16:27:42 +053018/* Maximum banks */
19#define ZYNQ_GPIO_MAX_BANK 4
20
21#define ZYNQ_GPIO_BANK0_NGPIO 32
22#define ZYNQ_GPIO_BANK1_NGPIO 22
23#define ZYNQ_GPIO_BANK2_NGPIO 32
24#define ZYNQ_GPIO_BANK3_NGPIO 32
25
26#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
27 ZYNQ_GPIO_BANK1_NGPIO + \
28 ZYNQ_GPIO_BANK2_NGPIO + \
29 ZYNQ_GPIO_BANK3_NGPIO)
30
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +053031#define ZYNQMP_GPIO_MAX_BANK 6
32
33#define ZYNQMP_GPIO_BANK0_NGPIO 26
34#define ZYNQMP_GPIO_BANK1_NGPIO 26
35#define ZYNQMP_GPIO_BANK2_NGPIO 26
36#define ZYNQMP_GPIO_BANK3_NGPIO 32
37#define ZYNQMP_GPIO_BANK4_NGPIO 32
38#define ZYNQMP_GPIO_BANK5_NGPIO 32
39
40#define ZYNQMP_GPIO_NR_GPIOS 174
41
42#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
43#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
44 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
45#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
46#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
47 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
48#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
49#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
50 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
51#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
52#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
53 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
54#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
55#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
56 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
57#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
58#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
59 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
Siva Durga Prasad Paladuguf17abca2016-03-10 16:27:42 +053060
61/* Register offsets for the GPIO device */
62/* LSW Mask & Data -WO */
63#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
64/* MSW Mask & Data -WO */
65#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
66/* Data Register-RW */
67#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
68/* Direction mode reg-RW */
69#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
70/* Output enable reg-RW */
71#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
72/* Interrupt mask reg-RO */
73#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
74/* Interrupt enable reg-WO */
75#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
76/* Interrupt disable reg-WO */
77#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
78/* Interrupt status reg-RO */
79#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
80/* Interrupt type reg-RW */
81#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
82/* Interrupt polarity reg-RW */
83#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
84/* Interrupt on any, reg-RW */
85#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
86
87/* Disable all interrupts mask */
88#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
89
90/* Mid pin number of a bank */
91#define ZYNQ_GPIO_MID_PIN_NUM 16
92
93/* GPIO upper 16 bit mask */
94#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
95
Vipul Kumar0f072572018-07-20 14:36:49 +053096struct zynq_gpio_platdata {
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +053097 phys_addr_t base;
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +053098 const struct zynq_platform_data *p_data;
99};
100
101/**
102 * struct zynq_platform_data - zynq gpio platform data structure
103 * @label: string to store in gpio->label
104 * @ngpio: max number of gpio pins
105 * @max_bank: maximum number of gpio banks
106 * @bank_min: this array represents bank's min pin
107 * @bank_max: this array represents bank's max pin
108 */
109struct zynq_platform_data {
110 const char *label;
111 u16 ngpio;
Michal Simek01fcf012018-06-13 13:22:08 +0200112 u32 max_bank;
113 u32 bank_min[ZYNQMP_GPIO_MAX_BANK];
114 u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530115};
116
117static const struct zynq_platform_data zynqmp_gpio_def = {
118 .label = "zynqmp_gpio",
119 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
120 .max_bank = ZYNQMP_GPIO_MAX_BANK,
121 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
122 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
123 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
124 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
125 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
126 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
127 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
128 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
129 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
130 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
131 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
132 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
133};
134
135static const struct zynq_platform_data zynq_gpio_def = {
136 .label = "zynq_gpio",
137 .ngpio = ZYNQ_GPIO_NR_GPIOS,
138 .max_bank = ZYNQ_GPIO_MAX_BANK,
139 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
140 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
141 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
142 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
143 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
144 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
145 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
146 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530147};
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530148
Andrea Sciand37c6282015-03-20 16:00:25 +0100149/**
150 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
151 * for a given pin in the GPIO device
152 * @pin_num: gpio pin number within the device
153 * @bank_num: an output parameter used to return the bank number of the gpio
154 * pin
155 * @bank_pin_num: an output parameter used to return pin number within a bank
156 * for the given gpio pin
157 *
158 * Returns the bank number and pin offset within the bank.
159 */
160static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
161 unsigned int *bank_num,
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530162 unsigned int *bank_pin_num,
163 struct udevice *dev)
Andrea Sciand37c6282015-03-20 16:00:25 +0100164{
Vipul Kumar0f072572018-07-20 14:36:49 +0530165 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Michal Simek01fcf012018-06-13 13:22:08 +0200166 u32 bank;
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530167
Vipul Kumar0f072572018-07-20 14:36:49 +0530168 for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
169 if (pin_num >= platdata->p_data->bank_min[bank] &&
170 pin_num <= platdata->p_data->bank_max[bank]) {
171 *bank_num = bank;
172 *bank_pin_num = pin_num -
173 platdata->p_data->bank_min[bank];
174 return;
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530175 }
176 }
177
Vipul Kumar0f072572018-07-20 14:36:49 +0530178 if (bank >= platdata->p_data->max_bank) {
Michal Simek946205a2018-07-12 12:30:34 +0200179 printf("Invalid bank and pin num\n");
Andrea Sciand37c6282015-03-20 16:00:25 +0100180 *bank_num = 0;
181 *bank_pin_num = 0;
Andrea Sciand37c6282015-03-20 16:00:25 +0100182 }
183}
184
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530185static int gpio_is_valid(unsigned gpio, struct udevice *dev)
Andrea Sciand37c6282015-03-20 16:00:25 +0100186{
Vipul Kumar0f072572018-07-20 14:36:49 +0530187 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530188
Vipul Kumar0f072572018-07-20 14:36:49 +0530189 return gpio < platdata->p_data->ngpio;
Andrea Sciand37c6282015-03-20 16:00:25 +0100190}
191
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530192static int check_gpio(unsigned gpio, struct udevice *dev)
Andrea Sciand37c6282015-03-20 16:00:25 +0100193{
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530194 if (!gpio_is_valid(gpio, dev)) {
Andrea Sciand37c6282015-03-20 16:00:25 +0100195 printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
196 return -1;
197 }
198 return 0;
199}
200
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530201static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
202{
203 u32 data;
204 unsigned int bank_num, bank_pin_num;
Vipul Kumar0f072572018-07-20 14:36:49 +0530205 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530206
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530207 if (check_gpio(gpio, dev) < 0)
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530208 return -1;
209
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530210 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530211
Vipul Kumar0f072572018-07-20 14:36:49 +0530212 data = readl(platdata->base +
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530213 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
214
215 return (data >> bank_pin_num) & 1;
216}
217
218static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
219{
220 unsigned int reg_offset, bank_num, bank_pin_num;
Vipul Kumar0f072572018-07-20 14:36:49 +0530221 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530222
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530223 if (check_gpio(gpio, dev) < 0)
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530224 return -1;
225
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530226 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530227
228 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
229 /* only 16 data bits in bit maskable reg */
230 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
231 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
232 } else {
233 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
234 }
235
236 /*
237 * get the 32 bit value to be written to the mask/data register where
238 * the upper 16 bits is the mask and lower 16 bits is the data
239 */
240 value = !!value;
241 value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
242 ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
243
Vipul Kumar0f072572018-07-20 14:36:49 +0530244 writel(value, platdata->base + reg_offset);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530245
246 return 0;
247}
248
249static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
250{
251 u32 reg;
252 unsigned int bank_num, bank_pin_num;
Vipul Kumar0f072572018-07-20 14:36:49 +0530253 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530254
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530255 if (check_gpio(gpio, dev) < 0)
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530256 return -1;
257
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530258 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530259
260 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
261 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
262 return -1;
263
264 /* clear the bit in direction mode reg to set the pin as input */
Vipul Kumar0f072572018-07-20 14:36:49 +0530265 reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530266 reg &= ~BIT(bank_pin_num);
Vipul Kumar0f072572018-07-20 14:36:49 +0530267 writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530268
269 return 0;
270}
271
272static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
273 int value)
274{
275 u32 reg;
276 unsigned int bank_num, bank_pin_num;
Vipul Kumar0f072572018-07-20 14:36:49 +0530277 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530278
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530279 if (check_gpio(gpio, dev) < 0)
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530280 return -1;
281
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530282 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530283
284 /* set the GPIO pin as output */
Vipul Kumar0f072572018-07-20 14:36:49 +0530285 reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530286 reg |= BIT(bank_pin_num);
Vipul Kumar0f072572018-07-20 14:36:49 +0530287 writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530288
289 /* configure the output enable reg for the pin */
Vipul Kumar0f072572018-07-20 14:36:49 +0530290 reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530291 reg |= BIT(bank_pin_num);
Vipul Kumar0f072572018-07-20 14:36:49 +0530292 writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530293
294 /* set the state of the pin */
Ashok Reddy Soma0384ac02019-09-11 04:40:11 -0600295 zynq_gpio_set_value(dev, gpio, value);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530296 return 0;
297}
298
Michal Simeka6b95872016-03-04 15:56:50 +0100299static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
300{
301 u32 reg;
302 unsigned int bank_num, bank_pin_num;
Vipul Kumar0f072572018-07-20 14:36:49 +0530303 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Michal Simeka6b95872016-03-04 15:56:50 +0100304
305 if (check_gpio(offset, dev) < 0)
306 return -1;
307
308 zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
309
310 /* set the GPIO pin as output */
Vipul Kumar0f072572018-07-20 14:36:49 +0530311 reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Michal Simeka6b95872016-03-04 15:56:50 +0100312 reg &= BIT(bank_pin_num);
313 if (reg)
314 return GPIOF_OUTPUT;
315 else
316 return GPIOF_INPUT;
317}
318
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530319static const struct dm_gpio_ops gpio_zynq_ops = {
320 .direction_input = zynq_gpio_direction_input,
321 .direction_output = zynq_gpio_direction_output,
322 .get_value = zynq_gpio_get_value,
323 .set_value = zynq_gpio_set_value,
Michal Simeka6b95872016-03-04 15:56:50 +0100324 .get_function = zynq_gpio_get_function,
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530325};
326
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530327static const struct udevice_id zynq_gpio_ids[] = {
328 { .compatible = "xlnx,zynq-gpio-1.0",
329 .data = (ulong)&zynq_gpio_def},
330 { .compatible = "xlnx,zynqmp-gpio-1.0",
331 .data = (ulong)&zynqmp_gpio_def},
332 { }
333};
334
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530335static int zynq_gpio_probe(struct udevice *dev)
336{
Vipul Kumar0f072572018-07-20 14:36:49 +0530337 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530338 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Michal Simek312dd1c2018-08-02 12:58:54 +0200339 const void *label_ptr;
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530340
Michal Simek312dd1c2018-08-02 12:58:54 +0200341 label_ptr = dev_read_prop(dev, "label", NULL);
342 if (label_ptr) {
343 uc_priv->bank_name = strdup(label_ptr);
344 if (!uc_priv->bank_name)
345 return -ENOMEM;
346 } else {
347 uc_priv->bank_name = dev->name;
348 }
Michal Simek0d6fabb2018-06-21 13:58:56 +0200349
Vipul Kumar0f072572018-07-20 14:36:49 +0530350 if (platdata->p_data)
351 uc_priv->gpio_count = platdata->p_data->ngpio;
Siva Durga Prasad Paladugu404a00c2016-03-10 16:27:43 +0530352
353 return 0;
354}
355
356static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
357{
Vipul Kumar0f072572018-07-20 14:36:49 +0530358 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530359
Vipul Kumar0f072572018-07-20 14:36:49 +0530360 platdata->base = (phys_addr_t)dev_read_addr(dev);
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530361
Vipul Kumar0f072572018-07-20 14:36:49 +0530362 platdata->p_data =
363 (struct zynq_platform_data *)dev_get_driver_data(dev);
Michal Simek0df9bea2018-07-12 10:58:04 +0200364
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530365 return 0;
366}
367
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530368U_BOOT_DRIVER(gpio_zynq) = {
369 .name = "gpio_zynq",
370 .id = UCLASS_GPIO,
371 .ops = &gpio_zynq_ops,
372 .of_match = zynq_gpio_ids,
373 .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
374 .probe = zynq_gpio_probe,
Vipul Kumar0f072572018-07-20 14:36:49 +0530375 .platdata_auto_alloc_size = sizeof(struct zynq_gpio_platdata),
Siva Durga Prasad Paladugu68c70262016-03-10 16:27:38 +0530376};