| /* |
| * Copyright (C) 2011 Freescale Semiconductor, Inc. |
| * |
| * Configuration settings for the MX53SMD Freescale board. |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #ifndef __CONFIG_H |
| #define __CONFIG_H |
| |
| #define CONFIG_MX53 |
| |
| #define CONFIG_DISPLAY_CPUINFO |
| #define CONFIG_DISPLAY_BOARDINFO |
| |
| #define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD |
| |
| #include <asm/arch/imx-regs.h> |
| |
| #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| #define CONFIG_SETUP_MEMORY_TAGS |
| #define CONFIG_INITRD_TAG |
| #define CONFIG_REVISION_TAG |
| |
| #define CONFIG_SYS_GENERIC_BOARD |
| |
| /* Size of malloc() pool */ |
| #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) |
| |
| #define CONFIG_BOARD_EARLY_INIT_F |
| #define CONFIG_MXC_GPIO |
| |
| #define CONFIG_MXC_UART |
| #define CONFIG_MXC_UART_BASE UART1_BASE |
| |
| /* I2C Configs */ |
| #define CONFIG_CMD_I2C |
| #define CONFIG_SYS_I2C |
| #define CONFIG_SYS_I2C_MXC |
| |
| /* MMC Configs */ |
| #define CONFIG_FSL_ESDHC |
| #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
| #define CONFIG_SYS_FSL_ESDHC_NUM 1 |
| |
| #define CONFIG_MMC |
| #define CONFIG_CMD_MMC |
| #define CONFIG_GENERIC_MMC |
| #define CONFIG_CMD_FAT |
| #define CONFIG_DOS_PARTITION |
| |
| /* Eth Configs */ |
| #define CONFIG_HAS_ETH1 |
| #define CONFIG_MII |
| |
| #define CONFIG_FEC_MXC |
| #define IMX_FEC_BASE FEC_BASE_ADDR |
| #define CONFIG_FEC_MXC_PHYADDR 0x1F |
| |
| #define CONFIG_CMD_PING |
| #define CONFIG_CMD_DHCP |
| #define CONFIG_CMD_MII |
| #define CONFIG_CMD_NET |
| |
| /* allow to overwrite serial and ethaddr */ |
| #define CONFIG_ENV_OVERWRITE |
| #define CONFIG_CONS_INDEX 1 |
| #define CONFIG_BAUDRATE 115200 |
| |
| /* Command definition */ |
| #include <config_cmd_default.h> |
| |
| #undef CONFIG_CMD_IMLS |
| |
| #define CONFIG_BOOTDELAY 3 |
| |
| #define CONFIG_ETHPRIME "FEC0" |
| |
| #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ |
| #define CONFIG_SYS_TEXT_BASE 0x77800000 |
| |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| "script=boot.scr\0" \ |
| "uimage=uImage\0" \ |
| "mmcdev=0\0" \ |
| "mmcpart=2\0" \ |
| "mmcroot=/dev/mmcblk0p3 rw\0" \ |
| "mmcrootfstype=ext3 rootwait\0" \ |
| "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ |
| "root=${mmcroot} " \ |
| "rootfstype=${mmcrootfstype}\0" \ |
| "loadbootscript=" \ |
| "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
| "bootscript=echo Running bootscript from mmc ...; " \ |
| "source\0" \ |
| "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ |
| "mmcboot=echo Booting from mmc ...; " \ |
| "run mmcargs; " \ |
| "bootm\0" \ |
| "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ |
| "root=/dev/nfs " \ |
| "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ |
| "netboot=echo Booting from net ...; " \ |
| "run netargs; " \ |
| "dhcp ${uimage}; bootm\0" \ |
| |
| #define CONFIG_BOOTCOMMAND \ |
| "mmc dev ${mmcdev}; if mmc rescan; then " \ |
| "if run loadbootscript; then " \ |
| "run bootscript; " \ |
| "else " \ |
| "if run loaduimage; then " \ |
| "run mmcboot; " \ |
| "else run netboot; " \ |
| "fi; " \ |
| "fi; " \ |
| "else run netboot; fi" |
| #define CONFIG_ARP_TIMEOUT 200UL |
| |
| /* Miscellaneous configurable options */ |
| #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
| #define CONFIG_AUTO_COMPLETE |
| #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| |
| /* Print Buffer Size */ |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| |
| #define CONFIG_SYS_MEMTEST_START 0x70000000 |
| #define CONFIG_SYS_MEMTEST_END 0x70010000 |
| |
| #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| |
| #define CONFIG_CMDLINE_EDITING |
| |
| /* Physical Memory Map */ |
| #define CONFIG_NR_DRAM_BANKS 2 |
| #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
| #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) |
| #define PHYS_SDRAM_2 CSD1_BASE_ADDR |
| #define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) |
| #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) |
| |
| #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) |
| #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) |
| #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) |
| |
| #define CONFIG_SYS_INIT_SP_OFFSET \ |
| (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| #define CONFIG_SYS_INIT_SP_ADDR \ |
| (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| |
| /* FLASH and environment organization */ |
| #define CONFIG_SYS_NO_FLASH |
| |
| #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
| #define CONFIG_ENV_SIZE (8 * 1024) |
| #define CONFIG_ENV_IS_IN_MMC |
| #define CONFIG_SYS_MMC_ENV_DEV 0 |
| |
| #define CONFIG_OF_LIBFDT |
| |
| #endif /* __CONFIG_H */ |