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gerrit.cesnet.cz / github / trini / u-boot / 446707c90f52e5fcafecd468920cfad685ee9fc7 / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 3e731aa fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave by Dave Liu · 15 years ago
  2. 1aa3d08 fsl-ddr: add override for the Rtt_Wr by Dave Liu · 15 years ago
  3. bdc9f7b fsl-ddr: add the override for write leveling by Dave Liu · 15 years ago
  4. 0a71c92 fsl-ddr: Fix power-down timing settings by Dave Liu · 15 years ago
  5. 6d8565a ppc/8xxx: Misc DDR related fixes by Kumar Gala · 15 years ago
  6. 2abbd31 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  7. e7563af fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  8. c360cea fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  9. 6a81978 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  10. 22cca7e fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  11. 22ff3d0 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  12. 80ee3ce fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  13. 1f293b4 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  14. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  15. 302e52e Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  16. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago