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gerrit.cesnet.cz / github / trini / u-boot / 446707c90f52e5fcafecd468920cfad685ee9fc7 / cpu / mpc8xxx / ddr
  1. 3e731aa fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave by Dave Liu · 15 years ago
  2. 1aa3d08 fsl-ddr: add override for the Rtt_Wr by Dave Liu · 15 years ago
  3. bdc9f7b fsl-ddr: add the override for write leveling by Dave Liu · 15 years ago
  4. 0a71c92 fsl-ddr: Fix power-down timing settings by Dave Liu · 15 years ago
  5. 3ad95de fsl-ddr: Fix the chip-select interleaving issue by Dave Liu · 15 years ago
  6. d11823c mpc8xxx: improve LAW error messages when setting up DDR by Paul Gortmaker · 15 years ago
  7. 6d8565a ppc/8xxx: Misc DDR related fixes by Kumar Gala · 15 years ago
  8. 2abbd31 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  9. d9c147f 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · 15 years ago
  10. e66f38d fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more by Timur Tabi · 15 years ago
  11. e7563af fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  12. c360cea fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  13. 6a81978 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  14. edf0e25 fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · 16 years ago
  15. 1542fbd fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · 16 years ago
  16. b4983e1 fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  17. 22cca7e fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  18. 22ff3d0 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  19. 80ee3ce fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  20. 7008d26 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  21. 1f293b4 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  22. c9ffd83 Check DDR interleaving mode by Haiying Wang · 16 years ago
  23. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  24. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  25. 6d0f6bc rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · 16 years ago
  26. f12e454 Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  27. 302e52e Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  28. 233fdd5 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · 16 years ago
  29. 05c05a2 FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · 16 years ago
  30. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago