Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012-2013, Xilinx, Michal Simek |
| 4 | * |
| 5 | * (C) Copyright 2012 |
| 6 | * Joe Hershberger <joe.hershberger@ni.com> |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef _ZYNQPL_H_ |
| 10 | #define _ZYNQPL_H_ |
| 11 | |
| 12 | #include <xilinx.h> |
| 13 | |
Siva Durga Prasad Paladugu | 37e3a36 | 2018-06-26 15:02:19 +0530 | [diff] [blame] | 14 | #ifdef CONFIG_CMD_ZYNQ_AES |
Siva Durga Prasad Paladugu | 3427f4d | 2015-12-09 18:46:43 +0530 | [diff] [blame] | 15 | int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen, |
| 16 | u8 bstype); |
Siva Durga Prasad Paladugu | 37e3a36 | 2018-06-26 15:02:19 +0530 | [diff] [blame] | 17 | #endif |
| 18 | |
Michal Simek | 14cfc4f | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 19 | extern struct xilinx_fpga_op zynq_op; |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 20 | |
Michal Simek | 4aba5fb | 2018-01-17 10:56:22 -0300 | [diff] [blame] | 21 | #define XILINX_ZYNQ_XC7Z007S 0x3 |
| 22 | #define XILINX_ZYNQ_XC7Z010 0x2 |
Michal Simek | 5389564 | 2024-07-30 15:50:17 +0200 | [diff] [blame] | 23 | #define XILINX_ZYNQ_XC7Z010_LR 0x4 |
Michal Simek | 4aba5fb | 2018-01-17 10:56:22 -0300 | [diff] [blame] | 24 | #define XILINX_ZYNQ_XC7Z012S 0x1c |
| 25 | #define XILINX_ZYNQ_XC7Z014S 0x8 |
| 26 | #define XILINX_ZYNQ_XC7Z015 0x1b |
Michal Simek | 5389564 | 2024-07-30 15:50:17 +0200 | [diff] [blame] | 27 | #define XILINX_ZYNQ_XC7Z020_LR 0x9 |
Michal Simek | 4aba5fb | 2018-01-17 10:56:22 -0300 | [diff] [blame] | 28 | #define XILINX_ZYNQ_XC7Z020 0x7 |
| 29 | #define XILINX_ZYNQ_XC7Z030 0xc |
| 30 | #define XILINX_ZYNQ_XC7Z035 0x12 |
| 31 | #define XILINX_ZYNQ_XC7Z045 0x11 |
| 32 | #define XILINX_ZYNQ_XC7Z100 0x16 |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 33 | |
| 34 | /* Device Image Sizes */ |
Michal Simek | 05c59d0 | 2016-10-18 16:10:25 +0200 | [diff] [blame] | 35 | #define XILINX_XC7Z007S_SIZE 16669920/8 |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 36 | #define XILINX_XC7Z010_SIZE 16669920/8 |
Michal Simek | 5389564 | 2024-07-30 15:50:17 +0200 | [diff] [blame] | 37 | #define XILINX_XC7Z010_LR_SIZE 16669920/8 |
Michal Simek | 05c59d0 | 2016-10-18 16:10:25 +0200 | [diff] [blame] | 38 | #define XILINX_XC7Z012S_SIZE 28085344/8 |
| 39 | #define XILINX_XC7Z014S_SIZE 32364512/8 |
Michal Simek | 31993d6 | 2013-09-26 16:39:03 +0200 | [diff] [blame] | 40 | #define XILINX_XC7Z015_SIZE 28085344/8 |
Michal Simek | 5389564 | 2024-07-30 15:50:17 +0200 | [diff] [blame] | 41 | #define XILINX_XC7Z020_LR_SIZE 32364512/8 |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 42 | #define XILINX_XC7Z020_SIZE 32364512/8 |
| 43 | #define XILINX_XC7Z030_SIZE 47839328/8 |
Siva Durga Prasad Paladugu | b910380 | 2014-11-25 15:29:54 +0530 | [diff] [blame] | 44 | #define XILINX_XC7Z035_SIZE 106571232/8 |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 45 | #define XILINX_XC7Z045_SIZE 106571232/8 |
Michal Simek | fd2b10b | 2013-06-17 13:54:07 +0200 | [diff] [blame] | 46 | #define XILINX_XC7Z100_SIZE 139330784/8 |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 47 | |
Michal Simek | 4aba5fb | 2018-01-17 10:56:22 -0300 | [diff] [blame] | 48 | /* Device Names */ |
| 49 | #define XILINX_XC7Z007S_NAME "7z007s" |
| 50 | #define XILINX_XC7Z010_NAME "7z010" |
Michal Simek | 5389564 | 2024-07-30 15:50:17 +0200 | [diff] [blame] | 51 | #define XILINX_XC7Z010_LR_NAME "xc7z010_lr" |
Michal Simek | 4aba5fb | 2018-01-17 10:56:22 -0300 | [diff] [blame] | 52 | #define XILINX_XC7Z012S_NAME "7z012s" |
| 53 | #define XILINX_XC7Z014S_NAME "7z014s" |
| 54 | #define XILINX_XC7Z015_NAME "7z015" |
Michal Simek | 5389564 | 2024-07-30 15:50:17 +0200 | [diff] [blame] | 55 | #define XILINX_XC7Z020_LR_NAME "xa7z020_lr" |
Michal Simek | 4aba5fb | 2018-01-17 10:56:22 -0300 | [diff] [blame] | 56 | #define XILINX_XC7Z020_NAME "7z020" |
| 57 | #define XILINX_XC7Z030_NAME "7z030" |
| 58 | #define XILINX_XC7Z035_NAME "7z035" |
| 59 | #define XILINX_XC7Z045_NAME "7z045" |
| 60 | #define XILINX_XC7Z100_NAME "7z100" |
Michal Simek | 05c59d0 | 2016-10-18 16:10:25 +0200 | [diff] [blame] | 61 | |
Michal Simek | 4aba5fb | 2018-01-17 10:56:22 -0300 | [diff] [blame] | 62 | #if defined(CONFIG_FPGA) |
| 63 | #define ZYNQ_DESC(name) { \ |
| 64 | .idcode = XILINX_ZYNQ_XC##name, \ |
| 65 | .fpga_size = XILINX_XC##name##_SIZE, \ |
| 66 | .devicename = XILINX_XC##name##_NAME \ |
| 67 | } |
| 68 | #else |
| 69 | #define ZYNQ_DESC(name) { \ |
| 70 | .idcode = XILINX_ZYNQ_XC##name, \ |
| 71 | .devicename = XILINX_XC##name##_NAME \ |
| 72 | } |
| 73 | #endif |
Michal Simek | fd2b10b | 2013-06-17 13:54:07 +0200 | [diff] [blame] | 74 | |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 75 | #endif /* _ZYNQPL_H_ */ |