blob: f0867227acc33d007816ef04eb18796e51241a33 [file] [log] [blame]
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +09001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 */
5#ifndef __CONFIG_H
6#define __CONFIG_H
7
8/* Timers for fasp(TIMCLK) */
Tom Rini65cc0e22022-11-16 13:10:41 -05009#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090010
11/*
12 * SDRAM (for initialize)
13 */
Tom Riniaa6e94d2022-11-16 13:10:37 -050014#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090015#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
16
Tom Rini1d457db2022-12-04 10:04:50 -050017#define CFG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090018
19#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
20
21/*
22 * Boot info
23 */
Masahisa Kojimafd50ae32024-02-08 11:33:44 +090024#define SCB_PLAT_METADATA_OFFSET (0x510000)
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090025
26/*
27 * Hardware drivers support
28 */
29
30/* RTC */
Tom Rini65cc0e22022-11-16 13:10:41 -050031#define CFG_SYS_I2C_RTC_ADDR 0x51
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090032
33/* Serial (pl011) */
34#define UART_CLK (62500000)
Tom Rinif410d0a2022-12-04 10:13:30 -050035#define CFG_PL011_CLOCK UART_CLK
Tom Rinib8615742022-12-04 10:13:31 -050036#define CFG_PL01x_PORTS {(void *)(0x2a400000)}
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090037
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090038/* Support MTD */
Tom Rini65cc0e22022-11-16 13:10:41 -050039#define CFG_SYS_FLASH_BASE (0x08000000)
40#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE}
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090041
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090042/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090043
Jassi Brar6b403ca2023-05-31 00:29:56 -050044#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
Jassi Brar6b403ca2023-05-31 00:29:56 -050045#define DEVELOPERBOX_FIP_IMAGE_GUID \
46 EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \
47 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08)
48#else
Sughosh Ganu741ef862022-04-15 11:29:34 +053049#define DEVELOPERBOX_FIP_IMAGE_GUID \
50 EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \
51 0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98)
Jassi Brar6b403ca2023-05-31 00:29:56 -050052#endif
Sughosh Ganu741ef862022-04-15 11:29:34 +053053
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090054/* Distro boot settings */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090055#ifdef CONFIG_CMD_USB
56#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
57#else
58#define BOOT_TARGET_DEVICE_USB(func)
59#endif
60
61#ifdef CONFIG_CMD_MMC
62#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
63#else
64#define BOOT_TARGET_DEVICE_MMC(func)
65#endif
66
67#ifdef CONFIG_CMD_NVME
68#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
69#else
70#define BOOT_TARGET_DEVICE_NVME(func)
71#endif
72
73#ifdef CONFIG_CMD_SCSI
74#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
75#else
76#define BOOT_TARGET_DEVICE_SCSI(func)
77#endif
78
79#define BOOT_TARGET_DEVICES(func) \
80 BOOT_TARGET_DEVICE_USB(func) \
81 BOOT_TARGET_DEVICE_MMC(func) \
82 BOOT_TARGET_DEVICE_SCSI(func) \
83 BOOT_TARGET_DEVICE_NVME(func) \
84
85#include <config_distro_bootcmd.h>
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090086
Tom Rini0613c362022-12-04 10:03:50 -050087#define CFG_EXTRA_ENV_SETTINGS \
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090088 "fdt_addr_r=0x9fe00000\0" \
89 "kernel_addr_r=0x90000000\0" \
90 "ramdisk_addr_r=0xa0000000\0" \
91 "scriptaddr=0x88000000\0" \
92 "pxefile_addr_r=0x88100000\0" \
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090093 BOOTENV
94
95#endif /* __CONFIG_H */