blob: 6294bffc58232603b274ffe0b0c9f87698d75c29 [file] [log] [blame]
Troy Kisky8682aba2012-02-07 14:08:48 +00001#ifndef _MICREL_H
2
3#define MII_KSZ9021_EXT_COMMON_CTRL 0x100
4#define MII_KSZ9021_EXT_STRAP_STATUS 0x101
5#define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE 0x102
6#define MII_KSZ9021_EXT_OP_STRAP_STATUS 0x103
7#define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW 0x104
8#define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW 0x105
9#define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
10#define MII_KSZ9021_EXT_ANALOG_TEST 0x107
SARTRE Leo42a7cb52013-04-30 16:57:25 +020011/* Register operations */
12#define MII_KSZ9031_MOD_REG 0x0000
13/* Data operations */
14#define MII_KSZ9031_MOD_DATA_NO_POST_INC 0x4000
15#define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000
16#define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000
Troy Kisky8682aba2012-02-07 14:08:48 +000017
Stefano Babic71817a12013-09-02 15:42:28 +020018#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4
19#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5
20#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
21#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
22
Ash Charlesf0185452016-10-21 17:31:33 -040023#define MII_KSZ9031_FLP_BURST_TX_LO 0x3
24#define MII_KSZ9031_FLP_BURST_TX_HI 0x4
25
Philippe Schenker0861aa82020-03-11 11:59:22 +010026#define MII_KSZ9x31_SILICON_REV_MASK 0xfffff0
27
Philippe Schenkerf72e48b2020-03-11 11:59:26 +010028#define MII_KSZ9131_RXTXDLL_BYPASS BIT(12)
29#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL 0x4c
30#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL 0x4d
31
Philippe Schenker0861aa82020-03-11 11:59:22 +010032#define PHY_ID_KSZ9031 0x00221620
Philippe Schenkerc51eef52020-03-11 11:59:23 +010033#define PHY_ID_KSZ9131 0x00221640
Philippe Schenker0861aa82020-03-11 11:59:22 +010034
Otavio Salvadorf0222902015-07-28 20:24:41 -030035/* Registers */
36#define MMD_ACCESS_CONTROL 0xd
37#define MMD_ACCESS_REG_DATA 0xe
38
Troy Kisky8682aba2012-02-07 14:08:48 +000039struct phy_device;
40int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
41int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
42
SARTRE Leo42a7cb52013-04-30 16:57:25 +020043int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
44 int regnum, u16 mode, u16 val);
45int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
46 int regnum, u16 mode);
Philippe Schenkerc51eef52020-03-11 11:59:23 +010047int ksz9xx1_phy_get_id(struct phy_device *phydev);
SARTRE Leo42a7cb52013-04-30 16:57:25 +020048
Troy Kisky8682aba2012-02-07 14:08:48 +000049#endif