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Stefan Roese8b7d1f02007-01-31 16:37:34 +01001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese8b7d1f02007-01-31 16:37:34 +01006 */
7
8
9/*************************************************************************
10 * (c) 2005 esd gmbh Hannover
11 *
12 *
13 * from IceCube.h file
14 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
15 *
16 *************************************************************************/
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/*
22 * High Level Configuration Options
23 * (easy to change)
24 */
25
26#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
27#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
28#define CONFIG_ICECUBE 1 /* ... on IceCube board */
29#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
30#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
31
Wolfgang Denk2ae18242010-10-06 09:05:45 +020032#ifndef CONFIG_SYS_TEXT_BASE
33#define CONFIG_SYS_TEXT_BASE 0xFFF00000
34#endif
35
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Stefan Roese8b7d1f02007-01-31 16:37:34 +010037
Becky Bruce31d82672008-05-08 19:02:12 -050038#define CONFIG_HIGH_BATS 1 /* High BATs supported */
39
Stefan Roese8b7d1f02007-01-31 16:37:34 +010040/*
41 * Serial console configuration
42 */
43#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
44#if 0 /* test-only */
45#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
46#else
47#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
48#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Stefan Roese8b7d1f02007-01-31 16:37:34 +010050
Stefan Roese8b7d1f02007-01-31 16:37:34 +010051#define CONFIG_MII
52#if 0 /* test-only !!! */
Stefan Roese8b7d1f02007-01-31 16:37:34 +010053#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Stefan Roese8b7d1f02007-01-31 16:37:34 +010055#define CONFIG_NS8382X 1
56#endif
57
Stefan Roese8b7d1f02007-01-31 16:37:34 +010058/* Partitions */
59#define CONFIG_MAC_PARTITION
60#define CONFIG_DOS_PARTITION
61
62/* USB */
63#if 0
64#define CONFIG_USB_OHCI
Stefan Roese8b7d1f02007-01-31 16:37:34 +010065#define CONFIG_USB_STORAGE
Stefan Roese8b7d1f02007-01-31 16:37:34 +010066#endif
67
Stefan Roese8b7d1f02007-01-31 16:37:34 +010068
Jon Loeligerd794cfe2007-07-04 22:31:15 -050069/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050070 * BOOTP options
71 */
72#define CONFIG_BOOTP_BOOTFILESIZE
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76
77
78/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -050079 * Command line configuration.
80 */
81#include <config_cmd_default.h>
82
83#define CONFIG_CMD_EEPROM
84#define CONFIG_CMD_FAT
85#define CONFIG_CMD_EXT2
86#define CONFIG_CMD_I2C
87#define CONFIG_CMD_IDE
88#define CONFIG_CMD_BSP
89#define CONFIG_CMD_ELF
90
Stefan Roese8b7d1f02007-01-31 16:37:34 +010091
Wolfgang Denk14d0a022010-10-07 21:51:12 +020092#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093# define CONFIG_SYS_LOWBOOT 1
94# define CONFIG_SYS_LOWBOOT16 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +010095#endif
Wolfgang Denk14d0a022010-10-07 21:51:12 +020096#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097# define CONFIG_SYS_LOWBOOT 1
98# define CONFIG_SYS_LOWBOOT08 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +010099#endif
100
101/*
102 * Autobooting
103 */
104#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
105
106#define CONFIG_PREBOOT "echo;" \
107 "echo Welcome to CBX-CPU5200 (mecp5200);" \
108 "echo"
109
110#undef CONFIG_BOOTARGS
111
112#define CONFIG_EXTRA_ENV_SETTINGS \
113 "netdev=eth0\0" \
Wolfgang Denk74357112007-02-27 14:26:04 +0100114 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
115 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
116 "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
117 "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
118 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
119 "loadaddr=01000000\0" \
120 "serverip=192.168.2.99\0" \
121 "gatewayip=10.0.0.79\0" \
122 "user=mu\0" \
123 "target=mecp5200.esd\0" \
124 "script=mecp5200.bat\0" \
125 "image=/tftpboot/vxWorks_mecp5200\0" \
126 "ipaddr=10.0.13.196\0" \
127 "netmask=255.255.0.0\0" \
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100128 ""
129
130#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
131
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100132/*
133 * IPB Bus clocking configuration.
134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100136/*
137 * I2C configuration
138 */
139#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
143#define CONFIG_SYS_I2C_SLAVE 0x7F
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100144
145/*
146 * EEPROM configuration
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
149#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
150#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
151#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
152#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100153/*
154 * Flash configuration
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_BASE 0xFFC00000
157#define CONFIG_SYS_FLASH_SIZE 0x00400000
158#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
159#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
160#define CONFIG_SYS_MAX_FLASH_SECT 512
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
163#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100164
165/*
166 * Environment settings
167 */
168#if 1 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200169#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200170#define CONFIG_ENV_SIZE 0x10000
171#define CONFIG_ENV_SECT_SIZE 0x10000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100172#define CONFIG_ENV_OVERWRITE 1
173#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200174#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200175#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
176#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100177 /* total size of a CAT24WC32 is 8192 bytes */
178#define CONFIG_ENV_OVERWRITE 1
179#endif
180
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200181#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
183#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100184#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100186#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */
188#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
189#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100190
191
192/*
193 * Memory map
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_MBAR 0xF0000000
196#define CONFIG_SYS_SDRAM_BASE 0x00000000
197#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100198
199/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200201#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100202
203
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200204#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100206
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200207#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
209# define CONFIG_SYS_RAMBOOT 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100210#endif
211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
213#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
214#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100215
216/*
217 * Ethernet configuration
218 */
219#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800220#define CONFIG_MPC5xxx_FEC_MII100
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100221/*
Ben Warren86321fc2009-02-05 23:58:25 -0800222 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100223 */
Ben Warren86321fc2009-02-05 23:58:25 -0800224/* #define CONFIG_MPC5xxx_FEC_MII10 */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100225#define CONFIG_PHY_ADDR 0x00
226#define CONFIG_UDP_CHECKSUM 1
227
228
229/*
230 * GPIO configuration
231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100233
234/*
235 * Miscellaneous configurable options
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500238#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100240#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100242#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
244#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
245#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
248#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500255#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500257#endif
258
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100259/*
260 * Various low-level settings
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
263#define CONFIG_SYS_HID0_FINAL HID0_ICE
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
266#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
267#define CONFIG_SYS_BOOTCS_CFG 0x00085d00
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
270#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_CS1_START 0xfd000000
273#define CONFIG_SYS_CS1_SIZE 0x00010000
274#define CONFIG_SYS_CS1_CFG 0x10101410
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_CS_BURST 0x00000000
277#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100280
281/*-----------------------------------------------------------------------
282 * USB stuff
283 *-----------------------------------------------------------------------
284 */
285#define CONFIG_USB_CLOCK 0x0001BBBB
286#define CONFIG_USB_CONFIG 0x00001000
287
288/*-----------------------------------------------------------------------
289 * IDE/ATA stuff Supports IDE harddisk
290 *-----------------------------------------------------------------------
291 */
292
293#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
294
295#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
296#undef CONFIG_IDE_LED /* LED for ide not supported */
297
298#define CONFIG_IDE_RESET /* reset for ide supported */
299#define CONFIG_IDE_PREINIT
300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
302#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100307
308/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100310
311/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100313
314/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100316
Wolfgang Denk74357112007-02-27 14:26:04 +0100317/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_ATA_STRIDE 4
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100319
320#endif /* __CONFIG_H */