blob: 79d656133adb4d50a7a28dfb529f81121db708ac [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Freescale Three Speed Ethernet Controller driver
wdenk42d1f032003-10-15 23:53:47 +00003 *
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
6 * herein by reference.
7 *
Claudiu Manoilaec84bf2013-09-30 12:44:42 +03008 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00009 * (C) Copyright 2003, Motorola, Inc.
wdenk42d1f032003-10-15 23:53:47 +000010 * author Andy Fleming
11 *
12 */
13
14#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000015#include <common.h>
16#include <malloc.h>
17#include <net.h>
18#include <command.h>
Andy Flemingdd3d1f52008-08-31 16:33:25 -050019#include <tsec.h>
Andy Fleming063c1262011-04-08 02:10:54 -050020#include <fsl_mdio.h>
Kim Phillips0d071cd2009-08-24 14:32:26 -050021#include <asm/errno.h>
chenhui zhaoaada81d2011-10-03 08:38:50 -050022#include <asm/processor.h>
Alison Wang52d00a82014-09-05 13:52:38 +080023#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000024
Wolfgang Denkd87080b2006-03-31 18:32:53 +020025DECLARE_GLOBAL_DATA_PTR;
26
Marian Balakowicz63ff0042005-10-28 22:30:33 +020027#define TX_BUF_CNT 2
wdenk42d1f032003-10-15 23:53:47 +000028
Claudiu Manoil18b338f2013-09-30 12:44:44 +030029static uint rx_idx; /* index of the current RX buffer */
30static uint tx_idx; /* index of the current TX buffer */
wdenk42d1f032003-10-15 23:53:47 +000031
wdenk42d1f032003-10-15 23:53:47 +000032#ifdef __GNUC__
Claudiu Manoil9c9141f2013-10-04 19:13:53 +030033static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
34static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
35
wdenk42d1f032003-10-15 23:53:47 +000036#else
37#error "rtx must be 64-bit aligned"
38#endif
39
Joe Hershbergerc8a60b52012-05-21 09:46:36 +000040static int tsec_send(struct eth_device *dev, void *packet, int length);
chenhui zhaoaada81d2011-10-03 08:38:50 -050041
Andy Fleming75b9d4a2008-08-31 16:33:26 -050042/* Default initializations for TSEC controllers. */
43
44static struct tsec_info_struct tsec_info[] = {
45#ifdef CONFIG_TSEC1
46 STD_TSEC_INFO(1), /* TSEC1 */
47#endif
48#ifdef CONFIG_TSEC2
49 STD_TSEC_INFO(2), /* TSEC2 */
50#endif
51#ifdef CONFIG_MPC85XX_FEC
52 {
Claudiu Manoilaec84bf2013-09-30 12:44:42 +030053 .regs = TSEC_GET_REGS(2, 0x2000),
Andy Fleming75b9d4a2008-08-31 16:33:26 -050054 .devname = CONFIG_MPC85XX_FEC_NAME,
55 .phyaddr = FEC_PHY_ADDR,
Andy Fleming063c1262011-04-08 02:10:54 -050056 .flags = FEC_FLAGS,
57 .mii_devname = DEFAULT_MII_NAME
Andy Fleming75b9d4a2008-08-31 16:33:26 -050058 }, /* FEC */
59#endif
60#ifdef CONFIG_TSEC3
61 STD_TSEC_INFO(3), /* TSEC3 */
62#endif
63#ifdef CONFIG_TSEC4
64 STD_TSEC_INFO(4), /* TSEC4 */
65#endif
66};
67
Andy Fleming2abe3612008-08-31 16:33:27 -050068#define TBIANA_SETTINGS ( \
69 TBIANA_ASYMMETRIC_PAUSE \
70 | TBIANA_SYMMETRIC_PAUSE \
71 | TBIANA_FULL_DUPLEX \
72 )
73
Felix Radensky90b5bf22010-06-28 01:57:39 +030074/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
75#ifndef CONFIG_TSEC_TBICR_SETTINGS
Kumar Gala72c96a62010-12-01 22:55:54 -060076#define CONFIG_TSEC_TBICR_SETTINGS ( \
Andy Fleming2abe3612008-08-31 16:33:27 -050077 TBICR_PHY_RESET \
Kumar Gala72c96a62010-12-01 22:55:54 -060078 | TBICR_ANEG_ENABLE \
Andy Fleming2abe3612008-08-31 16:33:27 -050079 | TBICR_FULL_DUPLEX \
80 | TBICR_SPEED1_SET \
81 )
Felix Radensky90b5bf22010-06-28 01:57:39 +030082#endif /* CONFIG_TSEC_TBICR_SETTINGS */
Peter Tyser46e91672009-11-03 17:52:07 -060083
Andy Fleming2abe3612008-08-31 16:33:27 -050084/* Configure the TBI for SGMII operation */
85static void tsec_configure_serdes(struct tsec_private *priv)
86{
Peter Tyserc6dbdfd2009-11-09 13:09:46 -060087 /* Access TBI PHY registers at given TSEC register offset as opposed
88 * to the register offset used for external PHY accesses */
Andy Fleming063c1262011-04-08 02:10:54 -050089 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
90 0, TBI_ANA, TBIANA_SETTINGS);
91 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
92 0, TBI_TBICON, TBICON_CLK_SELECT);
93 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
94 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
Andy Fleming2abe3612008-08-31 16:33:27 -050095}
michael.firth@bt.com55fe7c52008-01-16 11:40:51 +000096
David Updegraff53a5c422007-06-11 10:41:07 -050097#ifdef CONFIG_MCAST_TFTP
98
99/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
100
101/* Set the appropriate hash bit for the given addr */
102
103/* The algorithm works like so:
104 * 1) Take the Destination Address (ie the multicast address), and
105 * do a CRC on it (little endian), and reverse the bits of the
106 * result.
107 * 2) Use the 8 most significant bits as a hash into a 256-entry
108 * table. The table is controlled through 8 32-bit registers:
Claudiu Manoil876d4512013-09-30 12:44:40 +0300109 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
110 * 255. This means that the 3 most significant bits in the
David Updegraff53a5c422007-06-11 10:41:07 -0500111 * hash index which gaddr register to use, and the 5 other bits
112 * indicate which bit (assuming an IBM numbering scheme, which
Claudiu Manoil876d4512013-09-30 12:44:40 +0300113 * for PowerPC (tm) is usually the case) in the register holds
David Updegraff53a5c422007-06-11 10:41:07 -0500114 * the entry. */
115static int
Claudiu Manoil9c4cffa2013-09-30 12:44:39 +0300116tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
David Updegraff53a5c422007-06-11 10:41:07 -0500117{
Claudiu Manoilb2002042013-09-30 12:44:41 +0300118 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoil876d4512013-09-30 12:44:40 +0300119 struct tsec __iomem *regs = priv->regs;
120 u32 result, value;
121 u8 whichbit, whichreg;
David Updegraff53a5c422007-06-11 10:41:07 -0500122
Claudiu Manoil876d4512013-09-30 12:44:40 +0300123 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
124 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
125 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
David Updegraff53a5c422007-06-11 10:41:07 -0500126
Claudiu Manoil876d4512013-09-30 12:44:40 +0300127 value = 1 << (31-whichbit);
David Updegraff53a5c422007-06-11 10:41:07 -0500128
Claudiu Manoil876d4512013-09-30 12:44:40 +0300129 if (set)
130 setbits_be32(&regs->hash.gaddr0 + whichreg, value);
131 else
132 clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
133
David Updegraff53a5c422007-06-11 10:41:07 -0500134 return 0;
135}
136#endif /* Multicast TFTP ? */
Mingkai Hu90751912011-01-27 12:52:46 +0800137
138/* Initialized required registers to appropriate values, zeroing
139 * those we don't care about (unless zero is bad, in which case,
140 * choose a more appropriate value)
141 */
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300142static void init_registers(struct tsec __iomem *regs)
Mingkai Hu90751912011-01-27 12:52:46 +0800143{
144 /* Clear IEVENT */
145 out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
146
147 out_be32(&regs->imask, IMASK_INIT_CLEAR);
148
149 out_be32(&regs->hash.iaddr0, 0);
150 out_be32(&regs->hash.iaddr1, 0);
151 out_be32(&regs->hash.iaddr2, 0);
152 out_be32(&regs->hash.iaddr3, 0);
153 out_be32(&regs->hash.iaddr4, 0);
154 out_be32(&regs->hash.iaddr5, 0);
155 out_be32(&regs->hash.iaddr6, 0);
156 out_be32(&regs->hash.iaddr7, 0);
157
158 out_be32(&regs->hash.gaddr0, 0);
159 out_be32(&regs->hash.gaddr1, 0);
160 out_be32(&regs->hash.gaddr2, 0);
161 out_be32(&regs->hash.gaddr3, 0);
162 out_be32(&regs->hash.gaddr4, 0);
163 out_be32(&regs->hash.gaddr5, 0);
164 out_be32(&regs->hash.gaddr6, 0);
165 out_be32(&regs->hash.gaddr7, 0);
166
167 out_be32(&regs->rctrl, 0x00000000);
168
169 /* Init RMON mib registers */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300170 memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
Mingkai Hu90751912011-01-27 12:52:46 +0800171
172 out_be32(&regs->rmon.cam1, 0xffffffff);
173 out_be32(&regs->rmon.cam2, 0xffffffff);
174
175 out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
176
177 out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
178
179 out_be32(&regs->attr, ATTR_INIT_SETTINGS);
180 out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
181
182}
183
184/* Configure maccfg2 based on negotiated speed and duplex
185 * reported by PHY handling code
186 */
Andy Fleming063c1262011-04-08 02:10:54 -0500187static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
Mingkai Hu90751912011-01-27 12:52:46 +0800188{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300189 struct tsec __iomem *regs = priv->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800190 u32 ecntrl, maccfg2;
191
Andy Fleming063c1262011-04-08 02:10:54 -0500192 if (!phydev->link) {
193 printf("%s: No link.\n", phydev->dev->name);
Mingkai Hu90751912011-01-27 12:52:46 +0800194 return;
195 }
196
197 /* clear all bits relative with interface mode */
198 ecntrl = in_be32(&regs->ecntrl);
199 ecntrl &= ~ECNTRL_R100;
200
201 maccfg2 = in_be32(&regs->maccfg2);
202 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
203
Andy Fleming063c1262011-04-08 02:10:54 -0500204 if (phydev->duplex)
Mingkai Hu90751912011-01-27 12:52:46 +0800205 maccfg2 |= MACCFG2_FULL_DUPLEX;
206
Andy Fleming063c1262011-04-08 02:10:54 -0500207 switch (phydev->speed) {
Mingkai Hu90751912011-01-27 12:52:46 +0800208 case 1000:
209 maccfg2 |= MACCFG2_GMII;
210 break;
211 case 100:
212 case 10:
213 maccfg2 |= MACCFG2_MII;
214
215 /* Set R100 bit in all modes although
216 * it is only used in RGMII mode
217 */
Andy Fleming063c1262011-04-08 02:10:54 -0500218 if (phydev->speed == 100)
Mingkai Hu90751912011-01-27 12:52:46 +0800219 ecntrl |= ECNTRL_R100;
220 break;
221 default:
Andy Fleming063c1262011-04-08 02:10:54 -0500222 printf("%s: Speed was bad\n", phydev->dev->name);
Mingkai Hu90751912011-01-27 12:52:46 +0800223 break;
224 }
225
226 out_be32(&regs->ecntrl, ecntrl);
227 out_be32(&regs->maccfg2, maccfg2);
228
Andy Fleming063c1262011-04-08 02:10:54 -0500229 printf("Speed: %d, %s duplex%s\n", phydev->speed,
230 (phydev->duplex) ? "full" : "half",
231 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
Mingkai Hu90751912011-01-27 12:52:46 +0800232}
233
chenhui zhaoaada81d2011-10-03 08:38:50 -0500234#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
235/*
236 * When MACCFG1[Rx_EN] is enabled during system boot as part
237 * of the eTSEC port initialization sequence,
238 * the eTSEC Rx logic may not be properly initialized.
239 */
240void redundant_init(struct eth_device *dev)
241{
242 struct tsec_private *priv = dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300243 struct tsec __iomem *regs = priv->regs;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500244 uint t, count = 0;
245 int fail = 1;
246 static const u8 pkt[] = {
247 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
248 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
249 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
250 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
251 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
252 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
253 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
254 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
255 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
256 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
257 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
258 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
259 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
260 0x71, 0x72};
261
262 /* Enable promiscuous mode */
263 setbits_be32(&regs->rctrl, 0x8);
264 /* Enable loopback mode */
265 setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
266 /* Enable transmit and receive */
267 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
268
269 /* Tell the DMA it is clear to go */
270 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
271 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
272 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
273 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
Alison Wang52d00a82014-09-05 13:52:38 +0800274#ifdef CONFIG_LS102XA
275 setbits_be32(&regs->dmactrl, DMACTRL_LE);
276#endif
chenhui zhaoaada81d2011-10-03 08:38:50 -0500277
278 do {
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300279 uint16_t status;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500280 tsec_send(dev, (void *)pkt, sizeof(pkt));
281
282 /* Wait for buffer to be received */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300283 for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
chenhui zhaoaada81d2011-10-03 08:38:50 -0500284 if (t >= 10 * TOUT_LOOP) {
285 printf("%s: tsec: rx error\n", dev->name);
286 break;
287 }
288 }
289
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300290 if (!memcmp(pkt, (void *)NetRxPackets[rx_idx], sizeof(pkt)))
chenhui zhaoaada81d2011-10-03 08:38:50 -0500291 fail = 0;
292
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300293 out_be16(&rxbd[rx_idx].length, 0);
294 status = RXBD_EMPTY;
295 if ((rx_idx + 1) == PKTBUFSRX)
296 status |= RXBD_WRAP;
297 out_be16(&rxbd[rx_idx].status, status);
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300298 rx_idx = (rx_idx + 1) % PKTBUFSRX;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500299
300 if (in_be32(&regs->ievent) & IEVENT_BSY) {
301 out_be32(&regs->ievent, IEVENT_BSY);
302 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
303 }
304 if (fail) {
305 printf("loopback recv packet error!\n");
306 clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
307 udelay(1000);
308 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
309 }
310 } while ((count++ < 4) && (fail == 1));
311
312 if (fail)
313 panic("eTSEC init fail!\n");
314 /* Disable promiscuous mode */
315 clrbits_be32(&regs->rctrl, 0x8);
316 /* Disable loopback mode */
317 clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
318}
319#endif
320
Mingkai Hu90751912011-01-27 12:52:46 +0800321/* Set up the buffers and their descriptors, and bring up the
322 * interface
323 */
324static void startup_tsec(struct eth_device *dev)
325{
Mingkai Hu90751912011-01-27 12:52:46 +0800326 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300327 struct tsec __iomem *regs = priv->regs;
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300328 uint16_t status;
329 int i;
Mingkai Hu90751912011-01-27 12:52:46 +0800330
Andy Fleming063c1262011-04-08 02:10:54 -0500331 /* reset the indices to zero */
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300332 rx_idx = 0;
333 tx_idx = 0;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500334#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
335 uint svr;
336#endif
Andy Fleming063c1262011-04-08 02:10:54 -0500337
Mingkai Hu90751912011-01-27 12:52:46 +0800338 /* Point to the buffer descriptors */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300339 out_be32(&regs->tbase, (u32)&txbd[0]);
340 out_be32(&regs->rbase, (u32)&rxbd[0]);
Mingkai Hu90751912011-01-27 12:52:46 +0800341
342 /* Initialize the Rx Buffer descriptors */
343 for (i = 0; i < PKTBUFSRX; i++) {
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300344 out_be16(&rxbd[i].status, RXBD_EMPTY);
345 out_be16(&rxbd[i].length, 0);
346 out_be32(&rxbd[i].bufptr, (u32)NetRxPackets[i]);
Mingkai Hu90751912011-01-27 12:52:46 +0800347 }
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300348 status = in_be16(&rxbd[PKTBUFSRX - 1].status);
349 out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
Mingkai Hu90751912011-01-27 12:52:46 +0800350
351 /* Initialize the TX Buffer Descriptors */
352 for (i = 0; i < TX_BUF_CNT; i++) {
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300353 out_be16(&txbd[i].status, 0);
354 out_be16(&txbd[i].length, 0);
355 out_be32(&txbd[i].bufptr, 0);
Mingkai Hu90751912011-01-27 12:52:46 +0800356 }
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300357 status = in_be16(&txbd[TX_BUF_CNT - 1].status);
358 out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
Mingkai Hu90751912011-01-27 12:52:46 +0800359
chenhui zhaoaada81d2011-10-03 08:38:50 -0500360#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
361 svr = get_svr();
362 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
363 redundant_init(dev);
364#endif
Mingkai Hu90751912011-01-27 12:52:46 +0800365 /* Enable Transmit and Receive */
366 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
367
368 /* Tell the DMA it is clear to go */
369 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
370 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
371 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
372 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
Alison Wang52d00a82014-09-05 13:52:38 +0800373#ifdef CONFIG_LS102XA
374 setbits_be32(&regs->dmactrl, DMACTRL_LE);
375#endif
Mingkai Hu90751912011-01-27 12:52:46 +0800376}
377
378/* This returns the status bits of the device. The return value
379 * is never checked, and this is what the 8260 driver did, so we
380 * do the same. Presumably, this would be zero if there were no
381 * errors
382 */
Joe Hershbergerc8a60b52012-05-21 09:46:36 +0000383static int tsec_send(struct eth_device *dev, void *packet, int length)
Mingkai Hu90751912011-01-27 12:52:46 +0800384{
Mingkai Hu90751912011-01-27 12:52:46 +0800385 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300386 struct tsec __iomem *regs = priv->regs;
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300387 uint16_t status;
388 int result = 0;
389 int i;
Mingkai Hu90751912011-01-27 12:52:46 +0800390
391 /* Find an empty buffer descriptor */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300392 for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
Mingkai Hu90751912011-01-27 12:52:46 +0800393 if (i >= TOUT_LOOP) {
394 debug("%s: tsec: tx buffers full\n", dev->name);
395 return result;
396 }
397 }
398
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300399 out_be32(&txbd[tx_idx].bufptr, (u32)packet);
400 out_be16(&txbd[tx_idx].length, length);
401 status = in_be16(&txbd[tx_idx].status);
402 out_be16(&txbd[tx_idx].status, status |
403 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
Mingkai Hu90751912011-01-27 12:52:46 +0800404
405 /* Tell the DMA to go */
406 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
407
408 /* Wait for buffer to be transmitted */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300409 for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
Mingkai Hu90751912011-01-27 12:52:46 +0800410 if (i >= TOUT_LOOP) {
411 debug("%s: tsec: tx error\n", dev->name);
412 return result;
413 }
414 }
415
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300416 tx_idx = (tx_idx + 1) % TX_BUF_CNT;
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300417 result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
Mingkai Hu90751912011-01-27 12:52:46 +0800418
419 return result;
420}
421
422static int tsec_recv(struct eth_device *dev)
423{
Mingkai Hu90751912011-01-27 12:52:46 +0800424 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300425 struct tsec __iomem *regs = priv->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800426
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300427 while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
428 int length = in_be16(&rxbd[rx_idx].length);
429 uint16_t status = in_be16(&rxbd[rx_idx].status);
Mingkai Hu90751912011-01-27 12:52:46 +0800430
431 /* Send the packet up if there were no errors */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300432 if (!(status & RXBD_STATS))
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300433 NetReceive(NetRxPackets[rx_idx], length - 4);
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300434 else
435 printf("Got error %x\n", (status & RXBD_STATS));
Mingkai Hu90751912011-01-27 12:52:46 +0800436
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300437 out_be16(&rxbd[rx_idx].length, 0);
Mingkai Hu90751912011-01-27 12:52:46 +0800438
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300439 status = RXBD_EMPTY;
Mingkai Hu90751912011-01-27 12:52:46 +0800440 /* Set the wrap bit if this is the last element in the list */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300441 if ((rx_idx + 1) == PKTBUFSRX)
442 status |= RXBD_WRAP;
443 out_be16(&rxbd[rx_idx].status, status);
Mingkai Hu90751912011-01-27 12:52:46 +0800444
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300445 rx_idx = (rx_idx + 1) % PKTBUFSRX;
Mingkai Hu90751912011-01-27 12:52:46 +0800446 }
447
448 if (in_be32(&regs->ievent) & IEVENT_BSY) {
449 out_be32(&regs->ievent, IEVENT_BSY);
450 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
451 }
452
453 return -1;
454
455}
456
457/* Stop the interface */
458static void tsec_halt(struct eth_device *dev)
459{
460 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300461 struct tsec __iomem *regs = priv->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800462
463 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
464 setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
465
466 while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
467 != (IEVENT_GRSC | IEVENT_GTSC))
468 ;
469
470 clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
471
472 /* Shut down the PHY, as needed */
Andy Fleming063c1262011-04-08 02:10:54 -0500473 phy_shutdown(priv->phydev);
Mingkai Hu90751912011-01-27 12:52:46 +0800474}
475
476/* Initializes data structures and registers for the controller,
477 * and brings the interface up. Returns the link status, meaning
478 * that it returns success if the link is up, failure otherwise.
479 * This allows u-boot to find the first active controller.
480 */
481static int tsec_init(struct eth_device *dev, bd_t * bd)
482{
Mingkai Hu90751912011-01-27 12:52:46 +0800483 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300484 struct tsec __iomem *regs = priv->regs;
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300485 u32 tempval;
Timur Tabi11af8d62012-07-09 08:52:43 +0000486 int ret;
Mingkai Hu90751912011-01-27 12:52:46 +0800487
488 /* Make sure the controller is stopped */
489 tsec_halt(dev);
490
491 /* Init MACCFG2. Defaults to GMII */
492 out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
493
494 /* Init ECNTRL */
495 out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
496
497 /* Copy the station address into the address registers.
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300498 * For a station address of 0x12345678ABCD in transmission
499 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
500 * MACnADDR2 is set to 0x34120000.
501 */
502 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
503 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
Mingkai Hu90751912011-01-27 12:52:46 +0800504
505 out_be32(&regs->macstnaddr1, tempval);
506
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300507 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
Mingkai Hu90751912011-01-27 12:52:46 +0800508
509 out_be32(&regs->macstnaddr2, tempval);
510
Mingkai Hu90751912011-01-27 12:52:46 +0800511 /* Clear out (for the most part) the other registers */
512 init_registers(regs);
513
514 /* Ready the device for tx/rx */
515 startup_tsec(dev);
516
Andy Fleming063c1262011-04-08 02:10:54 -0500517 /* Start up the PHY */
Timur Tabi11af8d62012-07-09 08:52:43 +0000518 ret = phy_startup(priv->phydev);
519 if (ret) {
520 printf("Could not initialize PHY %s\n",
521 priv->phydev->dev->name);
522 return ret;
523 }
Andy Fleming063c1262011-04-08 02:10:54 -0500524
525 adjust_link(priv, priv->phydev);
526
Mingkai Hu90751912011-01-27 12:52:46 +0800527 /* If there's no link, fail */
Andy Fleming063c1262011-04-08 02:10:54 -0500528 return priv->phydev->link ? 0 : -1;
Mingkai Hu90751912011-01-27 12:52:46 +0800529}
530
Andy Fleming063c1262011-04-08 02:10:54 -0500531static phy_interface_t tsec_get_interface(struct tsec_private *priv)
532{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300533 struct tsec __iomem *regs = priv->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500534 u32 ecntrl;
535
536 ecntrl = in_be32(&regs->ecntrl);
537
538 if (ecntrl & ECNTRL_SGMII_MODE)
539 return PHY_INTERFACE_MODE_SGMII;
540
541 if (ecntrl & ECNTRL_TBI_MODE) {
542 if (ecntrl & ECNTRL_REDUCED_MODE)
543 return PHY_INTERFACE_MODE_RTBI;
544 else
545 return PHY_INTERFACE_MODE_TBI;
546 }
547
548 if (ecntrl & ECNTRL_REDUCED_MODE) {
549 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
550 return PHY_INTERFACE_MODE_RMII;
551 else {
552 phy_interface_t interface = priv->interface;
553
554 /*
555 * This isn't autodetected, so it must
556 * be set by the platform code.
557 */
558 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
559 (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
560 (interface == PHY_INTERFACE_MODE_RGMII_RXID))
561 return interface;
562
563 return PHY_INTERFACE_MODE_RGMII;
564 }
565 }
566
567 if (priv->flags & TSEC_GIGABIT)
568 return PHY_INTERFACE_MODE_GMII;
569
570 return PHY_INTERFACE_MODE_MII;
571}
572
573
Mingkai Hu90751912011-01-27 12:52:46 +0800574/* Discover which PHY is attached to the device, and configure it
575 * properly. If the PHY is not recognized, then return 0
576 * (failure). Otherwise, return 1
577 */
578static int init_phy(struct eth_device *dev)
579{
580 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Andy Fleming063c1262011-04-08 02:10:54 -0500581 struct phy_device *phydev;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300582 struct tsec __iomem *regs = priv->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500583 u32 supported = (SUPPORTED_10baseT_Half |
584 SUPPORTED_10baseT_Full |
585 SUPPORTED_100baseT_Half |
586 SUPPORTED_100baseT_Full);
587
588 if (priv->flags & TSEC_GIGABIT)
589 supported |= SUPPORTED_1000baseT_Full;
Mingkai Hu90751912011-01-27 12:52:46 +0800590
591 /* Assign a Physical address to the TBI */
592 out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
593
Andy Fleming063c1262011-04-08 02:10:54 -0500594 priv->interface = tsec_get_interface(priv);
Mingkai Hu90751912011-01-27 12:52:46 +0800595
Andy Fleming063c1262011-04-08 02:10:54 -0500596 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
Mingkai Hu90751912011-01-27 12:52:46 +0800597 tsec_configure_serdes(priv);
598
Andy Fleming063c1262011-04-08 02:10:54 -0500599 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
Mingkai Hu90751912011-01-27 12:52:46 +0800600
Andy Fleming063c1262011-04-08 02:10:54 -0500601 phydev->supported &= supported;
602 phydev->advertising = phydev->supported;
603
604 priv->phydev = phydev;
605
606 phy_config(phydev);
Mingkai Hu90751912011-01-27 12:52:46 +0800607
608 return 1;
609}
610
611/* Initialize device structure. Returns success if PHY
612 * initialization succeeded (i.e. if it recognizes the PHY)
613 */
614static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
615{
616 struct eth_device *dev;
617 int i;
618 struct tsec_private *priv;
619
620 dev = (struct eth_device *)malloc(sizeof *dev);
621
622 if (NULL == dev)
623 return 0;
624
625 memset(dev, 0, sizeof *dev);
626
627 priv = (struct tsec_private *)malloc(sizeof(*priv));
628
629 if (NULL == priv)
630 return 0;
631
Mingkai Hu90751912011-01-27 12:52:46 +0800632 priv->regs = tsec_info->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800633 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
634
635 priv->phyaddr = tsec_info->phyaddr;
636 priv->flags = tsec_info->flags;
637
638 sprintf(dev->name, tsec_info->devname);
Andy Fleming063c1262011-04-08 02:10:54 -0500639 priv->interface = tsec_info->interface;
640 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
Mingkai Hu90751912011-01-27 12:52:46 +0800641 dev->iobase = 0;
642 dev->priv = priv;
643 dev->init = tsec_init;
644 dev->halt = tsec_halt;
645 dev->send = tsec_send;
646 dev->recv = tsec_recv;
647#ifdef CONFIG_MCAST_TFTP
648 dev->mcast = tsec_mcast_addr;
649#endif
650
651 /* Tell u-boot to get the addr from the env */
652 for (i = 0; i < 6; i++)
653 dev->enetaddr[i] = 0;
654
655 eth_register(dev);
656
657 /* Reset the MAC */
658 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
659 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
660 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
661
Mingkai Hu90751912011-01-27 12:52:46 +0800662 /* Try to initialize PHY here, and return */
663 return init_phy(dev);
664}
665
666/*
667 * Initialize all the TSEC devices
668 *
669 * Returns the number of TSEC devices that were initialized
670 */
671int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
672{
673 int i;
674 int ret, count = 0;
675
676 for (i = 0; i < num; i++) {
677 ret = tsec_initialize(bis, &tsecs[i]);
678 if (ret > 0)
679 count += ret;
680 }
681
682 return count;
683}
684
685int tsec_standard_init(bd_t *bis)
686{
Andy Fleming063c1262011-04-08 02:10:54 -0500687 struct fsl_pq_mdio_info info;
688
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300689 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
Andy Fleming063c1262011-04-08 02:10:54 -0500690 info.name = DEFAULT_MII_NAME;
691
692 fsl_pq_mdio_init(bis, &info);
693
Mingkai Hu90751912011-01-27 12:52:46 +0800694 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
695}