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gerrit.cesnet.cz / github / trini / u-boot / ff4681c9285b2b4d24552a19cacc1769fe2fc7e0 / . / include / configs / MPC837XERDB.h
blob: 2da4f290f91c861e21dc7d909f84ef8f58b655ea [file] [log] [blame]
Kim Phillips5e918a92008-01-16 00:38:05 -0600[diff] [blame]1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25/*
26 * High Level Configuration Options
27 */
28#define CONFIG_E300 1 /* E300 family */
29#define CONFIG_MPC83XX 1 /* MPC83XX family */
30#define CONFIG_MPC837X 1 /* MPC837X CPU specific */
31#define CONFIG_MPC837XERDB 1
32
33#define CONFIG_PCI 1
34
35/*
36 * System Clock Setup
37 */
38#ifdef CONFIG_PCISLAVE
39#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
40#else
41#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
42#define CONFIG_83XX_GENERIC_PCI 1
43#endif
44
45#ifndef CONFIG_SYS_CLK_FREQ
46#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
47#endif
48
49/*
50 * Hardware Reset Configuration Word
51 */
52#define CFG_HRCW_LOW (\
53 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
54 HRCWL_DDR_TO_SCB_CLK_1X1 |\
55 HRCWL_SVCOD_DIV_2 |\
56 HRCWL_CSB_TO_CLKIN_5X1 |\
57 HRCWL_CORE_TO_CSB_2X1)
58
59#ifdef CONFIG_PCISLAVE
60#define CFG_HRCW_HIGH (\
61 HRCWH_PCI_AGENT |\
62 HRCWH_PCI1_ARBITER_DISABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_FROM_0XFFF00100 |\
65 HRCWH_BOOTSEQ_DISABLE |\
66 HRCWH_SW_WATCHDOG_DISABLE |\
67 HRCWH_ROM_LOC_LOCAL_16BIT |\
68 HRCWH_RL_EXT_LEGACY |\
69 HRCWH_TSEC1M_IN_RGMII |\
70 HRCWH_TSEC2M_IN_RGMII |\
71 HRCWH_BIG_ENDIAN |\
72 HRCWH_LDP_CLEAR)
73#else
74#define CFG_HRCW_HIGH (\
75 HRCWH_PCI_HOST |\
76 HRCWH_PCI1_ARBITER_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT |\
82 HRCWH_RL_EXT_LEGACY |\
83 HRCWH_TSEC1M_IN_RGMII |\
84 HRCWH_TSEC2M_IN_RGMII |\
85 HRCWH_BIG_ENDIAN |\
86 HRCWH_LDP_CLEAR)
87#endif
88
89/* System performance - define the value i.e. CFG_XXX
90*/
91
92/* Arbiter Configuration Register */
93#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
94#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
95
96/* System Priority Control Regsiter */
97#define CFG_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
98
99/* System Clock Configuration Register */
100#define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
101#define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
102#define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */
103
104/*
105 * System IO Config
106 */
107#define CFG_SICRH 0x08200000
108#define CFG_SICRL 0x00000000
109
110/*
111 * Output Buffer Impedance
112 */
113#define CFG_OBIR 0x30100000
114
115/*
116 * IMMR new address
117 */
118#define CFG_IMMR 0xE0000000
119
120/*
121 * DDR Setup
122 */
123#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
124#define CFG_SDRAM_BASE CFG_DDR_BASE
125#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
126#define CFG_DDR_SDRAM_CLK_CNTL 0x03000000
127#define CFG_83XX_DDR_USES_CS0
128
129#define CFG_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
130
131#undef CONFIG_DDR_ECC /* support DDR ECC function */
132#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
133
134#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
135
136/*
137 * Manually set up DDR parameters
138 */
139#define CFG_DDR_SIZE 256 /* MB */
140#define CFG_DDR_CS0_BNDS 0x0000000f
141#define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
142 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
143
144#define CFG_DDR_TIMING_3 0x00000000
145#define CFG_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
146 | (0 << TIMING_CFG0_WRT_SHIFT) \
147 | (0 << TIMING_CFG0_RRT_SHIFT) \
148 | (0 << TIMING_CFG0_WWT_SHIFT) \
149 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
150 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
151 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
152 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
153 /* 0x00220802 */
154 /* 0x00260802 */ /* DDR400 */
155#define CFG_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
156 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
157 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
158 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
159 | (13 << TIMING_CFG1_REFREC_SHIFT) \
160 | (3 << TIMING_CFG1_WRREC_SHIFT) \
161 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
162 | (2 << TIMING_CFG1_WRTORD_SHIFT))
163 /* 0x3935d322 */
164 /* 0x3937d322 */
165#define CFG_DDR_TIMING_2 0x02984cc8
166
167#define CFG_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
168 | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
169 /* 0x06090100 */
170
171#if defined(CONFIG_DDR_2T_TIMING)
172#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
173 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
174 | SDRAM_CFG_2T_EN \
175 | SDRAM_CFG_DBW_32)
176#else
177#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
178 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
179 /* 0x43000000 */
180#endif
181#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
182#define CFG_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
183 | (0x0442 << SDRAM_MODE_SD_SHIFT))
184 /* 0x04400442 */ /* DDR400 */
185#define CFG_DDR_MODE2 0x00000000;
186
187/*
188 * Memory test
189 */
190#undef CFG_DRAM_TEST /* memory test, takes time */
191#define CFG_MEMTEST_START 0x00040000 /* memtest region */
192#define CFG_MEMTEST_END 0x0ef70010
193
194/*
195 * The reserved memory
196 */
197#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
198
199#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
200#define CFG_RAMBOOT
201#else
202#undef CFG_RAMBOOT
203#endif
204
205#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
206#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
207
208/*
209 * Initial RAM Base Address Setup
210 */
211#define CFG_INIT_RAM_LOCK 1
212#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
213#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
214#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
215#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
216
217/*
218 * Local Bus Configuration & Clock Setup
219 */
220#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
221#define CFG_LBC_LBCR 0x00000000
222
223/*
224 * FLASH on the Local Bus
225 */
226#define CFG_FLASH_CFI /* use the Common Flash Interface */
227#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
228#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
229#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
230
231#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
232#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
233
234#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
235#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
236
237#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
238 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
239 BR_V) /* valid */
240#define CFG_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
241 | OR_GPCM_XACS \
242 | OR_GPCM_SCY_9 \
243 | OR_GPCM_EHTR \
244 | OR_GPCM_EAD)
245 /* 0xFF806FF7 TODO SLOW 8 MB flash size */
246
247#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
248#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
249
250#undef CFG_FLASH_CHECKSUM
251#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
252#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
253
254#define CFG_VSC7385_BASE 0xF0000000
255
256/* VSC7385 Gigabit Switch support */
257#define CONFIG_VSC7385_ENET
258#define CFG_BR2_PRELIM 0xf0000801 /* Base address */
259#define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
260#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */
261#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
262
263/*
264 * Serial Port
265 */
266#define CONFIG_CONS_INDEX 1
267#undef CONFIG_SERIAL_SOFTWARE_FIFO
268#define CFG_NS16550
269#define CFG_NS16550_SERIAL
270#define CFG_NS16550_REG_SIZE 1
271#define CFG_NS16550_CLK get_bus_freq(0)
272
273#define CFG_BAUDRATE_TABLE \
274 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
275
276#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
277#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
278
279/* Use the HUSH parser */
280#define CFG_HUSH_PARSER
281#ifdef CFG_HUSH_PARSER
282#define CFG_PROMPT_HUSH_PS2 "> "
283#endif
284
285/* Pass open firmware flat tree */
286#define CONFIG_OF_LIBFDT 1
287#define CONFIG_OF_BOARD_SETUP 1
288
289/* I2C */
290#define CONFIG_HARD_I2C /* I2C with hardware support */
291#undef CONFIG_SOFT_I2C /* I2C bit-banged */
292#define CONFIG_FSL_I2C
293#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
294#define CFG_I2C_SLAVE 0x7F
295#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
296#define CFG_I2C_OFFSET 0x3000
297#define CFG_I2C2_OFFSET 0x3100
298
299/*
300 * Config on-board RTC
301 */
302#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
303#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
304
305/*
306 * General PCI
307 * Addresses are mapped 1-1.
308 */
309#define CFG_PCI_MEM_BASE 0x80000000
310#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
311#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
312#define CFG_PCI_MMIO_BASE 0x90000000
313#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
314#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
315#define CFG_PCI_IO_BASE 0xE0300000
316#define CFG_PCI_IO_PHYS 0xE0300000
317#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
318
319#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
320#define CFG_PCI_SLV_MEM_BUS 0x00000000
321#define CFG_PCI_SLV_MEM_SIZE 0x80000000
322
323#ifdef CONFIG_PCI
324#define CONFIG_NET_MULTI
325#define CONFIG_PCI_PNP /* do pci plug-and-play */
326
327#undef CONFIG_EEPRO100
328#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
329#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
330#endif /* CONFIG_PCI */
331
332#ifndef CONFIG_NET_MULTI
333#define CONFIG_NET_MULTI 1
334#endif
335
336/*
337 * TSEC
338 */
339#define CONFIG_TSEC_ENET /* TSEC ethernet support */
340#define CFG_TSEC1_OFFSET 0x24000
341#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
342#define CFG_TSEC2_OFFSET 0x25000
343#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
344
345/*
346 * TSEC ethernet configuration
347 */
348#define CONFIG_GMII 1 /* MII PHY management */
349#define CONFIG_TSEC1 1
350#define CONFIG_TSEC1_NAME "TSEC0"
351#define CONFIG_TSEC2 1
352#define CONFIG_TSEC2_NAME "TSEC1"
353#define TSEC1_PHY_ADDR 2
354#define TSEC2_PHY_ADDR 0x1c
355#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
356#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
357#define TSEC1_PHYIDX 0
358#define TSEC2_PHYIDX 0
359
360
361/* Options are: TSEC[0-1] */
362#define CONFIG_ETHPRIME "TSEC0"
363
364/*
365 * Environment
366 */
367#ifndef CFG_RAMBOOT
368 #define CFG_ENV_IS_IN_FLASH 1
369 #define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
370 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
371 #define CFG_ENV_SIZE 0x4000
372#else
373 #define CFG_NO_FLASH 1 /* Flash is not usable now */
374 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
375 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-0x1000)
376 #define CFG_ENV_SIZE 0x2000
377#endif
378
379#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
380#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
381
382/*
383 * BOOTP options
384 */
385#define CONFIG_BOOTP_BOOTFILESIZE
386#define CONFIG_BOOTP_BOOTPATH
387#define CONFIG_BOOTP_GATEWAY
388#define CONFIG_BOOTP_HOSTNAME
389
390
391/*
392 * Command line configuration.
393 */
394#include <config_cmd_default.h>
395
396#define CONFIG_CMD_PING
397#define CONFIG_CMD_I2C
398#define CONFIG_CMD_MII
399#define CONFIG_CMD_DATE
400
401#if defined(CONFIG_PCI)
402#define CONFIG_CMD_PCI
403#endif
404
405#if defined(CFG_RAMBOOT)
406#undef CONFIG_CMD_ENV
407#undef CONFIG_CMD_LOADS
408#endif
409
410#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
411
412#undef CONFIG_WATCHDOG /* watchdog disabled */
413
414/*
415 * Miscellaneous configurable options
416 */
417#define CFG_LONGHELP /* undef to save memory */
418#define CFG_LOAD_ADDR 0x2000000 /* default load address */
419#define CFG_PROMPT "=> " /* Monitor Command Prompt */
420
421#if defined(CONFIG_CMD_KGDB)
422 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
423#else
424 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
425#endif
426
427#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
428#define CFG_MAXARGS 16 /* max number of command args */
429#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
430#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
431
432/*
433 * For booting Linux, the board info and command line data
434 * have to be in the first 8 MB of memory, since this is
435 * the maximum mapped by the Linux kernel during initialization.
436 */
437#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
438
439/*
440 * Core HID Setup
441 */
442#define CFG_HID0_INIT 0x000000000
443#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
444#define CFG_HID2 HID2_HBE
445
446/*
447 * MMU Setup
448 */
449
450/* DDR: cache cacheable */
451#define CFG_SDRAM_LOWER CFG_SDRAM_BASE
452#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000)
453
454#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
455#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
456#define CFG_DBAT0L CFG_IBAT0L
457#define CFG_DBAT0U CFG_IBAT0U
458
459#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
460#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
461#define CFG_DBAT1L CFG_IBAT1L
462#define CFG_DBAT1U CFG_IBAT1U
463
464/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
465#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \
466 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
467#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
468#define CFG_DBAT2L CFG_IBAT2L
469#define CFG_DBAT2U CFG_IBAT2U
470
471/* L2 Switch: cache-inhibit and guarded */
472#define CFG_IBAT3L (CFG_VSC7385_BASE | BATL_PP_10 | \
473 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
474#define CFG_IBAT3U (CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
475#define CFG_DBAT3L CFG_IBAT3L
476#define CFG_DBAT3U CFG_IBAT3U
477
478/* FLASH: icache cacheable, but dcache-inhibit and guarded */
479#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
480#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
481#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \
482 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
483#define CFG_DBAT4U CFG_IBAT4U
484
485/* Stack in dcache: cacheable, no memory coherence */
486#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
487#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
488#define CFG_DBAT5L CFG_IBAT5L
489#define CFG_DBAT5U CFG_IBAT5U
490
491#ifdef CONFIG_PCI
492/* PCI MEM space: cacheable */
493#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
494#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
495#define CFG_DBAT6L CFG_IBAT6L
496#define CFG_DBAT6U CFG_IBAT6U
497/* PCI MMIO space: cache-inhibit and guarded */
498#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
499 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
500#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
501#define CFG_DBAT7L CFG_IBAT7L
502#define CFG_DBAT7U CFG_IBAT7U
503#else
504#define CFG_IBAT6L (0)
505#define CFG_IBAT6U (0)
506#define CFG_IBAT7L (0)
507#define CFG_IBAT7U (0)
508#define CFG_DBAT6L CFG_IBAT6L
509#define CFG_DBAT6U CFG_IBAT6U
510#define CFG_DBAT7L CFG_IBAT7L
511#define CFG_DBAT7U CFG_IBAT7U
512#endif
513
514/*
515 * Internal Definitions
516 *
517 * Boot Flags
518 */
519#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
520#define BOOTFLAG_WARM 0x02 /* Software reboot */
521
522#if defined(CONFIG_CMD_KGDB)
523#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
524#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
525#endif
526
527/*
528 * Environment Configuration
529 */
530#define CONFIG_ENV_OVERWRITE
531
532#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
533#define CONFIG_ETHADDR 00:04:9f:ef:04:01
534#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
535#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
536
537#define CONFIG_IPADDR 10.0.0.2
538#define CONFIG_SERVERIP 10.0.0.1
539#define CONFIG_GATEWAYIP 10.0.0.1
540#define CONFIG_NETMASK 255.0.0.0
541#define CONFIG_NETDEV eth1
542
543#define CONFIG_HOSTNAME mpc837x_rdb
544#define CONFIG_ROOTPATH /nfsroot
545#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
546#define CONFIG_BOOTFILE uImage
547#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
548#define CONFIG_FDTFILE mpc837x_rdb.dtb
549
550#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
551#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
552#define CONFIG_BAUDRATE 115200
553
554#define XMK_STR(x) #x
555#define MK_STR(x) XMK_STR(x)
556
557#define CONFIG_EXTRA_ENV_SETTINGS \
558 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
559 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
560 "tftpflash=tftp $loadaddr $uboot;" \
561 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
562 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
563 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
564 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
565 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
566 "fdtaddr=400000\0" \
567 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
568 "ramdiskaddr=1000000\0" \
569 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
570 "console=ttyS0\0" \
571 "setbootargs=setenv bootargs " \
572 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
573 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
574 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
575 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
576
577#define CONFIG_NFSBOOTCOMMAND \
578 "setenv rootdev /dev/nfs;" \
579 "run setbootargs;" \
580 "run setipargs;" \
581 "tftp $loadaddr $bootfile;" \
582 "tftp $fdtaddr $fdtfile;" \
583 "bootm $loadaddr - $fdtaddr"
584
585#define CONFIG_RAMBOOTCOMMAND \
586 "setenv rootdev /dev/ram;" \
587 "run setbootargs;" \
588 "tftp $ramdiskaddr $ramdiskfile;" \
589 "tftp $loadaddr $bootfile;" \
590 "tftp $fdtaddr $fdtfile;" \
591 "bootm $loadaddr $ramdiskaddr $fdtaddr"
592
593#undef MK_STR
594#undef XMK_STR
595
596#endif /* __CONFIG_H */