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wdenkc6097192002-11-03 00:24:07 +00001/*
Stefan Roesea47a12b2010-04-15 16:07:28 +02002 * arch/powerpc/kernel/pci_auto.c
wdenkc6097192002-11-03 00:24:07 +00003 *
4 * PCI autoconfiguration library
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * Copyright 2000 MontaVista Software Inc.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +000011 */
12
13#include <common.h>
Simon Glass4a2708a2015-01-14 21:37:04 -070014#include <errno.h>
wdenkc6097192002-11-03 00:24:07 +000015#include <pci.h>
16
17#undef DEBUG
18#ifdef DEBUG
19#define DEBUGF(x...) printf(x)
20#else
21#define DEBUGF(x...)
22#endif /* DEBUG */
23
24#define PCIAUTO_IDE_MODE_MASK 0x05
25
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
27#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
28#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
Gary Jennejohn81b73de2007-08-31 15:21:46 +020029#endif
30
wdenkc6097192002-11-03 00:24:07 +000031/*
32 *
33 */
34
Andrew Sharpcb2bf932012-08-29 14:16:29 +000035void pciauto_region_init(struct pci_region *res)
wdenkc6097192002-11-03 00:24:07 +000036{
Sergei Shtylyovb7598a42007-04-23 15:30:39 +020037 /*
38 * Avoid allocating PCI resources from address 0 -- this is illegal
39 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
40 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
41 */
42 res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
wdenkc6097192002-11-03 00:24:07 +000043}
44
Kumar Gala30e76d52008-10-21 08:36:08 -050045void pciauto_region_align(struct pci_region *res, pci_size_t size)
wdenkc6097192002-11-03 00:24:07 +000046{
47 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
48}
49
Andrew Sharpcb2bf932012-08-29 14:16:29 +000050int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
51 pci_addr_t *bar)
wdenkc6097192002-11-03 00:24:07 +000052{
Kumar Gala30e76d52008-10-21 08:36:08 -050053 pci_addr_t addr;
wdenkc6097192002-11-03 00:24:07 +000054
wdenk3c74e322004-02-22 23:46:08 +000055 if (!res) {
wdenkc6097192002-11-03 00:24:07 +000056 DEBUGF("No resource");
57 goto error;
58 }
59
60 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
61
wdenk3c74e322004-02-22 23:46:08 +000062 if (addr - res->bus_start + size > res->size) {
wdenkc6097192002-11-03 00:24:07 +000063 DEBUGF("No room in resource");
64 goto error;
65 }
66
67 res->bus_lower = addr + size;
68
Kumar Gala30e76d52008-10-21 08:36:08 -050069 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
wdenkc6097192002-11-03 00:24:07 +000070
71 *bar = addr;
72 return 0;
73
74 error:
Kumar Gala30e76d52008-10-21 08:36:08 -050075 *bar = (pci_addr_t)-1;
wdenkc6097192002-11-03 00:24:07 +000076 return -1;
77}
78
79/*
80 *
81 */
82
83void pciauto_setup_device(struct pci_controller *hose,
84 pci_dev_t dev, int bars_num,
85 struct pci_region *mem,
Kumar Galaa1790122006-01-11 13:24:15 -060086 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +000087 struct pci_region *io)
88{
Kumar Galacf5787f2012-09-19 04:47:36 +000089 u32 bar_response;
Kumar Gala30e76d52008-10-21 08:36:08 -050090 pci_size_t bar_size;
Andrew Sharpaf778c62012-08-01 12:27:16 +000091 u16 cmdstat = 0;
wdenkc6097192002-11-03 00:24:07 +000092 int bar, bar_nr = 0;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000093#ifndef CONFIG_PCI_ENUM_ONLY
94 pci_addr_t bar_value;
95 struct pci_region *bar_res;
wdenkc6097192002-11-03 00:24:07 +000096 int found_mem64 = 0;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000097#endif
wdenkc6097192002-11-03 00:24:07 +000098
Andrew Sharpaf778c62012-08-01 12:27:16 +000099 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
wdenkc6097192002-11-03 00:24:07 +0000100 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
101
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000102 for (bar = PCI_BASE_ADDRESS_0;
103 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
wdenkc6097192002-11-03 00:24:07 +0000104 /* Tickle the BAR and get the response */
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000105#ifndef CONFIG_PCI_ENUM_ONLY
wdenkc6097192002-11-03 00:24:07 +0000106 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000107#endif
wdenkc6097192002-11-03 00:24:07 +0000108 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
109
110 /* If BAR is not implemented go to the next BAR */
111 if (!bar_response)
112 continue;
113
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000114#ifndef CONFIG_PCI_ENUM_ONLY
wdenkc6097192002-11-03 00:24:07 +0000115 found_mem64 = 0;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000116#endif
wdenkc6097192002-11-03 00:24:07 +0000117
118 /* Check the BAR type and set our address mask */
wdenk3c74e322004-02-22 23:46:08 +0000119 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
Jin Zhengxiong-R64188bd22c2b2006-06-27 18:12:02 +0800120 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
121 & 0xffff) + 1;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000122#ifndef CONFIG_PCI_ENUM_ONLY
wdenkc6097192002-11-03 00:24:07 +0000123 bar_res = io;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000124#endif
wdenkc6097192002-11-03 00:24:07 +0000125
Kumar Gala30e76d52008-10-21 08:36:08 -0500126 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
wdenk3c74e322004-02-22 23:46:08 +0000127 } else {
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000128 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
Kumar Gala30e76d52008-10-21 08:36:08 -0500129 PCI_BASE_ADDRESS_MEM_TYPE_64) {
130 u32 bar_response_upper;
131 u64 bar64;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000132
133#ifndef CONFIG_PCI_ENUM_ONLY
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000134 pci_hose_write_config_dword(hose, dev, bar + 4,
135 0xffffffff);
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000136#endif
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000137 pci_hose_read_config_dword(hose, dev, bar + 4,
138 &bar_response_upper);
wdenkc6097192002-11-03 00:24:07 +0000139
Kumar Gala30e76d52008-10-21 08:36:08 -0500140 bar64 = ((u64)bar_response_upper << 32) | bar_response;
141
142 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000143#ifndef CONFIG_PCI_ENUM_ONLY
Kumar Gala30e76d52008-10-21 08:36:08 -0500144 found_mem64 = 1;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000145#endif
Kumar Gala30e76d52008-10-21 08:36:08 -0500146 } else {
147 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
148 }
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000149#ifndef CONFIG_PCI_ENUM_ONLY
Kumar Galaa1790122006-01-11 13:24:15 -0600150 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
151 bar_res = prefetch;
152 else
153 bar_res = mem;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000154#endif
wdenkc6097192002-11-03 00:24:07 +0000155
Kumar Gala30e76d52008-10-21 08:36:08 -0500156 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
wdenkc6097192002-11-03 00:24:07 +0000157 }
158
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000159#ifndef CONFIG_PCI_ENUM_ONLY
wdenk3c74e322004-02-22 23:46:08 +0000160 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
wdenkc6097192002-11-03 00:24:07 +0000161 /* Write it out and update our limit */
Kumar Gala30e76d52008-10-21 08:36:08 -0500162 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
wdenkc6097192002-11-03 00:24:07 +0000163
wdenk3c74e322004-02-22 23:46:08 +0000164 if (found_mem64) {
wdenkc6097192002-11-03 00:24:07 +0000165 bar += 4;
Kumar Gala30e76d52008-10-21 08:36:08 -0500166#ifdef CONFIG_SYS_PCI_64BIT
167 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
168#else
169 /*
170 * If we are a 64-bit decoder then increment to the
171 * upper 32 bits of the bar and force it to locate
172 * in the lower 4GB of memory.
173 */
wdenkc6097192002-11-03 00:24:07 +0000174 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
Kumar Gala30e76d52008-10-21 08:36:08 -0500175#endif
wdenkc6097192002-11-03 00:24:07 +0000176 }
177
wdenkc6097192002-11-03 00:24:07 +0000178 }
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000179#endif
180 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
181 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
wdenkc6097192002-11-03 00:24:07 +0000182
183 DEBUGF("\n");
184
185 bar_nr++;
186 }
187
Andrew Sharpaf778c62012-08-01 12:27:16 +0000188 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
Gary Jennejohn81b73de2007-08-31 15:21:46 +0200189 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
wdenkc6097192002-11-03 00:24:07 +0000191 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
192}
193
Simon Glass4a2708a2015-01-14 21:37:04 -0700194int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev)
195{
196 pci_addr_t bar_value;
197 pci_size_t bar_size;
198 u32 bar_response;
199 u16 cmdstat = 0;
200
201 pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe);
202 pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response);
203 if (!bar_response)
204 return -ENOENT;
205
206 bar_size = -(bar_response & ~1);
207 DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
208 if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) {
209 pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
210 bar_value);
211 }
212 DEBUGF("\n");
213 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
214 cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
215 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
216
217 return 0;
218}
219
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500220void pciauto_prescan_setup_bridge(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000221 pci_dev_t dev, int sub_bus)
222{
223 struct pci_region *pci_mem = hose->pci_mem;
Kumar Galaa1790122006-01-11 13:24:15 -0600224 struct pci_region *pci_prefetch = hose->pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000225 struct pci_region *pci_io = hose->pci_io;
David Feng6eefd522015-02-02 16:53:13 +0800226 u16 cmdstat, prefechable_64;
wdenkc6097192002-11-03 00:24:07 +0000227
Andrew Sharpaf778c62012-08-01 12:27:16 +0000228 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
David Feng6eefd522015-02-02 16:53:13 +0800229 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
230 &prefechable_64);
231 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
wdenkc6097192002-11-03 00:24:07 +0000232
233 /* Configure bus number registers */
Ed Swarthoute8b85f32007-07-11 14:52:08 -0500234 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
235 PCI_BUS(dev) - hose->first_busno);
236 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
237 sub_bus - hose->first_busno);
wdenkc6097192002-11-03 00:24:07 +0000238 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
239
wdenk3c74e322004-02-22 23:46:08 +0000240 if (pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000241 /* Round memory allocator to 1MB boundary */
242 pciauto_region_align(pci_mem, 0x100000);
243
244 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
245 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
246 (pci_mem->bus_lower & 0xfff00000) >> 16);
247
248 cmdstat |= PCI_COMMAND_MEMORY;
249 }
250
Kumar Galaa1790122006-01-11 13:24:15 -0600251 if (pci_prefetch) {
252 /* Round memory allocator to 1MB boundary */
253 pciauto_region_align(pci_prefetch, 0x100000);
254
255 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
256 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
257 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
David Feng6eefd522015-02-02 16:53:13 +0800258 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
259#ifdef CONFIG_SYS_PCI_64BIT
260 pci_hose_write_config_dword(hose, dev,
261 PCI_PREF_BASE_UPPER32,
262 pci_prefetch->bus_lower >> 32);
263#else
264 pci_hose_write_config_dword(hose, dev,
265 PCI_PREF_BASE_UPPER32,
266 0x0);
267#endif
Kumar Galaa1790122006-01-11 13:24:15 -0600268
269 cmdstat |= PCI_COMMAND_MEMORY;
270 } else {
271 /* We don't support prefetchable memory for now, so disable */
272 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
Matthew McClintocka4e11552006-06-28 10:44:23 -0500273 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
David Feng6eefd522015-02-02 16:53:13 +0800274 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
275 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
276 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
277 }
Kumar Galaa1790122006-01-11 13:24:15 -0600278 }
279
wdenk3c74e322004-02-22 23:46:08 +0000280 if (pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000281 /* Round I/O allocator to 4KB boundary */
282 pciauto_region_align(pci_io, 0x1000);
283
284 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
285 (pci_io->bus_lower & 0x0000f000) >> 8);
286 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
287 (pci_io->bus_lower & 0xffff0000) >> 16);
288
289 cmdstat |= PCI_COMMAND_IO;
290 }
291
wdenkc6097192002-11-03 00:24:07 +0000292 /* Enable memory and I/O accesses, enable bus master */
Andrew Sharpaf778c62012-08-01 12:27:16 +0000293 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
294 cmdstat | PCI_COMMAND_MASTER);
wdenkc6097192002-11-03 00:24:07 +0000295}
296
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500297void pciauto_postscan_setup_bridge(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000298 pci_dev_t dev, int sub_bus)
299{
300 struct pci_region *pci_mem = hose->pci_mem;
Kumar Galaa1790122006-01-11 13:24:15 -0600301 struct pci_region *pci_prefetch = hose->pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000302 struct pci_region *pci_io = hose->pci_io;
303
304 /* Configure bus number registers */
Ed Swarthoute8b85f32007-07-11 14:52:08 -0500305 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
306 sub_bus - hose->first_busno);
wdenkc6097192002-11-03 00:24:07 +0000307
wdenk3c74e322004-02-22 23:46:08 +0000308 if (pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000309 /* Round memory allocator to 1MB boundary */
310 pciauto_region_align(pci_mem, 0x100000);
311
312 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000313 (pci_mem->bus_lower - 1) >> 16);
wdenkc6097192002-11-03 00:24:07 +0000314 }
315
Kumar Galaa1790122006-01-11 13:24:15 -0600316 if (pci_prefetch) {
David Feng6eefd522015-02-02 16:53:13 +0800317 u16 prefechable_64;
318
319 pci_hose_read_config_word(hose, dev,
320 PCI_PREF_MEMORY_LIMIT,
321 &prefechable_64);
322 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
323
Kumar Galaa1790122006-01-11 13:24:15 -0600324 /* Round memory allocator to 1MB boundary */
325 pciauto_region_align(pci_prefetch, 0x100000);
326
327 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000328 (pci_prefetch->bus_lower - 1) >> 16);
David Feng6eefd522015-02-02 16:53:13 +0800329 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
330#ifdef CONFIG_SYS_PCI_64BIT
331 pci_hose_write_config_dword(hose, dev,
332 PCI_PREF_LIMIT_UPPER32,
333 (pci_prefetch->bus_lower - 1) >> 32);
334#else
335 pci_hose_write_config_dword(hose, dev,
336 PCI_PREF_LIMIT_UPPER32,
337 0x0);
338#endif
Kumar Galaa1790122006-01-11 13:24:15 -0600339 }
340
wdenk3c74e322004-02-22 23:46:08 +0000341 if (pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000342 /* Round I/O allocator to 4KB boundary */
343 pciauto_region_align(pci_io, 0x1000);
344
345 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000346 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
wdenkc6097192002-11-03 00:24:07 +0000347 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000348 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
wdenkc6097192002-11-03 00:24:07 +0000349 }
350}
351
352/*
353 *
354 */
355
356void pciauto_config_init(struct pci_controller *hose)
357{
358 int i;
359
Thierry Reding010c4802013-09-20 15:50:50 +0200360 hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
wdenkc6097192002-11-03 00:24:07 +0000361
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000362 for (i = 0; i < hose->region_count; i++) {
wdenk3c74e322004-02-22 23:46:08 +0000363 switch(hose->regions[i].flags) {
wdenkc6097192002-11-03 00:24:07 +0000364 case PCI_REGION_IO:
365 if (!hose->pci_io ||
366 hose->pci_io->size < hose->regions[i].size)
367 hose->pci_io = hose->regions + i;
368 break;
369 case PCI_REGION_MEM:
370 if (!hose->pci_mem ||
371 hose->pci_mem->size < hose->regions[i].size)
372 hose->pci_mem = hose->regions + i;
373 break;
Kumar Galaa1790122006-01-11 13:24:15 -0600374 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
375 if (!hose->pci_prefetch ||
376 hose->pci_prefetch->size < hose->regions[i].size)
377 hose->pci_prefetch = hose->regions + i;
378 break;
wdenkc6097192002-11-03 00:24:07 +0000379 }
380 }
381
382
wdenk3c74e322004-02-22 23:46:08 +0000383 if (hose->pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000384 pciauto_region_init(hose->pci_mem);
385
Kumar Gala30e76d52008-10-21 08:36:08 -0500386 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
387 "\t\tPhysical Memory [%llx-%llxx]\n",
388 (u64)hose->pci_mem->bus_start,
389 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
390 (u64)hose->pci_mem->phys_start,
391 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
wdenkc6097192002-11-03 00:24:07 +0000392 }
393
Kumar Galaa1790122006-01-11 13:24:15 -0600394 if (hose->pci_prefetch) {
395 pciauto_region_init(hose->pci_prefetch);
396
Kumar Gala30e76d52008-10-21 08:36:08 -0500397 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
398 "\t\tPhysical Memory [%llx-%llx]\n",
399 (u64)hose->pci_prefetch->bus_start,
400 (u64)(hose->pci_prefetch->bus_start +
401 hose->pci_prefetch->size - 1),
402 (u64)hose->pci_prefetch->phys_start,
403 (u64)(hose->pci_prefetch->phys_start +
404 hose->pci_prefetch->size - 1));
Kumar Galaa1790122006-01-11 13:24:15 -0600405 }
406
wdenk3c74e322004-02-22 23:46:08 +0000407 if (hose->pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000408 pciauto_region_init(hose->pci_io);
409
Kumar Gala30e76d52008-10-21 08:36:08 -0500410 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
411 "\t\tPhysical Memory: [%llx-%llx]\n",
412 (u64)hose->pci_io->bus_start,
413 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
414 (u64)hose->pci_io->phys_start,
415 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500416
wdenkc6097192002-11-03 00:24:07 +0000417 }
418}
419
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000420/*
421 * HJF: Changed this to return int. I think this is required
wdenkc7de8292002-11-19 11:04:11 +0000422 * to get the correct result when scanning bridges
423 */
424int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
wdenkc6097192002-11-03 00:24:07 +0000425{
wdenkc7de8292002-11-19 11:04:11 +0000426 unsigned int sub_bus = PCI_BUS(dev);
wdenkc6097192002-11-03 00:24:07 +0000427 unsigned short class;
428 unsigned char prg_iface;
wdenk5653fc32004-02-08 22:55:38 +0000429 int n;
wdenkc6097192002-11-03 00:24:07 +0000430
431 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
432
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000433 switch (class) {
wdenkc6097192002-11-03 00:24:07 +0000434 case PCI_CLASS_BRIDGE_PCI:
Simon Glassff3e0772015-03-05 12:25:25 -0700435 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n",
436 PCI_DEV(dev));
437
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000438 pciauto_setup_device(hose, dev, 2, hose->pci_mem,
439 hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000440
Simon Glassff3e0772015-03-05 12:25:25 -0700441#ifdef CONFIG_DM_PCI
442 n = dm_pci_hose_probe_bus(hose, dev);
443 if (n < 0)
444 return n;
445 sub_bus = (unsigned int)n;
446#else
wdenk3c74e322004-02-22 23:46:08 +0000447 /* Passing in current_busno allows for sibling P2P bridges */
Simon Glassff3e0772015-03-05 12:25:25 -0700448 hose->current_busno++;
wdenk5653fc32004-02-08 22:55:38 +0000449 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
wdenkcd37d9e2004-02-10 00:03:41 +0000450 /*
wdenk3c74e322004-02-22 23:46:08 +0000451 * need to figure out if this is a subordinate bridge on the bus
wdenk5653fc32004-02-08 22:55:38 +0000452 * to be able to properly set the pri/sec/sub bridge registers.
453 */
454 n = pci_hose_scan_bus(hose, hose->current_busno);
wdenk8bde7f72003-06-27 21:31:46 +0000455
wdenk3c74e322004-02-22 23:46:08 +0000456 /* figure out the deepest we've gone for this leg */
Masahiro Yamadab4141192014-11-07 03:03:31 +0900457 sub_bus = max((unsigned int)n, sub_bus);
wdenkdb2f721f2003-03-06 00:58:30 +0000458 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
wdenk5653fc32004-02-08 22:55:38 +0000459
wdenkdb2f721f2003-03-06 00:58:30 +0000460 sub_bus = hose->current_busno;
Simon Glassff3e0772015-03-05 12:25:25 -0700461#endif
wdenkc6097192002-11-03 00:24:07 +0000462 break;
463
464 case PCI_CLASS_STORAGE_IDE:
465 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
wdenk3c74e322004-02-22 23:46:08 +0000466 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
467 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
468 return sub_bus;
469 }
wdenkc6097192002-11-03 00:24:07 +0000470
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000471 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
472 hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000473 break;
474
wdenk1cb8e982003-03-06 21:55:29 +0000475 case PCI_CLASS_BRIDGE_CARDBUS:
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000476 /*
477 * just do a minimal setup of the bridge,
478 * let the OS take care of the rest
479 */
480 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
481 hose->pci_prefetch, hose->pci_io);
wdenk1cb8e982003-03-06 21:55:29 +0000482
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000483 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
484 PCI_DEV(dev));
wdenk1cb8e982003-03-06 21:55:29 +0000485
Simon Glassff3e0772015-03-05 12:25:25 -0700486#ifndef CONFIG_DM_PCI
wdenk1cb8e982003-03-06 21:55:29 +0000487 hose->current_busno++;
Simon Glassff3e0772015-03-05 12:25:25 -0700488#endif
wdenk1cb8e982003-03-06 21:55:29 +0000489 break;
490
TsiChung Liewf33fca22008-03-30 01:19:06 -0500491#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
wdenke0ac62d2003-08-17 18:55:18 +0000492 case PCI_CLASS_BRIDGE_OTHER:
493 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
494 PCI_DEV(dev));
495 break;
496#endif
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200497#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200498 case PCI_CLASS_BRIDGE_OTHER:
499 /*
500 * The host/PCI bridge 1 seems broken in 8349 - it presents
501 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
502 * device claiming resources io/mem/irq.. we only allow for
503 * the PIMMR window to be allocated (BAR0 - 1MB size)
504 */
505 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000506 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
507 hose->pci_prefetch, hose->pci_io);
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200508 break;
509#endif
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000510
511 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
512 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
513
wdenkc6097192002-11-03 00:24:07 +0000514 default:
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000515 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
516 hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000517 break;
518 }
wdenkc7de8292002-11-19 11:04:11 +0000519
520 return sub_bus;
wdenkc6097192002-11-03 00:24:07 +0000521}