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gerrit.cesnet.cz / github / trini / u-boot / ff2b47f6a9cc10251cc601d34241ee02933c2187 / . / arch / arm / cpu / armv7 / rmobile / pfc-r8a7794.c
blob: e1236633337629f6c0a7e4bcc79497fb8562baac [file] [log] [blame]
Nobuhiro Iwamatsufafcfc52014-06-24 17:10:02 +0900[diff] [blame]1/*
2 * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
3 * This file is r8a7794 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#include <common.h>
11#include <sh_pfc.h>
12#include <asm/gpio.h>
13
14#define CPU_32_PORT(fn, pfx, sfx) \
15 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
16 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
17 PORT_1(fn, pfx##31, sfx)
18
19#define CPU_26_PORT(fn, pfx, sfx) \
20 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
21 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
22 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
23 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
24
25#define CPU_28_PORT(fn, pfx, sfx) \
26 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
27 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
28 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
29 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
30 PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
31
32/*
33 * GP_0_0_DATA -> GP_6_25_DATA
34 * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31]
35 * GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28],
36 * GP6[29]),GP6[30],GP6[31])
37 */
38#define CPU_ALL_PORT(fn, pfx, sfx) \
39 CPU_32_PORT(fn, pfx##_0_, sfx), \
40 CPU_26_PORT(fn, pfx##_1_, sfx), \
41 CPU_32_PORT(fn, pfx##_2_, sfx), \
42 CPU_32_PORT(fn, pfx##_3_, sfx), \
43 CPU_32_PORT(fn, pfx##_4_, sfx), \
44 CPU_28_PORT(fn, pfx##_5_, sfx), \
45 CPU_26_PORT(fn, pfx##_6_, sfx)
46
47#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
48#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
49 GP##pfx##_IN, GP##pfx##_OUT)
50
51#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
52#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
53
54#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
55#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
56#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
57
58
59#define PORT_10_REV(fn, pfx, sfx) \
60 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
61 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
62 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
63 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
64 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
65
66#define CPU_32_PORT_REV(fn, pfx, sfx) \
67 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
68 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
69 PORT_10_REV(fn, pfx, sfx)
70
71#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
72#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
73
74#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
75#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
76 FN_##ipsr, FN_##fn)
77
78enum {
79 PINMUX_RESERVED = 0,
80
81 PINMUX_DATA_BEGIN,
82 GP_ALL(DATA),
83 PINMUX_DATA_END,
84
85 PINMUX_INPUT_BEGIN,
86 GP_ALL(IN),
87 PINMUX_INPUT_END,
88
89 PINMUX_OUTPUT_BEGIN,
90 GP_ALL(OUT),
91 PINMUX_OUTPUT_END,
92
93 PINMUX_FUNCTION_BEGIN,
94 GP_ALL(FN),
95
96 /* GPSR0 */
97 FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
98 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
99 FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
100 FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
101 FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
102 FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
103 FN_IP2_17_16,
104
105 /* GPSR1 */
106 FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
107 FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
108 FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
109 FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
110 FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
111
112 /* GPSR2 */
113 FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
114 FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
115 FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
116 FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
117 FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
118 FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
119 FN_IP6_5_4, FN_IP6_7_6,
120
121 /* GPSR3 */
122 FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
123 FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
124 FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
125 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
126 FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
127 FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
128 FN_IP8_22_20,
129
130 /* GPSR4 */
131 FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
132 FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
133 FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
134 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
135 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
136 FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
137 FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
138
139 /* GPSR5 */
140 FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
141 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
142 FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
143 FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
144 FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
145 FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
146
147 /* GPSR6 */
148 FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
149 FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
150 FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
151 FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
152 FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
153
154 /*
155 * From IPSR0 to IPSR5 have been removed because they does not use.
156 */
157
158 /* IPSR6 */
159 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
160 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
161 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
162 FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
163 FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
164 FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
165 FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
166 FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
167 FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
168 FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
169 FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
170 FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
171 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
172 FN_ADIDATA, FN_AD_DI,
173
174 /* IPSR7 */
175 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
176 FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
177 FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
178 FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
179 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
180 FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
181 FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
182 FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
183 FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
184 FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
185 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
186 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
187 FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
188
189 /* IPSR8 */
190 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
191 FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
192 FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
193 FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
194 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
195 FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
196 FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
197 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
198 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
199 FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
200 FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
201 FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
202 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
203 FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
204 FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
205
206 /*
207 * From IPSR9 to IPSR10 have been removed because they does not use.
208 */
209
210 /* IPSR11 */
211 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
212 FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
213 FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
214 FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
215 FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
216 FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
217 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
218 FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
219 FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
220 FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
221 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
222 FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
223 FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
224 FN_ADICLK_B, FN_AD_CLK_B,
225
226 /*
227 * From IPSR12 to IPSR13 have been removed because they does not use.
228 */
229
230 /* MOD_SEL */
231 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
232 FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
233 FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
234 FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
235 FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
236 FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
237 FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
238 FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
239 FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
240 FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
241 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
242 FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
243 FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
244 FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
245
246 /* MOD_SEL2 */
247 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
248 FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
249 FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
250 FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
251 FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
252 FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
253 FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
254 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
255 FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
256 FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
257 FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
258 FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
259 FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
260 FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
261 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
262 FN_SEL_RDS_2, FN_SEL_RDS_3,
263
264 /* MOD_SEL3 */
265 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
266 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
267 FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
268 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
269 FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
270 FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
271 FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
272 FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
273 FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
274 FN_SEL_SSI9_1,
275 PINMUX_FUNCTION_END,
276
277 PINMUX_MARK_BEGIN,
278 A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
279
280 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
281
282 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
283 SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
284
285 SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
286 SD1_DATA2_MARK, SD1_DATA3_MARK,
287
288 /*
289 * From IPSR0 to IPSR5 have been removed because they does not use.
290 */
291
292 /* IPSR6 */
293 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
294 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
295 DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
296 CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
297 AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
298 VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
299 AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
300 VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
301 AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
302 I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
303 VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
304 AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
305 IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
306 I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
307 VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
308 ADIDATA_MARK, AD_DI_MARK,
309
310 /* IPSR7 */
311 ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
312 AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
313 MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
314 AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
315 CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
316 ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
317 AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
318 MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
319 ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
320 SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
321 IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
322 VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
323 SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
324 AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
325 SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
326 DREQ0_N_MARK, SCIFB1_RXD_MARK,
327
328 /* IPSR8 */
329 ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
330 AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
331 I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
332 HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
333 AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
334 SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
335 HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
336 AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
337 HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
338 I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
339 AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
340 SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
341 CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
342 DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
343 I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
344 TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
345 I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
346 FMCLK_C_MARK, RDS_CLK_MARK,
347
348 /*
349 * From IPSR9 to IPSR10 have been removed because they does not use.
350 */
351
352 /* IPSR11 */
353 SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
354 CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
355 DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
356 SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
357 SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
358 DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
359 SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
360 CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
361 DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
362 DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
363 AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
364 MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
365 PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
366 ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
367 PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
368
369 /*
370 * From IPSR12 to IPSR13 have been removed because they does not use.
371 */
372
373 PINMUX_MARK_END,
374};
375
376static pinmux_enum_t pinmux_data[] = {
377 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
378
379 PINMUX_DATA(A2_MARK, FN_A2),
380 PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
381 PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
382 PINMUX_DATA(DACK0_MARK, FN_DACK0),
383 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
384 PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
385 PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
386 PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
387 PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
388 PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
389 PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
390 PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
391 PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
392 PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
393 PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
394 PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
395 PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
396 PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
397 PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
398 PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
399 PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
400 PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
401
402 /*
403 * From IPSR0 to IPSR5 have been removed because they does not use.
404 */
405
406 /* IPSR6 */
407 PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
408 PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
409 PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
410 PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
411 PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
412 PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
413 PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
414 PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
415 PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
416 PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
417 PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
418 PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
419 PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
420 PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
421 PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
422 PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
423 PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
424 PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
425 PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
426 PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
427 PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
428 PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
429 PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
430 PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
431 PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
432 PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
433 PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
434 PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
435 PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
436 PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
437 PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
438 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
439 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
440 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2),
441 PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
442 PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
443 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
444 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
445 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2),
446 PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
447 PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
448 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
449 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
450 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2),
451 PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
452 PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
453 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
454 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
455 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
456 PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
457 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0),
458 PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
459 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
460 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
461 PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
462 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0),
463 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0),
464
465 /* IPSR7 */
466 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
467 PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
468 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
469 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
470 PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
471 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
472 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0),
473 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
474 PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
475 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
476 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
477 PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
478 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0),
479 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0),
480 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0),
481 PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
482 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
483 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
484 PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
485 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0),
486 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0),
487 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0),
488 PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
489 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
490 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
491 PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
492 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0),
493 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0),
494 PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
495 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
496 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
497 PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
498 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0),
499 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
500 PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
501 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
502 PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
503 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
504 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0),
505 PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
506 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
507 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
508 PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
509 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
510 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
511 PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
512 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
513 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
514 PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
515 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
516 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
517 PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
518 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
519 PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
520 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
521 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0),
522 PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
523 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
524 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
525 PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
526 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
527 PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
528 PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
529
530 /* IPSR8 */
531 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0),
532 PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
533 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
534 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
535 PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
536 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
537 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
538 PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
539 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
540 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
541 PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
542 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
543 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
544 PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
545 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
546 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
547 PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
548 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
549 PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
550 PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
551 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
552 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
553 PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
554 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
555 PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
556 PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
557 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
558 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
559 PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
560 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
561 PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
562 PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
563 PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
564 PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
565 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
566 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
567 PINMUX_IPSR_DATA(IP8_19_17, PWM5),
568 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1),
569 PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
570 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
571 PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
572 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
573 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
574 PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
575 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0),
576 PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
577 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
578 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
579 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
580 PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
581 PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
582 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
583 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
584 PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
585 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
586 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
587 PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
588 PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
589 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
590 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
591 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2),
592 PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
593 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
594 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
595 PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
596 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
597 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
598 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2),
599 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0),
600
601 /*
602 * From IPSR9 to IPSR10 have been removed because they does not use.
603 */
604
605 /* IPSR11 */
606 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0),
607 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
608 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
609 PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
610 PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
611 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
612 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
613 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
614 PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
615 PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
616 PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
617 PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
618 PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
619 PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
620 PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0),
621 PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
622 PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
623 PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
624 PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
625 PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
626 PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
627 PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
628 PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
629 PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
630 PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
631 PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
632 PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
633 PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
634 PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0),
635 PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
636 PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
637 PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
638 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
639 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
640 PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
641 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
642 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
643 PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
644 PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
645 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
646 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
647 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1),
648 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1),
649 PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
650 PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
651 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
652 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
653 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
654 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1),
655 PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
656 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
657 PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
658 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1),
659 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1),
660
661 /*
662 * From IPSR12 to IPSR13 have been removed because they does not use.
663 */
664};
665
666static struct pinmux_gpio pinmux_gpios[] = {
667 PINMUX_GPIO_GP_ALL(),
668
669 GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0),
670 GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
671 GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD),
672 GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2),
673 GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP),
674 GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
675 GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
676
677 /*
678 * From IPSR0 to IPSR5 have been removed because they does not use
679 */
680
681 /* IPSR6 */
682 GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
683 GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE),
684 GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP),
685 GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB),
686 GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK),
687 GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV),
688 GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2),
689 GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2),
690 GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5),
691 GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5),
692 GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB),
693 GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C),
694 GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA),
695 GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER),
696 GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C),
697 GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N),
698 GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B),
699 GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0),
700 GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK),
701 GPIO_FN(ADIDATA), GPIO_FN(AD_DI),
702
703 /* IPSR7 */
704 GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B),
705 GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP),
706 GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2),
707 GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1),
708 GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3),
709 GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2),
710 GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1),
711 GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D),
712 GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5),
713 GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4),
714 GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6),
715 GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B),
716 GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C),
717 GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B),
718 GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C),
719 GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B),
720 GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B),
721 GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0),
722 GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E),
723 GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N),
724 GPIO_FN(SCIFB1_RXD),
725
726 /* IPSR8 */
727 GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B),
728 GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B),
729 GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C),
730 GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B),
731 GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C),
732 GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B),
733 GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D),
734 GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B),
735 GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D),
736 GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B),
737 GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS),
738 GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C),
739 GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK),
740 GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA),
741 GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK),
742 GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL),
743 GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0),
744 GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B),
745 GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5),
746 GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D),
747 GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD),
748 GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B),
749 GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK),
750
751 /*
752 * From IPSR9 to IPSR10 have been removed because they does not use.
753 */
754
755 /* IPSR11 */
756 GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C),
757 GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5),
758 GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1),
759 GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B),
760 GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13),
761 GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C),
762 GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14),
763 GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C),
764 GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15),
765 GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C),
766 GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B),
767 GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7),
768 GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D),
769 GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129),
770 GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B),
771 GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129),
772 GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B),
773 GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B),
774 GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B),
775
776 /*
777 * From IPSR12 to IPSR13 have been removed because they does not use.
778 */
779};
780
781static struct pinmux_cfg_reg pinmux_config_regs[] = {
782 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
783 GP_0_31_FN, FN_IP2_17_16,
784 GP_0_30_FN, FN_IP2_15_14,
785 GP_0_29_FN, FN_IP2_13_12,
786 GP_0_28_FN, FN_IP2_11_10,
787 GP_0_27_FN, FN_IP2_9_8,
788 GP_0_26_FN, FN_IP2_7_6,
789 GP_0_25_FN, FN_IP2_5_4,
790 GP_0_24_FN, FN_IP2_3_2,
791 GP_0_23_FN, FN_IP2_1_0,
792 GP_0_22_FN, FN_IP1_31_30,
793 GP_0_21_FN, FN_IP1_29_28,
794 GP_0_20_FN, FN_IP1_27,
795 GP_0_19_FN, FN_IP1_26,
796 GP_0_18_FN, FN_A2,
797 GP_0_17_FN, FN_IP1_24,
798 GP_0_16_FN, FN_IP1_23_22,
799 GP_0_15_FN, FN_IP1_21_20,
800 GP_0_14_FN, FN_IP1_19_18,
801 GP_0_13_FN, FN_IP1_17_15,
802 GP_0_12_FN, FN_IP1_14_13,
803 GP_0_11_FN, FN_IP1_12_11,
804 GP_0_10_FN, FN_IP1_10_8,
805 GP_0_9_FN, FN_IP1_7_6,
806 GP_0_8_FN, FN_IP1_5_4,
807 GP_0_7_FN, FN_IP1_3_2,
808 GP_0_6_FN, FN_IP1_1_0,
809 GP_0_5_FN, FN_IP0_31_30,
810 GP_0_4_FN, FN_IP0_29_28,
811 GP_0_3_FN, FN_IP0_27_26,
812 GP_0_2_FN, FN_IP0_25,
813 GP_0_1_FN, FN_IP0_24,
814 GP_0_0_FN, FN_IP0_23_22, }
815 },
816 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
817 0, 0,
818 0, 0,
819 0, 0,
820 0, 0,
821 0, 0,
822 0, 0,
823 GP_1_25_FN, FN_DACK0,
824 GP_1_24_FN, FN_IP7_31,
825 GP_1_23_FN, FN_IP4_1_0,
826 GP_1_22_FN, FN_WE1_N,
827 GP_1_21_FN, FN_WE0_N,
828 GP_1_20_FN, FN_IP3_31,
829 GP_1_19_FN, FN_IP3_30,
830 GP_1_18_FN, FN_IP3_29_27,
831 GP_1_17_FN, FN_IP3_26_24,
832 GP_1_16_FN, FN_IP3_23_21,
833 GP_1_15_FN, FN_IP3_20_18,
834 GP_1_14_FN, FN_IP3_17_15,
835 GP_1_13_FN, FN_IP3_14_13,
836 GP_1_12_FN, FN_IP3_12,
837 GP_1_11_FN, FN_IP3_11,
838 GP_1_10_FN, FN_IP3_10,
839 GP_1_9_FN, FN_IP3_9_8,
840 GP_1_8_FN, FN_IP3_7_6,
841 GP_1_7_FN, FN_IP3_5_4,
842 GP_1_6_FN, FN_IP3_3_2,
843 GP_1_5_FN, FN_IP3_1_0,
844 GP_1_4_FN, FN_IP2_31_30,
845 GP_1_3_FN, FN_IP2_29_27,
846 GP_1_2_FN, FN_IP2_26_24,
847 GP_1_1_FN, FN_IP2_23_21,
848 GP_1_0_FN, FN_IP2_20_18, }
849 },
850 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
851 GP_2_31_FN, FN_IP6_7_6,
852 GP_2_30_FN, FN_IP6_5_4,
853 GP_2_29_FN, FN_IP6_3_2,
854 GP_2_28_FN, FN_IP6_1_0,
855 GP_2_27_FN, FN_IP5_31_30,
856 GP_2_26_FN, FN_IP5_29_28,
857 GP_2_25_FN, FN_IP5_27_26,
858 GP_2_24_FN, FN_IP5_25_24,
859 GP_2_23_FN, FN_IP5_23_22,
860 GP_2_22_FN, FN_IP5_21_20,
861 GP_2_21_FN, FN_IP5_19_18,
862 GP_2_20_FN, FN_IP5_17_16,
863 GP_2_19_FN, FN_IP5_15_14,
864 GP_2_18_FN, FN_IP5_13_12,
865 GP_2_17_FN, FN_IP5_11_9,
866 GP_2_16_FN, FN_IP5_8_6,
867 GP_2_15_FN, FN_IP5_5_4,
868 GP_2_14_FN, FN_IP5_3_2,
869 GP_2_13_FN, FN_IP5_1_0,
870 GP_2_12_FN, FN_IP4_31_30,
871 GP_2_11_FN, FN_IP4_29_28,
872 GP_2_10_FN, FN_IP4_27_26,
873 GP_2_9_FN, FN_IP4_25_23,
874 GP_2_8_FN, FN_IP4_22_20,
875 GP_2_7_FN, FN_IP4_19_18,
876 GP_2_6_FN, FN_IP4_17_16,
877 GP_2_5_FN, FN_IP4_15_14,
878 GP_2_4_FN, FN_IP4_13_12,
879 GP_2_3_FN, FN_IP4_11_10,
880 GP_2_2_FN, FN_IP4_9_8,
881 GP_2_1_FN, FN_IP4_7_5,
882 GP_2_0_FN, FN_IP4_4_2 }
883 },
884 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
885 GP_3_31_FN, FN_IP8_22_20,
886 GP_3_30_FN, FN_IP8_19_17,
887 GP_3_29_FN, FN_IP8_16_15,
888 GP_3_28_FN, FN_IP8_14_12,
889 GP_3_27_FN, FN_IP8_11_9,
890 GP_3_26_FN, FN_IP8_8_6,
891 GP_3_25_FN, FN_IP8_5_3,
892 GP_3_24_FN, FN_IP8_2_0,
893 GP_3_23_FN, FN_IP7_29_27,
894 GP_3_22_FN, FN_IP7_26_24,
895 GP_3_21_FN, FN_IP7_23_21,
896 GP_3_20_FN, FN_IP7_20_18,
897 GP_3_19_FN, FN_IP7_17_15,
898 GP_3_18_FN, FN_IP7_14_12,
899 GP_3_17_FN, FN_IP7_11_9,
900 GP_3_16_FN, FN_IP7_8_6,
901 GP_3_15_FN, FN_IP7_5_3,
902 GP_3_14_FN, FN_IP7_2_0,
903 GP_3_13_FN, FN_IP6_31_29,
904 GP_3_12_FN, FN_IP6_28_26,
905 GP_3_11_FN, FN_IP6_25_23,
906 GP_3_10_FN, FN_IP6_22_20,
907 GP_3_9_FN, FN_IP6_19_17,
908 GP_3_8_FN, FN_IP6_16,
909 GP_3_7_FN, FN_IP6_15,
910 GP_3_6_FN, FN_IP6_14,
911 GP_3_5_FN, FN_IP6_13,
912 GP_3_4_FN, FN_IP6_12,
913 GP_3_3_FN, FN_IP6_11,
914 GP_3_2_FN, FN_IP6_10,
915 GP_3_1_FN, FN_IP6_9,
916 GP_3_0_FN, FN_IP6_8 }
917 },
918 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
919 GP_4_31_FN, FN_IP11_17_16,
920 GP_4_30_FN, FN_IP11_15_14,
921 GP_4_29_FN, FN_IP11_13_11,
922 GP_4_28_FN, FN_IP11_10_8,
923 GP_4_27_FN, FN_IP11_7_6,
924 GP_4_26_FN, FN_IP11_5_3,
925 GP_4_25_FN, FN_IP11_2_0,
926 GP_4_24_FN, FN_IP10_31_30,
927 GP_4_23_FN, FN_IP10_29_27,
928 GP_4_22_FN, FN_IP10_26_24,
929 GP_4_21_FN, FN_IP10_23_21,
930 GP_4_20_FN, FN_IP10_20_18,
931 GP_4_19_FN, FN_IP10_17_15,
932 GP_4_18_FN, FN_IP10_14_12,
933 GP_4_17_FN, FN_IP10_11_9,
934 GP_4_16_FN, FN_IP10_8_6,
935 GP_4_15_FN, FN_IP10_5_3,
936 GP_4_14_FN, FN_IP10_2_0,
937 GP_4_13_FN, FN_IP9_30_28,
938 GP_4_12_FN, FN_IP9_27_25,
939 GP_4_11_FN, FN_IP9_24_22,
940 GP_4_10_FN, FN_IP9_21_19,
941 GP_4_9_FN, FN_IP9_18_17,
942 GP_4_8_FN, FN_IP9_16_15,
943 GP_4_7_FN, FN_IP9_14_12,
944 GP_4_6_FN, FN_IP9_11_9,
945 GP_4_5_FN, FN_IP9_8_6,
946 GP_4_4_FN, FN_IP9_5_3,
947 GP_4_3_FN, FN_IP9_2_0,
948 GP_4_2_FN, FN_IP8_31_29,
949 GP_4_1_FN, FN_IP8_28_26,
950 GP_4_0_FN, FN_IP8_25_23 }
951 },
952 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
953 0, 0,
954 0, 0,
955 0, 0,
956 0, 0,
957 GP_5_27_FN, FN_USB1_OVC,
958 GP_5_26_FN, FN_USB1_PWEN,
959 GP_5_25_FN, FN_USB0_OVC,
960 GP_5_24_FN, FN_USB0_PWEN,
961 GP_5_23_FN, FN_IP13_26_24,
962 GP_5_22_FN, FN_IP13_23_21,
963 GP_5_21_FN, FN_IP13_20_18,
964 GP_5_20_FN, FN_IP13_17_15,
965 GP_5_19_FN, FN_IP13_14_12,
966 GP_5_18_FN, FN_IP13_11_9,
967 GP_5_17_FN, FN_IP13_8_6,
968 GP_5_16_FN, FN_IP13_5_3,
969 GP_5_15_FN, FN_IP13_2_0,
970 GP_5_14_FN, FN_IP12_29_27,
971 GP_5_13_FN, FN_IP12_26_24,
972 GP_5_12_FN, FN_IP12_23_21,
973 GP_5_11_FN, FN_IP12_20_18,
974 GP_5_10_FN, FN_IP12_17_15,
975 GP_5_9_FN, FN_IP12_14_13,
976 GP_5_8_FN, FN_IP12_12_11,
977 GP_5_7_FN, FN_IP12_10_9,
978 GP_5_6_FN, FN_IP12_8_6,
979 GP_5_5_FN, FN_IP12_5_3,
980 GP_5_4_FN, FN_IP12_2_0,
981 GP_5_3_FN, FN_IP11_29_27,
982 GP_5_2_FN, FN_IP11_26_24,
983 GP_5_1_FN, FN_IP11_23_21,
984 GP_5_0_FN, FN_IP11_20_18 }
985 },
986 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
987 0, 0,
988 0, 0,
989 0, 0,
990 0, 0,
991 0, 0,
992 0, 0,
993 GP_6_25_FN, FN_IP0_21_20,
994 GP_6_24_FN, FN_IP0_19_18,
995 GP_6_23_FN, FN_IP0_17,
996 GP_6_22_FN, FN_IP0_16,
997 GP_6_21_FN, FN_IP0_15,
998 GP_6_20_FN, FN_IP0_14,
999 GP_6_19_FN, FN_IP0_13,
1000 GP_6_18_FN, FN_IP0_12,
1001 GP_6_17_FN, FN_IP0_11,
1002 GP_6_16_FN, FN_IP0_10,
1003 GP_6_15_FN, FN_IP0_9_8,
1004 GP_6_14_FN, FN_IP0_0,
1005 GP_6_13_FN, FN_SD1_DATA3,
1006 GP_6_12_FN, FN_SD1_DATA2,
1007 GP_6_11_FN, FN_SD1_DATA1,
1008 GP_6_10_FN, FN_SD1_DATA0,
1009 GP_6_9_FN, FN_SD1_CMD,
1010 GP_6_8_FN, FN_SD1_CLK,
1011 GP_6_7_FN, FN_SD0_WP,
1012 GP_6_6_FN, FN_SD0_CD,
1013 GP_6_5_FN, FN_SD0_DATA3,
1014 GP_6_4_FN, FN_SD0_DATA2,
1015 GP_6_3_FN, FN_SD0_DATA1,
1016 GP_6_2_FN, FN_SD0_DATA0,
1017 GP_6_1_FN, FN_SD0_CMD,
1018 GP_6_0_FN, FN_SD0_CLK }
1019 },
1020
1021 /*
1022 * From IPSR0 to IPSR5 have been removed because they does not use.
1023 */
1024
1025 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
1026 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
1027 2, 2) {
1028 /* IP6_31_29 [3] */
1029 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
1030 FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
1031 /* IP6_28_26 [3] */
1032 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
1033 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
1034 /* IP6_25_23 [3] */
1035 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
1036 FN_AVB_COL, 0, 0, 0,
1037 /* IP6_22_20 [3] */
1038 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
1039 FN_AVB_RX_ER, 0, 0, 0,
1040 /* IP6_19_17 [3] */
1041 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
1042 FN_AVB_RXD7, 0, 0, 0,
1043 /* IP6_16 [1] */
1044 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
1045 /* IP6_15 [1] */
1046 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
1047 /* IP6_14 [1] */
1048 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
1049 /* IP6_13 [1] */
1050 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
1051 /* IP6_12 [1] */
1052 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
1053 /* IP6_11 [1] */
1054 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
1055 /* IP6_10 [1] */
1056 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
1057 /* IP6_9 [1] */
1058 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
1059 /* IP6_8 [1] */
1060 FN_VI0_CLK, FN_AVB_RX_CLK,
1061 /* IP6_7_6 [2] */
1062 FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
1063 /* IP6_5_4 [2] */
1064 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
1065 /* IP6_3_2 [2] */
1066 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
1067 /* IP6_1_0 [2] */
1068 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
1069 },
1070 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
1071 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
1072 /* IP7_31 [1] */
1073 FN_DREQ0_N, FN_SCIFB1_RXD,
1074 /* IP7_30 [1] */
1075 0, 0,
1076 /* IP7_29_27 [3] */
1077 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
1078 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
1079 /* IP7_26_24 [3] */
1080 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
1081 FN_SSI_SCK6_B, 0, 0, 0,
1082 /* IP7_23_21 [3] */
1083 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
1084 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
1085 /* IP7_20_18 [3] */
1086 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
1087 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
1088 /* IP7_17_15 [3] */
1089 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
1090 FN_SSI_SCK5_B, 0, 0, 0,
1091 /* IP7_14_12 [3] */
1092 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
1093 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
1094 /* IP7_11_9 [3] */
1095 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
1096 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
1097 /* IP7_8_6 [3] */
1098 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
1099 FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
1100 /* IP7_5_3 [3] */
1101 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
1102 FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
1103 /* IP7_2_0 [3] */
1104 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
1105 FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
1106 },
1107 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
1108 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
1109 /* IP8_31_29 [3] */
1110 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
1111 FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
1112 /* IP8_28_26 [3] */
1113 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
1114 FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
1115 /* IP8_25_23 [3] */
1116 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
1117 FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
1118 /* IP8_22_20 [3] */
1119 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
1120 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
1121 /* IP8_19_17 [3] */
1122 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
1123 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
1124 /* IP8_16_15 [2] */
1125 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
1126 /* IP8_14_12 [3] */
1127 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
1128 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
1129 /* IP8_11_9 [3] */
1130 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
1131 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
1132 /* IP8_8_6 [3] */
1133 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
1134 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
1135 /* IP8_5_3 [3] */
1136 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
1137 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
1138 /* IP8_2_0 [3] */
1139 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
1140 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
1141 },
1142
1143 /*
1144 * From IPSR9 to IPSR10 have been removed because they does not use.
1145 */
1146
1147 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
1148 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
1149 /* IP11_31_30 [2] */
1150 0, 0, 0, 0,
1151 /* IP11_29_27 [3] */
1152 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
1153 FN_AD_CLK_B, 0, 0, 0,
1154 /* IP11_26_24 [3] */
1155 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
1156 FN_AD_DO_B, 0, 0, 0,
1157 /* IP11_23_21 [3] */
1158 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
1159 FN_AD_DI_B, FN_PCMWE_N, 0, 0,
1160 /* IP11_20_18 [3] */
1161 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
1162 FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
1163 /* IP11_17_16 [2] */
1164 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
1165 /* IP11_15_14 [2] */
1166 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
1167 /* IP11_13_11 [3] */
1168 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
1169 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
1170 /* IP11_10_8 [3] */
1171 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
1172 FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
1173 /* IP11_7_6 [2] */
1174 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
1175 FN_CAN_DEBUGOUT13,
1176 /* IP11_5_3 [3] */
1177 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
1178 FN_CAN_DEBUGOUT12, 0, 0, 0,
1179 /* IP11_2_0 [3] */
1180 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
1181 FN_CAN_DEBUGOUT11, 0, 0, 0, }
1182 },
1183
1184 /*
1185 * From IPSR12 to IPSR13 have been removed because they does not use.
1186 */
1187
1188 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
1189 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
1190 2, 1) {
1191 /* SEL_ADG [2] */
1192 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
1193 /* SEL_ADI [1] */
1194 FN_SEL_ADI_0, FN_SEL_ADI_1,
1195 /* SEL_CAN [2] */
1196 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
1197 /* SEL_DARC [3] */
1198 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
1199 FN_SEL_DARC_4, 0, 0, 0,
1200 /* SEL_DR0 [1] */
1201 FN_SEL_DR0_0, FN_SEL_DR0_1,
1202 /* SEL_DR1 [1] */
1203 FN_SEL_DR1_0, FN_SEL_DR1_1,
1204 /* SEL_DR2 [1] */
1205 FN_SEL_DR2_0, FN_SEL_DR2_1,
1206 /* SEL_DR3 [1] */
1207 FN_SEL_DR3_0, FN_SEL_DR3_1,
1208 /* SEL_ETH [1] */
1209 FN_SEL_ETH_0, FN_SEL_ETH_1,
1210 /* SLE_FSN [1] */
1211 FN_SEL_FSN_0, FN_SEL_FSN_1,
1212 /* SEL_IC200 [3] */
1213 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
1214 FN_SEL_I2C00_4, 0, 0, 0,
1215 /* SEL_I2C01 [3] */
1216 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
1217 FN_SEL_I2C01_4, 0, 0, 0,
1218 /* SEL_I2C02 [3] */
1219 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
1220 FN_SEL_I2C02_4, 0, 0, 0,
1221 /* SEL_I2C03 [3] */
1222 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
1223 FN_SEL_I2C03_4, 0, 0, 0,
1224 /* SEL_I2C04 [3] */
1225 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
1226 FN_SEL_I2C04_4, 0, 0, 0,
1227 /* SEL_IIC00 [2] */
1228 FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
1229 /* SEL_AVB [1] */
1230 FN_SEL_AVB_0, FN_SEL_AVB_1, }
1231 },
1232 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
1233 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
1234 2, 2, 2, 1, 1, 2) {
1235 /* SEL_IEB [2] */
1236 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
1237 /* SEL_IIC0 [2] */
1238 FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
1239 /* SEL_LBS [1] */
1240 FN_SEL_LBS_0, FN_SEL_LBS_1,
1241 /* SEL_MSI1 [1] */
1242 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
1243 /* SEL_MSI2 [1] */
1244 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
1245 /* SEL_RAD [1] */
1246 FN_SEL_RAD_0, FN_SEL_RAD_1,
1247 /* SEL_RCN [1] */
1248 FN_SEL_RCN_0, FN_SEL_RCN_1,
1249 /* SEL_RSP [1] */
1250 FN_SEL_RSP_0, FN_SEL_RSP_1,
1251 /* SEL_SCIFA0 [2] */
1252 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
1253 FN_SEL_SCIFA0_3,
1254 /* SEL_SCIFA1 [2] */
1255 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
1256 /* SEL_SCIFA2 [1] */
1257 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
1258 /* SEL_SCIFA3 [1] */
1259 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
1260 /* SEL_SCIFA4 [2] */
1261 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
1262 FN_SEL_SCIFA4_3,
1263 /* SEL_SCIFA5 [2] */
1264 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
1265 FN_SEL_SCIFA5_3,
1266 /* SEL_SPDM [1] */
1267 FN_SEL_SPDM_0, FN_SEL_SPDM_1,
1268 /* SEL_TMU [1] */
1269 FN_SEL_TMU_0, FN_SEL_TMU_1,
1270 /* SEL_TSIF0 [2] */
1271 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
1272 /* SEL_CAN0 [2] */
1273 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
1274 /* SEL_CAN1 [2] */
1275 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
1276 /* SEL_HSCIF0 [1] */
1277 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
1278 /* SEL_HSCIF1 [1] */
1279 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
1280 /* SEL_RDS [2] */
1281 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
1282 },
1283 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
1284 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
1285 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
1286 /* SEL_SCIF0 [2] */
1287 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
1288 /* SEL_SCIF1 [2] */
1289 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
1290 /* SEL_SCIF2 [2] */
1291 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
1292 /* SEL_SCIF3 [1] */
1293 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
1294 /* SEL_SCIF4 [3] */
1295 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
1296 FN_SEL_SCIF4_4, 0, 0, 0,
1297 /* SEL_SCIF5 [2] */
1298 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
1299 /* SEL_SSI1 [1] */
1300 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
1301 /* SEL_SSI2 [1] */
1302 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
1303 /* SEL_SSI4 [1] */
1304 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
1305 /* SEL_SSI5 [1] */
1306 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
1307 /* SEL_SSI6 [1] */
1308 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
1309 /* SEL_SSI7 [1] */
1310 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
1311 /* SEL_SSI8 [1] */
1312 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
1313 /* SEL_SSI9 [1] */
1314 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
1315 /* RESEVED [1] */
1316 0, 0,
1317 /* RESEVED [1] */
1318 0, 0,
1319 /* RESEVED [1] */
1320 0, 0,
1321 /* RESEVED [1] */
1322 0, 0,
1323 /* RESEVED [1] */
1324 0, 0,
1325 /* RESEVED [1] */
1326 0, 0,
1327 /* RESEVED [1] */
1328 0, 0,
1329 /* RESEVED [1] */
1330 0, 0,
1331 /* RESEVED [1] */
1332 0, 0,
1333 /* RESEVED [1] */
1334 0, 0,
1335 /* RESEVED [1] */
1336 0, 0,
1337 /* RESEVED [1] */
1338 0, 0, }
1339 },
1340 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
1341 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
1342 0, 0,
1343 0, 0,
1344 0, 0,
1345 0, 0,
1346 0, 0,
1347 0, 0,
1348 GP_1_25_IN, GP_1_25_OUT,
1349 GP_1_24_IN, GP_1_24_OUT,
1350 GP_1_23_IN, GP_1_23_OUT,
1351 GP_1_22_IN, GP_1_22_OUT,
1352 GP_1_21_IN, GP_1_21_OUT,
1353 GP_1_20_IN, GP_1_20_OUT,
1354 GP_1_19_IN, GP_1_19_OUT,
1355 GP_1_18_IN, GP_1_18_OUT,
1356 GP_1_17_IN, GP_1_17_OUT,
1357 GP_1_16_IN, GP_1_16_OUT,
1358 GP_1_15_IN, GP_1_15_OUT,
1359 GP_1_14_IN, GP_1_14_OUT,
1360 GP_1_13_IN, GP_1_13_OUT,
1361 GP_1_12_IN, GP_1_12_OUT,
1362 GP_1_11_IN, GP_1_11_OUT,
1363 GP_1_10_IN, GP_1_10_OUT,
1364 GP_1_9_IN, GP_1_9_OUT,
1365 GP_1_8_IN, GP_1_8_OUT,
1366 GP_1_7_IN, GP_1_7_OUT,
1367 GP_1_6_IN, GP_1_6_OUT,
1368 GP_1_5_IN, GP_1_5_OUT,
1369 GP_1_4_IN, GP_1_4_OUT,
1370 GP_1_3_IN, GP_1_3_OUT,
1371 GP_1_2_IN, GP_1_2_OUT,
1372 GP_1_1_IN, GP_1_1_OUT,
1373 GP_1_0_IN, GP_1_0_OUT, }
1374 },
1375 { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
1376 { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
1377 { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
1378 { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
1379 0, 0,
1380 0, 0,
1381 0, 0,
1382 0, 0,
1383 GP_5_27_IN, GP_5_27_OUT,
1384 GP_5_26_IN, GP_5_26_OUT,
1385 GP_5_25_IN, GP_5_25_OUT,
1386 GP_5_24_IN, GP_5_24_OUT,
1387 GP_5_23_IN, GP_5_23_OUT,
1388 GP_5_22_IN, GP_5_22_OUT,
1389 GP_5_21_IN, GP_5_21_OUT,
1390 GP_5_20_IN, GP_5_20_OUT,
1391 GP_5_19_IN, GP_5_19_OUT,
1392 GP_5_18_IN, GP_5_18_OUT,
1393 GP_5_17_IN, GP_5_17_OUT,
1394 GP_5_16_IN, GP_5_16_OUT,
1395 GP_5_15_IN, GP_5_15_OUT,
1396 GP_5_14_IN, GP_5_14_OUT,
1397 GP_5_13_IN, GP_5_13_OUT,
1398 GP_5_12_IN, GP_5_12_OUT,
1399 GP_5_11_IN, GP_5_11_OUT,
1400 GP_5_10_IN, GP_5_10_OUT,
1401 GP_5_9_IN, GP_5_9_OUT,
1402 GP_5_8_IN, GP_5_8_OUT,
1403 GP_5_7_IN, GP_5_7_OUT,
1404 GP_5_6_IN, GP_5_6_OUT,
1405 GP_5_5_IN, GP_5_5_OUT,
1406 GP_5_4_IN, GP_5_4_OUT,
1407 GP_5_3_IN, GP_5_3_OUT,
1408 GP_5_2_IN, GP_5_2_OUT,
1409 GP_5_1_IN, GP_5_1_OUT,
1410 GP_5_0_IN, GP_5_0_OUT, }
1411 },
1412 { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
1413 0, 0,
1414 0, 0,
1415 0, 0,
1416 0, 0,
1417 0, 0,
1418 0, 0,
1419 GP_6_25_IN, GP_6_25_OUT,
1420 GP_6_24_IN, GP_6_24_OUT,
1421 GP_6_23_IN, GP_6_23_OUT,
1422 GP_6_22_IN, GP_6_22_OUT,
1423 GP_6_21_IN, GP_6_21_OUT,
1424 GP_6_20_IN, GP_6_20_OUT,
1425 GP_6_19_IN, GP_6_19_OUT,
1426 GP_6_18_IN, GP_6_18_OUT,
1427 GP_6_17_IN, GP_6_17_OUT,
1428 GP_6_16_IN, GP_6_16_OUT,
1429 GP_6_15_IN, GP_6_15_OUT,
1430 GP_6_14_IN, GP_6_14_OUT,
1431 GP_6_13_IN, GP_6_13_OUT,
1432 GP_6_12_IN, GP_6_12_OUT,
1433 GP_6_11_IN, GP_6_11_OUT,
1434 GP_6_10_IN, GP_6_10_OUT,
1435 GP_6_9_IN, GP_6_9_OUT,
1436 GP_6_8_IN, GP_6_8_OUT,
1437 GP_6_7_IN, GP_6_7_OUT,
1438 GP_6_6_IN, GP_6_6_OUT,
1439 GP_6_5_IN, GP_6_5_OUT,
1440 GP_6_4_IN, GP_6_4_OUT,
1441 GP_6_3_IN, GP_6_3_OUT,
1442 GP_6_2_IN, GP_6_2_OUT,
1443 GP_6_1_IN, GP_6_1_OUT,
1444 GP_6_0_IN, GP_6_0_OUT, }
1445 },
1446 { },
1447};
1448
1449static struct pinmux_data_reg pinmux_data_regs[] = {
1450 { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
1451 { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
1452 0, 0, 0, 0,
1453 0, 0, GP_1_25_DATA, GP_1_24_DATA,
1454 GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
1455 GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
1456 GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
1457 GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
1458 GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
1459 GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
1460 },
1461 { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
1462 { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
1463 { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
1464 { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
1465 0, 0, 0, 0,
1466 GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA,
1467 GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
1468 GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
1469 GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
1470 GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
1471 GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
1472 GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
1473 },
1474 { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
1475 0, 0, 0, 0,
1476 0, 0, GP_6_25_DATA, GP_6_24_DATA,
1477 GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA,
1478 GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA,
1479 GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
1480 GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
1481 GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
1482 GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
1483 },
1484 { },
1485};
1486
1487static struct pinmux_info r8a7794_pinmux_info = {
1488 .name = "r8a7794_pfc",
1489
1490 .unlock_reg = 0xe6060000, /* PMMR */
1491
1492 .reserved_id = PINMUX_RESERVED,
1493 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1494 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1495 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1496 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1497 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1498
1499 .first_gpio = GPIO_GP_0_0,
1500 .last_gpio = GPIO_FN_AD_CLK_B,
1501
1502 .gpios = pinmux_gpios,
1503 .cfg_regs = pinmux_config_regs,
1504 .data_regs = pinmux_data_regs,
1505
1506 .gpio_data = pinmux_data,
1507 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1508};
1509
1510void r8a7794_pinmux_init(void)
1511{
1512 register_pinmux(&r8a7794_pinmux_info);
1513}