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Lokesh Vutla687054a2013-02-12 21:29:08 +00001/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
Lokesh Vutla687054a2013-02-12 21:29:08 +000012 */
13#include <common.h>
Nishanth Menoncb199102013-03-26 05:20:54 +000014#include <palmas.h>
Dan Murphye9024ef2014-02-03 06:59:02 -060015#include <sata.h>
Lokesh Vutla687054a2013-02-12 21:29:08 +000016#include <asm/arch/sys_proto.h>
17#include <asm/arch/mmc_host_def.h>
Roger Quadros21914ee2013-11-11 16:56:44 +020018#include <asm/arch/sata.h>
Tom Rini79b079f2014-04-03 07:52:56 -040019#include <environment.h>
Lokesh Vutla687054a2013-02-12 21:29:08 +000020
21#include "mux_data.h"
22
Mugunthan V Nb1e26e32013-07-08 16:04:41 +053023#ifdef CONFIG_DRIVER_TI_CPSW
24#include <cpsw.h>
25#endif
26
Lokesh Vutla687054a2013-02-12 21:29:08 +000027DECLARE_GLOBAL_DATA_PTR;
28
29const struct omap_sysinfo sysinfo = {
30 "Board: DRA7xx\n"
31};
32
Mugunthan V Nb1e26e32013-07-08 16:04:41 +053033/*
34 * Adjust I/O delays on the Tx control and data lines of each MAC port. This
35 * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
36 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
37 * essentially need to counteract the DRA7xx internal delay, and we do this
38 * by delaying the control and data lines. If not using this PHY, you probably
39 * don't need to do this stuff!
40 */
41static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
42{
43 int i = 0;
44 u32 reg_val;
45 u32 delta;
46 u32 coarse;
47 u32 fine;
48
49 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
50
51 while(io_dly[i].addr) {
52 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
53 io_dly[i].addr);
54 delta = io_dly[i].dly;
55 reg_val = readl(io_dly[i].addr) & 0x3ff;
56 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
57 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
58 fine = (reg_val & 0x1F) + (delta & 0x1F);
59 fine = (fine > 0x1F) ? (0x1F) : (fine);
60 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
61 CFG_IO_DELAY_LOCK_MASK |
62 ((coarse << 5) | (fine));
63 writel(reg_val, io_dly[i].addr);
64 i++;
65 }
66
67 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
68}
69
Lokesh Vutla687054a2013-02-12 21:29:08 +000070/**
71 * @brief board_init
72 *
73 * @return 0
74 */
75int board_init(void)
76{
77 gpmc_init();
78 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
79
80 return 0;
81}
82
Roger Quadros21914ee2013-11-11 16:56:44 +020083int board_late_init(void)
84{
Lokesh Vutla4ec3f6e2014-07-14 19:57:58 +053085#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
86 if (omap_revision() == DRA722_ES1_0)
87 setenv("board_name", "dra72x");
88 else
89 setenv("board_name", "dra7xx");
90#endif
Dan Murphye9024ef2014-02-03 06:59:02 -060091 init_sata(0);
Roger Quadros21914ee2013-11-11 16:56:44 +020092 return 0;
93}
94
Lokesh Vutla687054a2013-02-12 21:29:08 +000095/**
96 * @brief misc_init_r - Configure EVM board specific configurations
97 * such as power configurations, ethernet initialization as phase2 of
98 * boot sequence
99 *
100 * @return 0
101 */
102int misc_init_r(void)
103{
104 return 0;
105}
106
107static void do_set_mux32(u32 base,
108 struct pad_conf_entry const *array, int size)
109{
110 int i;
111 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
112
113 for (i = 0; i < size; i++, pad++)
114 writel(pad->val, base + pad->offset);
115}
116
117void set_muxconf_regs_essential(void)
118{
119 do_set_mux32((*ctrl)->control_padconf_core_base,
120 core_padconf_array_essential,
121 sizeof(core_padconf_array_essential) /
122 sizeof(struct pad_conf_entry));
123}
124
125#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
126int board_mmc_init(bd_t *bis)
127{
128 omap_mmc_init(0, 0, 0, -1, -1);
129 omap_mmc_init(1, 0, 0, -1, -1);
130 return 0;
131}
132#endif
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530133
Tom Rini79b079f2014-04-03 07:52:56 -0400134#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
135int spl_start_uboot(void)
136{
137 /* break into full u-boot on 'c' */
138 if (serial_tstc() && serial_getc() == 'c')
139 return 1;
140
141#ifdef CONFIG_SPL_ENV_SUPPORT
142 env_init();
143 env_relocate_spec();
144 if (getenv_yesno("boot_os") != 1)
145 return 1;
146#endif
147
148 return 0;
149}
150#endif
151
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530152#ifdef CONFIG_DRIVER_TI_CPSW
153
154/* Delay value to add to calibrated value */
155#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
156#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
157#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
158#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
159#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
160#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
161#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
162#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
163#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
164#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
165
Mugunthan V N4c8014b2014-05-22 14:37:12 +0530166extern u32 *const omap_si_rev;
167
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530168static void cpsw_control(int enabled)
169{
170 /* VTP can be added here */
171
172 return;
173}
174
175static struct cpsw_slave_data cpsw_slaves[] = {
176 {
177 .slave_reg_ofs = 0x208,
178 .sliver_reg_ofs = 0xd80,
Mugunthan V N9c653aa2014-02-18 07:31:52 -0500179 .phy_addr = 2,
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530180 },
181 {
182 .slave_reg_ofs = 0x308,
183 .sliver_reg_ofs = 0xdc0,
Mugunthan V N9c653aa2014-02-18 07:31:52 -0500184 .phy_addr = 3,
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530185 },
186};
187
188static struct cpsw_platform_data cpsw_data = {
189 .mdio_base = CPSW_MDIO_BASE,
190 .cpsw_base = CPSW_BASE,
191 .mdio_div = 0xff,
192 .channels = 8,
193 .cpdma_reg_ofs = 0x800,
Mugunthan V N4c8014b2014-05-22 14:37:12 +0530194 .slaves = 2,
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530195 .slave_data = cpsw_slaves,
196 .ale_reg_ofs = 0xd00,
197 .ale_entries = 1024,
198 .host_port_reg_ofs = 0x108,
199 .hw_stats_reg_ofs = 0x900,
200 .bd_ram_ofs = 0x2000,
201 .mac_control = (1 << 5),
202 .control = cpsw_control,
203 .host_port_num = 0,
204 .version = CPSW_CTRL_VERSION_2,
205};
206
207int board_eth_init(bd_t *bis)
208{
209 int ret;
210 uint8_t mac_addr[6];
211 uint32_t mac_hi, mac_lo;
212 uint32_t ctrl_val;
213 const struct io_delay io_dly[] = {
214 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
215 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
216 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
217 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
218 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
219 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
220 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
221 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
222 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
223 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
224 {0}
225 };
226
227 /* Adjust IO delay for RGMII tx path */
228 dra7xx_adj_io_delay(io_dly);
229
230 /* try reading mac address from efuse */
231 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
232 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
Mugunthan V Ne0a1d592014-01-07 19:57:38 +0530233 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530234 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
Mugunthan V Ne0a1d592014-01-07 19:57:38 +0530235 mac_addr[2] = mac_hi & 0xFF;
236 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530237 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
Mugunthan V Ne0a1d592014-01-07 19:57:38 +0530238 mac_addr[5] = mac_lo & 0xFF;
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530239
240 if (!getenv("ethaddr")) {
241 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
242
243 if (is_valid_ether_addr(mac_addr))
244 eth_setenv_enetaddr("ethaddr", mac_addr);
245 }
Mugunthan V N8feb37b2014-02-18 07:31:56 -0500246
247 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
248 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
249 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
250 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
251 mac_addr[2] = mac_hi & 0xFF;
252 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
253 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
254 mac_addr[5] = mac_lo & 0xFF;
255
256 if (!getenv("eth1addr")) {
257 if (is_valid_ether_addr(mac_addr))
258 eth_setenv_enetaddr("eth1addr", mac_addr);
259 }
260
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530261 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
262 ctrl_val |= 0x22;
263 writel(ctrl_val, (*ctrl)->control_core_control_io1);
264
Mugunthan V N4c8014b2014-05-22 14:37:12 +0530265 if (*omap_si_rev == DRA722_ES1_0)
266 cpsw_data.active_slave = 1;
267
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530268 ret = cpsw_register(&cpsw_data);
269 if (ret < 0)
270 printf("Error %d registering CPSW switch\n", ret);
271
272 return ret;
273}
274#endif