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wdenkfe8c2802002-11-03 00:38:21 +00001/*------------------------------------------------------------------------------+ */
2/* */
3/* This source code has been made available to you by IBM on an AS-IS */
4/* basis. Anyone receiving this source is licensed under IBM */
5/* copyrights to use it in any way he or she deems fit, including */
6/* copying it, modifying it, compiling it, and redistributing it either */
7/* with or without modifications. No license under IBM patents or */
8/* patent applications is to be implied by the copyright license. */
9/* */
10/* Any user of this software should understand that IBM cannot provide */
11/* technical support for this software and will not be responsible for */
12/* any consequences resulting from the use of this software. */
13/* */
14/* Any person who transfers this source code or any derivative work */
15/* must include the IBM copyright notice, this paragraph, and the */
16/* preceding two paragraphs in the transferred software. */
17/* */
18/* COPYRIGHT I B M CORPORATION 1995 */
19/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
20/*------------------------------------------------------------------------------- */
21
22/*----------------------------------------------------------------------------- */
23/* Function: ext_bus_cntlr_init */
24/* Description: Initializes the External Bus Controller for the external */
25/* peripherals. IMPORTANT: For pass1 this code must run from */
26/* cache since you can not reliably change a peripheral banks */
27/* timing register (pbxap) while running code from that bank. */
28/* For ex., since we are running from ROM on bank 0, we can NOT */
29/* execute the code that modifies bank 0 timings from ROM, so */
30/* we run it from cache. */
31/* Bank 0 - Flash and SRAM */
32/* Bank 1 - NVRAM/RTC */
33/* Bank 2 - Keyboard/Mouse controller */
34/* Bank 3 - IR controller */
35/* Bank 4 - not used */
36/* Bank 5 - not used */
37/* Bank 6 - not used */
38/* Bank 7 - FPGA registers */
39/*-----------------------------------------------------------------------------#include <config.h> */
40#include <ppc4xx.h>
41
42#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
43
44#include <ppc_asm.tmpl>
45#include <ppc_defs.h>
46
47#include <asm/cache.h>
48#include <asm/mmu.h>
49
50/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
51/* except for #1 which we use for DMA'ing to IOCA-like things, so the */
52/* control registers to set that up are determined by what we've */
53/* empirically discovered work there. */
54
55 .globl ext_bus_cntlr_init
56ext_bus_cntlr_init:
57 mflr r4 /* save link register */
58 bl ..getAddr
59..getAddr:
60 mflr r3 /* get address of ..getAddr */
61 mtlr r4 /* restore link register */
62 addi r4,0,14 /* set ctr to 10; used to prefetch */
63 mtctr r4 /* 10 cache lines to fit this function */
64 /* in cache (gives us 8x10=80 instrctns) */
65..ebcloop:
66 icbt r0,r3 /* prefetch cache line for addr in r3 */
67 addi r3,r3,32 /* move to next cache line */
68 bdnz ..ebcloop /* continue for 10 cache lines */
69
70 /*------------------------------------------------------------------- */
71 /* Delay to ensure all accesses to ROM are complete before changing */
72 /* bank 0 timings. 200usec should be enough. */
73 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
74 /*------------------------------------------------------------------- */
75 addis r3,0,0x0
76 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
77 mtctr r3
78..spinlp:
79 bdnz ..spinlp /* spin loop */
80
81
82 /*---------------------------------------------------------------------- */
83 /* Peripheral Bank 0 (Flash) initialization */
84 /*---------------------------------------------------------------------- */
85 /* 0x7F8FFE80 slowest boot */
86 addi r4,0,pb0ap
87 mtdcr ebccfga,r4
88 addis r4,0,0x9B01
89 ori r4,r4,0x5480
90 mtdcr ebccfgd,r4
91
92 addi r4,0,pb0cr
93 mtdcr ebccfga,r4
94 addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
95 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
96 mtdcr ebccfgd,r4
97
98 blr
99
100 /*---------------------------------------------------------------------- */
101 /* Peripheral Bank 1 (NVRAM/RTC) initialization */
102 /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
103 /* and we do DMA on it. The ConfigurationRegister part is threfore */
104 /* almost arbitrary, except that our linux driver needs to know the */
105 /* address, but it can query, it.. */
106 /* */
107 /* The AccessParameter is CRITICAL, */
108 /* thouch, since it needs to agree with the electrical timings on the */
109 /* IOCA parallel interface. That value is: 0x0185,4380 */
110 /* BurstModeEnable BME=0 */
111 /* TransferWait TWT=3 */
112 /* ChipSelectOnTiming CSN=1 */
113 /* OutputEnableOnTimimg OEN=1 */
114 /* WriteByteEnableOnTiming WBN=1 */
115 /* WriteByteEnableOffTiming WBF=0 */
116 /* TransferHold TH=1 */
117 /* ReadyEnable RE=1 */
118 /* SampleOnReady SOR=1 */
119 /* ByteEnableMode BEM=0 */
120 /* ParityEnable PEN=0 */
121 /* all reserved bits=0 */
122 /*---------------------------------------------------------------------- */
123 /*---------------------------------------------------------------------- */
124 addi r4,0,pb1ap
125 mtdcr ebccfga,r4
126 addis r4,0,0x0185 /* hiword */
127 ori r4,r4,0x4380 /* loword */
128 mtdcr ebccfgd,r4
129
130 addi r4,0,pb1cr
131 mtdcr ebccfga,r4
132 addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
133 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
134 mtdcr ebccfgd,r4
135
136 blr
137
138/*----------------------------------------------------------------------------- */
139/* Function: sdram_init */
140/* Description: Configures SDRAM memory banks. */
141/* NOTE: for CrayL1 we have ECC memory, so enable it. */
142/*....now done in C in L1.c:init_sdram for readability. */
143/*----------------------------------------------------------------------------- */
144 .globl sdram_init
145
146sdram_init:
147 blr