blob: 0fb117f9d3651a59af64c74366cfa94502566625 [file] [log] [blame]
Stefan Roesea4884832014-10-22 12:13:19 +02001/*
2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _CONFIG_DB_MV7846MP_GP_H
8#define _CONFIG_DB_MV7846MP_GP_H
9
10/*
11 * High Level Configuration Options (easy to change)
12 */
13#define CONFIG_ARMADA_XP /* SOC Family Name */
14#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
15#define CONFIG_SYS_GENERIC_BOARD
16#define CONFIG_DISPLAY_BOARDINFO_LATE
17
18#define CONFIG_SYS_TEXT_BASE 0x04000000
19#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
20
21/*
22 * Commands configuration
23 */
24#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
Stefan Roesea4884832014-10-22 12:13:19 +020025#define CONFIG_CMD_DHCP
26#define CONFIG_CMD_ENV
27#define CONFIG_CMD_I2C
28#define CONFIG_CMD_PING
29#define CONFIG_CMD_SF
30#define CONFIG_CMD_SPI
31#define CONFIG_CMD_TFTPPUT
32#define CONFIG_CMD_TIME
33
34/* I2C */
35#define CONFIG_SYS_I2C
36#define CONFIG_SYS_I2C_MVTWSI
Paul Kocialkowskidd822422015-04-10 23:09:51 +020037#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roesea4884832014-10-22 12:13:19 +020038#define CONFIG_SYS_I2C_SLAVE 0x0
39#define CONFIG_SYS_I2C_SPEED 100000
40
41/* SPI NOR flash default params, used by sf commands */
42#define CONFIG_SF_DEFAULT_SPEED 1000000
43#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
44#define CONFIG_SPI_FLASH_STMICRO
Stefan Roese68102b82015-01-19 11:33:39 +010045#define CONFIG_SPI_FLASH_SPANSION
Stefan Roesea4884832014-10-22 12:13:19 +020046
47/* Environment in SPI NOR flash */
48#define CONFIG_ENV_IS_IN_SPI_FLASH
49#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
50#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
51#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
52
53#define CONFIG_PHY_MARVELL /* there is a marvell phy */
Stefan Roesecae90082015-04-25 06:29:52 +020054#define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 }
Stefan Roesea4884832014-10-22 12:13:19 +020055#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
56#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
57#define CONFIG_RESET_PHY_R
58
59#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
60#define CONFIG_SYS_ALT_MEMTEST
61
62/*
63 * mv-common.h should be defined after CMD configs since it used them
64 * to enable certain macros
65 */
66#include "mv-common.h"
67
Stefan Roesee7778ec2015-01-19 11:33:47 +010068/*
69 * Memory layout while starting into the bin_hdr via the
70 * BootROM:
71 *
72 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
73 * 0x4000.4030 bin_hdr start address
74 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
75 * 0x4007.fffc BootROM stack top
76 *
77 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
78 * L2 cache thus cannot be used.
79 */
80
81/* SPL */
82/* Defines for SPL */
83#define CONFIG_SPL_FRAMEWORK
84#define CONFIG_SPL_TEXT_BASE 0x40004030
85#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
86
87#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
88#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
89
90#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
91 CONFIG_SPL_BSS_MAX_SIZE)
92#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
93
94#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
95#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
96
97#define CONFIG_SPL_LIBCOMMON_SUPPORT
98#define CONFIG_SPL_LIBGENERIC_SUPPORT
99#define CONFIG_SPL_SERIAL_SUPPORT
100#define CONFIG_SPL_I2C_SUPPORT
Stefan Roesee7778ec2015-01-19 11:33:47 +0100101
102/* SPL related SPI defines */
103#define CONFIG_SPL_SPI_SUPPORT
104#define CONFIG_SPL_SPI_FLASH_SUPPORT
105#define CONFIG_SPL_SPI_LOAD
106#define CONFIG_SPL_SPI_BUS 0
107#define CONFIG_SPL_SPI_CS 0
108#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
109
110/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Stefan Roeseff9112d2015-03-25 12:51:18 +0100111#define CONFIG_SYS_MVEBU_DDR_AXP
Stefan Roesee7778ec2015-01-19 11:33:47 +0100112#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
113
Stefan Roesea4884832014-10-22 12:13:19 +0200114#endif /* _CONFIG_DB_MV7846MP_GP_H */