blob: 194f6ab961f9d68db5acfa97885d7037065edc88 [file] [log] [blame]
Joe Hamman11c45eb2007-12-13 06:45:08 -06001/*
Paul Gortmakerbd42bbb2009-09-18 19:08:46 -04002 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
3 *
Joe Hamman11c45eb2007-12-13 06:45:08 -06004 * Copyright 2007 Embedded Specialties, Inc.
5 *
6 * Copyright 2004, 2007 Freescale Semiconductor.
7 *
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <pci.h>
31#include <asm/processor.h>
32#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050033#include <asm/fsl_pci.h>
Kumar Gala33b90792008-08-26 23:15:28 -050034#include <asm/fsl_ddr_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060035#include <spd_sdram.h>
Paul Gortmaker94ca0912009-09-18 19:08:44 -040036#include <netdev.h>
37#include <tsec.h>
Joe Hamman11c45eb2007-12-13 06:45:08 -060038#include <miiphy.h>
39#include <libfdt.h>
40#include <fdt_support.h>
41
Joe Hamman11c45eb2007-12-13 06:45:08 -060042DECLARE_GLOBAL_DATA_PTR;
43
Joe Hamman11c45eb2007-12-13 06:45:08 -060044void local_bus_init(void);
45void sdram_init(void);
46long int fixed_sdram (void);
47
48int board_early_init_f (void)
49{
50 return 0;
51}
52
53int checkboard (void)
54{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
56 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
Joe Hamman11c45eb2007-12-13 06:45:08 -060057
58 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040059 in_8(rev) >> 4);
Joe Hamman11c45eb2007-12-13 06:45:08 -060060
61 /*
62 * Initialize local bus.
63 */
64 local_bus_init ();
65
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040066 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
67 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
Joe Hamman11c45eb2007-12-13 06:45:08 -060068 return 0;
69}
70
Becky Bruce9973e3c2008-06-09 16:03:40 -050071phys_size_t
Joe Hamman11c45eb2007-12-13 06:45:08 -060072initdram(int board_type)
73{
74 long dram_size = 0;
75
76 puts("Initializing\n");
77
78#if defined(CONFIG_DDR_DLL)
79 {
80 /*
81 * Work around to stabilize DDR DLL MSYNC_IN.
82 * Errata DDR9 seems to have been fixed.
83 * This is now the workaround for Errata DDR11:
84 * Override DLL = 1, Course Adj = 1, Tap Select = 0
85 */
86
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Joe Hamman11c45eb2007-12-13 06:45:08 -060088
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040089 out_be32(&gur->ddrdllcr, 0x81000000);
Joe Hamman11c45eb2007-12-13 06:45:08 -060090 asm("sync;isync;msync");
91 udelay(200);
92 }
93#endif
94
95#if defined(CONFIG_SPD_EEPROM)
Kumar Gala33b90792008-08-26 23:15:28 -050096 dram_size = fsl_ddr_sdram();
97 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
98 dram_size *= 0x100000;
Joe Hamman11c45eb2007-12-13 06:45:08 -060099#else
100 dram_size = fixed_sdram ();
101#endif
102
Joe Hamman11c45eb2007-12-13 06:45:08 -0600103 /*
104 * SDRAM Initialization
105 */
106 sdram_init();
107
108 puts(" DDR: ");
109 return dram_size;
110}
111
112/*
113 * Initialize Local Bus
114 */
115void
116local_bus_init(void)
117{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
119 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600120
121 uint clkdiv;
122 uint lbc_hz;
123 sys_info_t sysinfo;
124
125 get_sys_info(&sysinfo);
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400126 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600127 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
128
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400129 out_be32(&gur->lbiuiplldcr1, 0x00078080);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600130 if (clkdiv == 16) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400131 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600132 } else if (clkdiv == 8) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400133 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600134 } else if (clkdiv == 4) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400135 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600136 }
137
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400138 setbits_be32(&lbc->lcrr, 0x00030000);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600139
140 asm("sync;isync;msync");
141
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400142 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
143 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600144}
145
146/*
147 * Initialize SDRAM memory on the Local Bus.
148 */
149void
150sdram_init(void)
151{
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400152#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600153
154 uint idx;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
156 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600157 uint lsdmr_common;
158
159 puts(" SDRAM: ");
160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600162
163 /*
164 * Setup SDRAM Base and Option Registers
165 */
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400166 out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600167 asm("msync");
168
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400169 out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600170 asm("msync");
171
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400172 out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
173 asm("msync");
174
175 out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
176 asm("msync");
177
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400178 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600179 asm("msync");
180
181
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400182 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
183 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600184 asm("msync");
185
186 /*
187 * MPC8548 uses "new" 15-16 style addressing.
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500190 lsdmr_common |= LSDMR_BSMA1516;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600191
192 /*
193 * Issue PRECHARGE ALL command.
194 */
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400195 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600196 asm("sync;msync");
197 *sdram_addr = 0xff;
198 ppcDcbf((unsigned long) sdram_addr);
199 udelay(100);
200
201 /*
202 * Issue 8 AUTO REFRESH commands.
203 */
204 for (idx = 0; idx < 8; idx++) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400205 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600206 asm("sync;msync");
207 *sdram_addr = 0xff;
208 ppcDcbf((unsigned long) sdram_addr);
209 udelay(100);
210 }
211
212 /*
213 * Issue 8 MODE-set command.
214 */
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400215 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600216 asm("sync;msync");
217 *sdram_addr = 0xff;
218 ppcDcbf((unsigned long) sdram_addr);
219 udelay(100);
220
221 /*
222 * Issue NORMAL OP command.
223 */
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400224 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600225 asm("sync;msync");
226 *sdram_addr = 0xff;
227 ppcDcbf((unsigned long) sdram_addr);
228 udelay(200); /* Overkill. Must wait > 200 bus cycles */
229
230#endif /* enable SDRAM init */
231}
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#if defined(CONFIG_SYS_DRAM_TEST)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600234int
235testdram(void)
236{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
238 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600239 uint *p;
240
241 printf("Testing DRAM from 0x%08x to 0x%08x\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 CONFIG_SYS_MEMTEST_START,
243 CONFIG_SYS_MEMTEST_END);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600244
245 printf("DRAM test phase 1:\n");
246 for (p = pstart; p < pend; p++)
247 *p = 0xaaaaaaaa;
248
249 for (p = pstart; p < pend; p++) {
250 if (*p != 0xaaaaaaaa) {
251 printf ("DRAM test fails at: %08x\n", (uint) p);
252 return 1;
253 }
254 }
255
256 printf("DRAM test phase 2:\n");
257 for (p = pstart; p < pend; p++)
258 *p = 0x55555555;
259
260 for (p = pstart; p < pend; p++) {
261 if (*p != 0x55555555) {
262 printf ("DRAM test fails at: %08x\n", (uint) p);
263 return 1;
264 }
265 }
266
267 printf("DRAM test passed.\n");
268 return 0;
269}
270#endif
271
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400272#if !defined(CONFIG_SPD_EEPROM)
273#define CONFIG_SYS_DDR_CONTROL 0xc300c000
Joe Hamman11c45eb2007-12-13 06:45:08 -0600274/*************************************************************************
275 * fixed_sdram init -- doesn't use serial presence detect.
276 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
277 ************************************************************************/
278long int fixed_sdram (void)
279{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600281
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400282 out_be32(&ddr->cs0_bnds, 0x0000007f);
283 out_be32(&ddr->cs1_bnds, 0x008000ff);
284 out_be32(&ddr->cs2_bnds, 0x00000000);
285 out_be32(&ddr->cs3_bnds, 0x00000000);
286 out_be32(&ddr->cs0_config, 0x80010101);
287 out_be32(&ddr->cs1_config, 0x80010101);
288 out_be32(&ddr->cs2_config, 0x00000000);
289 out_be32(&ddr->cs3_config, 0x00000000);
290 out_be32(&ddr->timing_cfg_3, 0x00000000);
291 out_be32(&ddr->timing_cfg_0, 0x00220802);
292 out_be32(&ddr->timing_cfg_1, 0x38377322);
293 out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
294 out_be32(&ddr->sdram_cfg, 0x4300C000);
295 out_be32(&ddr->sdram_cfg_2, 0x24401000);
296 out_be32(&ddr->sdram_mode, 0x23C00542);
297 out_be32(&ddr->sdram_mode_2, 0x00000000);
298 out_be32(&ddr->sdram_interval, 0x05080100);
299 out_be32(&ddr->sdram_md_cntl, 0x00000000);
300 out_be32(&ddr->sdram_data_init, 0x00000000);
301 out_be32(&ddr->sdram_clk_cntl, 0x03800000);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600302 asm("sync;isync;msync");
303 udelay(500);
304
305 #if defined (CONFIG_DDR_ECC)
306 /* Enable ECC checking */
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400307 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600308 #else
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400309 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600310 #endif
311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600313}
314#endif
315
Paul Gortmaker7b1f1392009-09-18 19:08:39 -0400316#ifdef CONFIG_PCI1
317static struct pci_controller pci1_hose;
318#endif /* CONFIG_PCI1 */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600319
320#ifdef CONFIG_PCIE1
321static struct pci_controller pcie1_hose;
322#endif /* CONFIG_PCIE1 */
323
Joe Hamman11c45eb2007-12-13 06:45:08 -0600324
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400325#ifdef CONFIG_PCI
Joe Hamman11c45eb2007-12-13 06:45:08 -0600326void
327pci_init_board(void)
328{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400330 struct fsl_pci_info pci_info[2];
331 u32 devdisr, pordevsr, porpllsr, io_sel;
332 int first_free_busno = 0;
333 int num = 0;
334
335#ifdef CONFIG_PCIE1
336 int pcie_configured;
337#endif
338
339 devdisr = in_be32(&gur->devdisr);
340 pordevsr = in_be32(&gur->pordevsr);
341 porpllsr = in_be32(&gur->porpllsr);
342 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
343
344 debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600345
346#ifdef CONFIG_PCI1
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400347 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
348 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
349 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
350 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
351 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600352
Paul Gortmaker7b1f1392009-09-18 19:08:39 -0400353 printf (" PCI host: %d bit, %s MHz, %s, %s\n",
Joe Hamman11c45eb2007-12-13 06:45:08 -0600354 (pci_32) ? 32 : 64,
Paul Gortmaker2c40acd2009-09-18 19:08:40 -0400355 (pci_speed == 33000000) ? "33" :
356 (pci_speed == 66000000) ? "66" : "unknown",
Joe Hamman11c45eb2007-12-13 06:45:08 -0600357 pci_clk_sel ? "sync" : "async",
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400358 pci_arb ? "arbiter" : "external-arbiter");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600359
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400360 SET_STD_PCI_INFO(pci_info[num], 1);
361 first_free_busno = fsl_pci_init_port(&pci_info[num++],
362 &pci1_hose, first_free_busno);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600363 } else {
364 printf (" PCI: disabled\n");
365 }
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400366
367 puts("\n");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600368#else
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400369 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600370#endif
371
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400372 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600373
374#ifdef CONFIG_PCIE1
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400375 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600376
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400377 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
378 SET_STD_PCIE_INFO(pci_info[num], 1);
379 printf (" PCIE at base address %lx\n", pci_info[num].regs);
380 first_free_busno = fsl_pci_init_port(&pci_info[num++],
381 &pcie1_hose, first_free_busno);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600382 } else {
383 printf (" PCIE: disabled\n");
384 }
Joe Hamman11c45eb2007-12-13 06:45:08 -0600385
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400386 puts("\n");
387#else
388 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
389#endif
Joe Hamman11c45eb2007-12-13 06:45:08 -0600390}
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400391#endif
Joe Hamman11c45eb2007-12-13 06:45:08 -0600392
Paul Gortmaker94ca0912009-09-18 19:08:44 -0400393int board_eth_init(bd_t *bis)
394{
395 tsec_standard_init(bis);
396 pci_eth_init(bis);
397 return 0; /* otherwise cpu_eth_init gets run */
398}
399
Joe Hamman11c45eb2007-12-13 06:45:08 -0600400int last_stage_init(void)
401{
402 return 0;
403}
404
405#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500406void ft_board_setup(void *blob, bd_t *bd)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600407{
408 ft_cpu_setup(blob, bd);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500409#ifdef CONFIG_PCI1
410 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
411#endif
412#ifdef CONFIG_PCIE1
413 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600414#endif
415}
416#endif