blob: 3efd3e841f4e8f1c7696664ac7efc33dad54a839 [file] [log] [blame]
Simon Glass2b605152014-11-12 22:42:15 -07001/*
2 * From coreboot southbridge/intel/bd82x6x/lpc.c
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#include <common.h>
Simon Glassaad78d22015-03-05 12:25:33 -070010#include <dm.h>
Simon Glass2b605152014-11-12 22:42:15 -070011#include <errno.h>
12#include <fdtdec.h>
Simon Glass72cd0852014-11-14 18:18:35 -070013#include <rtc.h>
Simon Glass2b605152014-11-12 22:42:15 -070014#include <pci.h>
Simon Glass72cd0852014-11-14 18:18:35 -070015#include <asm/acpi.h>
16#include <asm/interrupt.h>
17#include <asm/io.h>
18#include <asm/ioapic.h>
Simon Glass2b605152014-11-12 22:42:15 -070019#include <asm/pci.h>
20#include <asm/arch/pch.h>
21
Simon Glass72cd0852014-11-14 18:18:35 -070022#define NMI_OFF 0
23
24#define ENABLE_ACPI_MODE_IN_COREBOOT 0
25#define TEST_SMM_FLASH_LOCKDOWN 0
26
27static int pch_enable_apic(pci_dev_t dev)
28{
29 u32 reg32;
30 int i;
31
32 /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
Simon Glass31f57c22015-03-05 12:25:15 -070033 x86_pci_write_config8(dev, ACPI_CNTL, 0x80);
Simon Glass72cd0852014-11-14 18:18:35 -070034
35 writel(0, IO_APIC_INDEX);
36 writel(1 << 25, IO_APIC_DATA);
37
38 /* affirm full set of redirection table entries ("write once") */
39 writel(1, IO_APIC_INDEX);
40 reg32 = readl(IO_APIC_DATA);
41 writel(1, IO_APIC_INDEX);
42 writel(reg32, IO_APIC_DATA);
43
44 writel(0, IO_APIC_INDEX);
45 reg32 = readl(IO_APIC_DATA);
46 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
47 if (reg32 != (1 << 25)) {
48 printf("APIC Error - cannot write to registers\n");
49 return -EPERM;
50 }
51
52 debug("Dumping IOAPIC registers\n");
53 for (i = 0; i < 3; i++) {
54 writel(i, IO_APIC_INDEX);
55 debug(" reg 0x%04x:", i);
56 reg32 = readl(IO_APIC_DATA);
57 debug(" 0x%08x\n", reg32);
58 }
59
60 /* Select Boot Configuration register. */
61 writel(3, IO_APIC_INDEX);
62
63 /* Use Processor System Bus to deliver interrupts. */
64 writel(1, IO_APIC_DATA);
65
66 return 0;
67}
68
69static void pch_enable_serial_irqs(pci_dev_t dev)
70{
71 u32 value;
72
73 /* Set packet length and toggle silent mode bit for one frame. */
74 value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
75#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
Simon Glass31f57c22015-03-05 12:25:15 -070076 x86_pci_write_config8(dev, SERIRQ_CNTL, value);
Simon Glass72cd0852014-11-14 18:18:35 -070077#else
Simon Glass31f57c22015-03-05 12:25:15 -070078 x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
Simon Glass72cd0852014-11-14 18:18:35 -070079#endif
80}
81
82static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
83{
84 uint8_t route[8], *ptr;
85
86 if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
87 sizeof(route)))
88 return -EINVAL;
89 ptr = route;
Simon Glass31f57c22015-03-05 12:25:15 -070090 x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++);
91 x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++);
92 x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++);
93 x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++);
Simon Glass72cd0852014-11-14 18:18:35 -070094
Simon Glass31f57c22015-03-05 12:25:15 -070095 x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++);
96 x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++);
97 x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++);
98 x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++);
Simon Glass72cd0852014-11-14 18:18:35 -070099
100 /*
101 * TODO(sjg@chromium.org): U-Boot does not set up the interrupts
102 * here. It's unclear if it is needed
103 */
104 return 0;
105}
106
107static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
108{
109 u8 route[16];
110 u32 reg;
111 int gpi;
112
113 if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
114 sizeof(route)))
115 return -EINVAL;
116
117 for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
118 reg |= route[gpi] << (gpi * 2);
119
Simon Glass31f57c22015-03-05 12:25:15 -0700120 x86_pci_write_config32(dev, 0xb8, reg);
Simon Glass72cd0852014-11-14 18:18:35 -0700121
122 return 0;
123}
124
125static int pch_power_options(const void *blob, int node, pci_dev_t dev)
126{
127 u8 reg8;
128 u16 reg16, pmbase;
129 u32 reg32;
130 const char *state;
131 int pwr_on;
132 int nmi_option;
133 int ret;
134
135 /*
136 * Which state do we want to goto after g3 (power restored)?
137 * 0 == S0 Full On
138 * 1 == S5 Soft Off
139 *
140 * If the option is not existent (Laptops), use Kconfig setting.
141 * TODO(sjg@chromium.org): Make this configurable
142 */
143 pwr_on = MAINBOARD_POWER_ON;
144
Simon Glass31f57c22015-03-05 12:25:15 -0700145 reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
Simon Glass72cd0852014-11-14 18:18:35 -0700146 reg16 &= 0xfffe;
147 switch (pwr_on) {
148 case MAINBOARD_POWER_OFF:
149 reg16 |= 1;
150 state = "off";
151 break;
152 case MAINBOARD_POWER_ON:
153 reg16 &= ~1;
154 state = "on";
155 break;
156 case MAINBOARD_POWER_KEEP:
157 reg16 &= ~1;
158 state = "state keep";
159 break;
160 default:
161 state = "undefined";
162 }
163
164 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
165 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
166
167 reg16 &= ~(1 << 10);
168 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
169
170 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
171
Simon Glass31f57c22015-03-05 12:25:15 -0700172 x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
Simon Glass72cd0852014-11-14 18:18:35 -0700173 debug("Set power %s after power failure.\n", state);
174
175 /* Set up NMI on errors. */
176 reg8 = inb(0x61);
177 reg8 &= 0x0f; /* Higher Nibble must be 0 */
178 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
179 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
180 outb(reg8, 0x61);
181
182 reg8 = inb(0x70);
183 /* TODO(sjg@chromium.org): Make this configurable */
184 nmi_option = NMI_OFF;
185 if (nmi_option) {
186 debug("NMI sources enabled.\n");
187 reg8 &= ~(1 << 7); /* Set NMI. */
188 } else {
189 debug("NMI sources disabled.\n");
190 /* Can't mask NMI from PCI-E and NMI_NOW */
191 reg8 |= (1 << 7);
192 }
193 outb(reg8, 0x70);
194
195 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
Simon Glass31f57c22015-03-05 12:25:15 -0700196 reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
Simon Glass72cd0852014-11-14 18:18:35 -0700197 reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
198 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
199#if DEBUG_PERIODIC_SMIS
200 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
201 reg16 |= (3 << 0); /* Periodic SMI every 8s */
202#endif
Simon Glass31f57c22015-03-05 12:25:15 -0700203 x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
Simon Glass72cd0852014-11-14 18:18:35 -0700204
205 /* Set the board's GPI routing. */
206 ret = pch_gpi_routing(blob, node, dev);
207 if (ret)
208 return ret;
209
Simon Glass31f57c22015-03-05 12:25:15 -0700210 pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe;
Simon Glass72cd0852014-11-14 18:18:35 -0700211
212 writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
213 "intel,gpe0-enable", 0));
214 writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
215 "intel,alt-gp-smi-enable", 0));
216
217 /* Set up power management block and determine sleep mode */
218 reg32 = inl(pmbase + 0x04); /* PM1_CNT */
219 reg32 &= ~(7 << 10); /* SLP_TYP */
220 reg32 |= (1 << 0); /* SCI_EN */
221 outl(reg32, pmbase + 0x04);
222
223 /* Clear magic status bits to prevent unexpected wake */
224 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
225 clrbits_le32(RCB_REG(0x3f02), 0xf);
226
227 return 0;
228}
229
230static void pch_rtc_init(pci_dev_t dev)
231{
232 int rtc_failed;
233 u8 reg8;
234
Simon Glass31f57c22015-03-05 12:25:15 -0700235 reg8 = x86_pci_read_config8(dev, GEN_PMCON_3);
Simon Glass72cd0852014-11-14 18:18:35 -0700236 rtc_failed = reg8 & RTC_BATTERY_DEAD;
237 if (rtc_failed) {
238 reg8 &= ~RTC_BATTERY_DEAD;
Simon Glass31f57c22015-03-05 12:25:15 -0700239 x86_pci_write_config8(dev, GEN_PMCON_3, reg8);
Simon Glass72cd0852014-11-14 18:18:35 -0700240 }
241 debug("rtc_failed = 0x%x\n", rtc_failed);
242
243#if CONFIG_HAVE_ACPI_RESUME
244 /* Avoid clearing pending interrupts and resetting the RTC control
245 * register in the resume path because the Linux kernel relies on
246 * this to know if it should restart the RTC timerqueue if the wake
247 * was due to the RTC alarm.
248 */
249 if (acpi_get_slp_type() == 3)
250 return;
251#endif
252 /* TODO: Handle power failure */
253 if (rtc_failed)
254 printf("RTC power failed\n");
Simon Glass72cd0852014-11-14 18:18:35 -0700255}
256
257/* CougarPoint PCH Power Management init */
258static void cpt_pm_init(pci_dev_t dev)
259{
260 debug("CougarPoint PM init\n");
Simon Glass31f57c22015-03-05 12:25:15 -0700261 x86_pci_write_config8(dev, 0xa9, 0x47);
Simon Glass72cd0852014-11-14 18:18:35 -0700262 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
263
264 setbits_le32(RCB_REG(0x228c), 1 << 0);
265 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
266 setbits_le32(RCB_REG(0x0900), 1 << 14);
267 writel(0xc0388400, RCB_REG(0x2304));
268 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
269 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
270 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
271 writel(0x050f0000, RCB_REG(0x3318));
272 writel(0x04000000, RCB_REG(0x3324));
273 setbits_le32(RCB_REG(0x3340), 0xfffff);
274 setbits_le32(RCB_REG(0x3344), 1 << 1);
275
276 writel(0x0001c000, RCB_REG(0x3360));
277 writel(0x00061100, RCB_REG(0x3368));
278 writel(0x7f8fdfff, RCB_REG(0x3378));
279 writel(0x000003fc, RCB_REG(0x337c));
280 writel(0x00001000, RCB_REG(0x3388));
281 writel(0x0001c000, RCB_REG(0x3390));
282 writel(0x00000800, RCB_REG(0x33a0));
283 writel(0x00001000, RCB_REG(0x33b0));
284 writel(0x00093900, RCB_REG(0x33c0));
285 writel(0x24653002, RCB_REG(0x33cc));
286 writel(0x062108fe, RCB_REG(0x33d0));
287 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
288 writel(0x01010000, RCB_REG(0x3a28));
289 writel(0x01010404, RCB_REG(0x3a2c));
290 writel(0x01041041, RCB_REG(0x3a80));
291 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
292 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
293 setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
294 writel(0x00000001, RCB_REG(0x3a6c));
295 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
296 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
297 writel(0, RCB_REG(0x33c8));
298 setbits_le32(RCB_REG(0x21b0), 0xf);
299}
300
301/* PantherPoint PCH Power Management init */
302static void ppt_pm_init(pci_dev_t dev)
303{
304 debug("PantherPoint PM init\n");
Simon Glass31f57c22015-03-05 12:25:15 -0700305 x86_pci_write_config8(dev, 0xa9, 0x47);
Simon Glass72cd0852014-11-14 18:18:35 -0700306 setbits_le32(RCB_REG(0x2238), 1 << 0);
307 setbits_le32(RCB_REG(0x228c), 1 << 0);
308 setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
309 setbits_le16(RCB_REG(0x0900), 1 << 14);
310 writel(0xc03b8400, RCB_REG(0x2304));
311 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
312 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
313 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
314 writel(0x054f0000, RCB_REG(0x3318));
315 writel(0x04000000, RCB_REG(0x3324));
316 setbits_le32(RCB_REG(0x3340), 0xfffff);
317 setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
318 writel(0x0001c000, RCB_REG(0x3360));
319 writel(0x00061100, RCB_REG(0x3368));
320 writel(0x7f8fdfff, RCB_REG(0x3378));
321 writel(0x000003fd, RCB_REG(0x337c));
322 writel(0x00001000, RCB_REG(0x3388));
323 writel(0x0001c000, RCB_REG(0x3390));
324 writel(0x00000800, RCB_REG(0x33a0));
325 writel(0x00001000, RCB_REG(0x33b0));
326 writel(0x00093900, RCB_REG(0x33c0));
327 writel(0x24653002, RCB_REG(0x33cc));
328 writel(0x067388fe, RCB_REG(0x33d0));
329 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
330 writel(0x01010000, RCB_REG(0x3a28));
331 writel(0x01010404, RCB_REG(0x3a2c));
332 writel(0x01040000, RCB_REG(0x3a80));
333 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
334 /* SATA 2/3 disabled */
335 setbits_le32(RCB_REG(0x3a84), 1 << 24);
336 /* SATA 4/5 disabled */
337 setbits_le32(RCB_REG(0x3a88), 1 << 0);
338 writel(0x00000001, RCB_REG(0x3a6c));
339 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
340 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
341 setbits_le32(RCB_REG(0x33a4), (1 << 0));
342 writel(0, RCB_REG(0x33c8));
343 setbits_le32(RCB_REG(0x21b0), 0xf);
344}
345
346static void enable_hpet(void)
347{
348 /* Move HPET to default address 0xfed00000 and enable it */
349 clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
350}
351
352static void enable_clock_gating(pci_dev_t dev)
353{
354 u32 reg32;
355 u16 reg16;
356
357 setbits_le32(RCB_REG(0x2234), 0xf);
358
Simon Glass31f57c22015-03-05 12:25:15 -0700359 reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
Simon Glass72cd0852014-11-14 18:18:35 -0700360 reg16 |= (1 << 2) | (1 << 11);
Simon Glass31f57c22015-03-05 12:25:15 -0700361 x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
Simon Glass72cd0852014-11-14 18:18:35 -0700362
363 pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
364 pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
365 pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
366 pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
367
368 reg32 = readl(RCB_REG(CG));
369 reg32 |= (1 << 31);
370 reg32 |= (1 << 29) | (1 << 28);
371 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
372 reg32 |= (1 << 16);
373 reg32 |= (1 << 17);
374 reg32 |= (1 << 18);
375 reg32 |= (1 << 22);
376 reg32 |= (1 << 23);
377 reg32 &= ~(1 << 20);
378 reg32 |= (1 << 19);
379 reg32 |= (1 << 0);
380 reg32 |= (0xf << 1);
381 writel(reg32, RCB_REG(CG));
382
383 setbits_le32(RCB_REG(0x38c0), 0x7);
384 setbits_le32(RCB_REG(0x36d4), 0x6680c004);
385 setbits_le32(RCB_REG(0x3564), 0x3);
386}
387
388#if CONFIG_HAVE_SMI_HANDLER
389static void pch_lock_smm(pci_dev_t dev)
390{
391#if TEST_SMM_FLASH_LOCKDOWN
392 u8 reg8;
393#endif
394
395 if (acpi_slp_type != 3) {
396#if ENABLE_ACPI_MODE_IN_COREBOOT
397 debug("Enabling ACPI via APMC:\n");
398 outb(0xe1, 0xb2); /* Enable ACPI mode */
399 debug("done.\n");
400#else
401 debug("Disabling ACPI via APMC:\n");
402 outb(0x1e, 0xb2); /* Disable ACPI mode */
403 debug("done.\n");
404#endif
405 }
406
407 /* Don't allow evil boot loaders, kernels, or
408 * userspace applications to deceive us:
409 */
410 smm_lock();
411
412#if TEST_SMM_FLASH_LOCKDOWN
413 /* Now try this: */
414 debug("Locking BIOS to RO... ");
Simon Glass31f57c22015-03-05 12:25:15 -0700415 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
Simon Glass72cd0852014-11-14 18:18:35 -0700416 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
417 (reg8 & 1) ? "rw" : "ro");
418 reg8 &= ~(1 << 0); /* clear BIOSWE */
Simon Glass31f57c22015-03-05 12:25:15 -0700419 x86_pci_write_config8(dev, 0xdc, reg8);
Simon Glass72cd0852014-11-14 18:18:35 -0700420 reg8 |= (1 << 1); /* set BLE */
Simon Glass31f57c22015-03-05 12:25:15 -0700421 x86_pci_write_config8(dev, 0xdc, reg8);
Simon Glass72cd0852014-11-14 18:18:35 -0700422 debug("ok.\n");
Simon Glass31f57c22015-03-05 12:25:15 -0700423 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
Simon Glass72cd0852014-11-14 18:18:35 -0700424 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
425 (reg8 & 1) ? "rw" : "ro");
426
427 debug("Writing:\n");
428 writeb(0, 0xfff00000);
429 debug("Testing:\n");
430 reg8 |= (1 << 0); /* set BIOSWE */
Simon Glass31f57c22015-03-05 12:25:15 -0700431 x86_pci_write_config8(dev, 0xdc, reg8);
Simon Glass72cd0852014-11-14 18:18:35 -0700432
Simon Glass31f57c22015-03-05 12:25:15 -0700433 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
Simon Glass72cd0852014-11-14 18:18:35 -0700434 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
435 (reg8 & 1) ? "rw" : "ro");
436 debug("Done.\n");
437#endif
438}
439#endif
440
441static void pch_disable_smm_only_flashing(pci_dev_t dev)
442{
443 u8 reg8;
444
445 debug("Enabling BIOS updates outside of SMM... ");
Simon Glass31f57c22015-03-05 12:25:15 -0700446 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
Simon Glass72cd0852014-11-14 18:18:35 -0700447 reg8 &= ~(1 << 5);
Simon Glass31f57c22015-03-05 12:25:15 -0700448 x86_pci_write_config8(dev, 0xdc, reg8);
Simon Glass72cd0852014-11-14 18:18:35 -0700449}
450
451static void pch_fixups(pci_dev_t dev)
452{
453 u8 gen_pmcon_2;
454
455 /* Indicate DRAM init done for MRC S3 to know it can resume */
Simon Glass31f57c22015-03-05 12:25:15 -0700456 gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2);
Simon Glass72cd0852014-11-14 18:18:35 -0700457 gen_pmcon_2 |= (1 << 7);
Simon Glass31f57c22015-03-05 12:25:15 -0700458 x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
Simon Glass72cd0852014-11-14 18:18:35 -0700459
460 /* Enable DMI ASPM in the PCH */
461 clrbits_le32(RCB_REG(0x2304), 1 << 10);
462 setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
463 setbits_le32(RCB_REG(0x21a8), 0x3);
464}
465
Simon Glass2b605152014-11-12 22:42:15 -0700466int lpc_early_init(const void *blob, int node, pci_dev_t dev)
467{
468 struct reg_info {
469 u32 base;
470 u32 size;
471 } values[4], *ptr;
472 int count;
473 int i;
474
Simon Glass72cd0852014-11-14 18:18:35 -0700475 count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
Simon Glass2b605152014-11-12 22:42:15 -0700476 (u32 *)values, sizeof(values) / sizeof(u32));
477 if (count < 0)
478 return -EINVAL;
479
480 /* Set COM1/COM2 decode range */
Simon Glass31f57c22015-03-05 12:25:15 -0700481 x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
Simon Glass2b605152014-11-12 22:42:15 -0700482
483 /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
Simon Glass31f57c22015-03-05 12:25:15 -0700484 x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
Simon Glass2b605152014-11-12 22:42:15 -0700485 GAMEL_LPC_EN | COMA_LPC_EN);
486
487 /* Write all registers but use 0 if we run out of data */
488 count = count * sizeof(u32) / sizeof(values[0]);
489 for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
490 u32 reg = 0;
491
492 if (i < count)
493 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
Simon Glass31f57c22015-03-05 12:25:15 -0700494 x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
Simon Glass2b605152014-11-12 22:42:15 -0700495 }
496
497 return 0;
498}
Simon Glass72cd0852014-11-14 18:18:35 -0700499
500int lpc_init(struct pci_controller *hose, pci_dev_t dev)
501{
502 const void *blob = gd->fdt_blob;
503 int node;
504
505 debug("pch: lpc_init\n");
506 pci_write_bar32(hose, dev, 0, 0);
507 pci_write_bar32(hose, dev, 1, 0xff800000);
508 pci_write_bar32(hose, dev, 2, 0xfec00000);
509 pci_write_bar32(hose, dev, 3, 0x800);
510 pci_write_bar32(hose, dev, 4, 0x900);
511
Simon Glass90b16d12015-03-26 09:29:29 -0600512 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
Simon Glass72cd0852014-11-14 18:18:35 -0700513 if (node < 0)
514 return -ENOENT;
515
516 /* Set the value for PCI command register. */
Simon Glass31f57c22015-03-05 12:25:15 -0700517 x86_pci_write_config16(dev, PCI_COMMAND, 0x000f);
Simon Glass72cd0852014-11-14 18:18:35 -0700518
519 /* IO APIC initialization. */
520 pch_enable_apic(dev);
521
522 pch_enable_serial_irqs(dev);
523
524 /* Setup the PIRQ. */
525 pch_pirq_init(blob, node, dev);
526
527 /* Setup power options. */
528 pch_power_options(blob, node, dev);
529
530 /* Initialize power management */
531 switch (pch_silicon_type()) {
532 case PCH_TYPE_CPT: /* CougarPoint */
533 cpt_pm_init(dev);
534 break;
535 case PCH_TYPE_PPT: /* PantherPoint */
536 ppt_pm_init(dev);
537 break;
538 default:
539 printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
540 PCI_FUNC(dev));
541 return -ENOSYS;
542 }
543
544 /* Initialize the real time clock. */
545 pch_rtc_init(dev);
546
547 /* Initialize the High Precision Event Timers, if present. */
548 enable_hpet();
549
550 /* Initialize Clock Gating */
551 enable_clock_gating(dev);
552
553 pch_disable_smm_only_flashing(dev);
554
555#if CONFIG_HAVE_SMI_HANDLER
556 pch_lock_smm(dev);
557#endif
558
559 pch_fixups(dev);
560
561 return 0;
562}
563
564void lpc_enable(pci_dev_t dev)
565{
566 /* Enable PCH Display Port */
567 writew(0x0010, RCB_REG(DISPBDF));
568 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
569}
Simon Glass90b16d12015-03-26 09:29:29 -0600570
571static const struct udevice_id bd82x6x_lpc_ids[] = {
572 { .compatible = "intel,bd82x6x-lpc" },
573 { }
574};
575
576U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
577 .name = "lpc",
578 .id = UCLASS_LPC,
579 .of_match = bd82x6x_lpc_ids,
580};