blob: d705830804e2666b8948e37d6e9d4a16705682e4 [file] [log] [blame]
Vikas Manochae66c49f2016-02-11 15:47:20 -08001/*
2 * (C) Copyright 2016
3 * Vikas Manocha, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_SYS_THUMB_BUILD
Vikas Manochaadcc90b2016-03-09 15:18:14 -080012/*#define CONFIG_SYS_NO_FLASH*/
Vikas Manochae66c49f2016-02-11 15:47:20 -080013
Vikas Manochae66c49f2016-02-11 15:47:20 -080014#define CONFIG_SYS_FLASH_BASE 0x08000000
15#define CONFIG_SYS_INIT_SP_ADDR 0x20050000
16#define CONFIG_SYS_TEXT_BASE 0x08000000
17
18#define CONFIG_SYS_ICACHE_OFF
19#define CONFIG_SYS_DCACHE_OFF
20
21/*
22 * Configuration of the external SDRAM memory
23 */
24#define CONFIG_NR_DRAM_BANKS 1
Toshifumi NISHINAGA25c1b132016-07-08 01:02:25 +090025#define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024)
Vikas Manochae66c49f2016-02-11 15:47:20 -080026#define CONFIG_SYS_RAM_CS 1
27#define CONFIG_SYS_RAM_FREQ_DIV 2
Toshifumi NISHINAGA25c1b132016-07-08 01:02:25 +090028#define CONFIG_SYS_RAM_BASE 0xC0000000
Vikas Manochae66c49f2016-02-11 15:47:20 -080029#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
Toshifumi NISHINAGA25c1b132016-07-08 01:02:25 +090030#define CONFIG_SYS_LOAD_ADDR 0xC0400000
31#define CONFIG_LOADADDR 0xC0400000
Vikas Manochae66c49f2016-02-11 15:47:20 -080032
Vikas Manochaadcc90b2016-03-09 15:18:14 -080033#define CONFIG_SYS_MAX_FLASH_SECT 8
34#define CONFIG_SYS_MAX_FLASH_BANKS 1
Vikas Manochae66c49f2016-02-11 15:47:20 -080035
Vikas Manochae66c49f2016-02-11 15:47:20 -080036#define CONFIG_ENV_IS_NOWHERE
Vikas Manochae66c49f2016-02-11 15:47:20 -080037#define CONFIG_ENV_SIZE (8 << 10)
38
39#define CONFIG_STM32_GPIO
Vikas Manochaadcc90b2016-03-09 15:18:14 -080040#define CONFIG_STM32_FLASH
Vikas Manochae66c49f2016-02-11 15:47:20 -080041#define CONFIG_STM32X7_SERIAL
42
Michael Kurzb20b70f2017-01-22 16:04:27 +010043#define CONFIG_DESIGNWARE_ETH
44#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
45#define CONFIG_DW_ALTDESCRIPTOR
46#define CONFIG_MII
Michael Kurzfc0d3db2017-01-22 16:04:29 +010047#define CONFIG_PHY_SMSC
Michael Kurzb20b70f2017-01-22 16:04:27 +010048
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090049#define CONFIG_STM32_HSE_HZ 25000000
50#define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */
Vikas Manochae66c49f2016-02-11 15:47:20 -080051#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
52
53#define CONFIG_CMDLINE_TAG
54#define CONFIG_SETUP_MEMORY_TAGS
55#define CONFIG_INITRD_TAG
56#define CONFIG_REVISION_TAG
57
58#define CONFIG_SYS_CBSIZE 1024
59#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
60 + sizeof(CONFIG_SYS_PROMPT) + 16)
61
62#define CONFIG_SYS_MAXARGS 16
Michael Kurzb20b70f2017-01-22 16:04:27 +010063#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
64#define CONFIG_STACKSIZE (256 * 1024)
Vikas Manochae66c49f2016-02-11 15:47:20 -080065
66#define CONFIG_BAUDRATE 115200
67#define CONFIG_BOOTARGS \
68 "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
69#define CONFIG_BOOTCOMMAND \
70 "run bootcmd_romfs"
71
72#define CONFIG_EXTRA_ENV_SETTINGS \
73 "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
74 "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
75 "bootm 0x08044000 - 0x08042000\0"
76
Vikas Manochae66c49f2016-02-11 15:47:20 -080077
78/*
79 * Command line configuration.
80 */
81#define CONFIG_SYS_LONGHELP
Vikas Manochae66c49f2016-02-11 15:47:20 -080082#define CONFIG_AUTO_COMPLETE
83#define CONFIG_CMDLINE_EDITING
84
85#define CONFIG_CMD_MEM
Vikas Manochae66c49f2016-02-11 15:47:20 -080086#endif /* __CONFIG_H */