| Tirumala Marri | 1b8fec1 | 2010-09-28 14:15:14 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010, Applied Micro Circuits Corporation |
| 3 | * Author: Tirumala R Marri <tmarri@apm.com> |
| 4 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Tirumala Marri | 1b8fec1 | 2010-09-28 14:15:14 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _APM821XX_H_ |
| 9 | #define _APM821XX_H_ |
| 10 | |
| 11 | #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ |
| 12 | |
| 13 | /* Memory mapped registers */ |
| 14 | #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 |
| 15 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) |
| 16 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) |
| 17 | |
| 18 | #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) |
| 19 | |
| 20 | #define SDR0_SRST0_DMC 0x00200000 |
| 21 | #define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ |
| 22 | |
| 23 | /* AHB config. */ |
| 24 | #define AHB_TOP 0xA4 |
| 25 | #define AHB_BOT 0xA5 |
| 26 | |
| 27 | /* clk divisors */ |
| 28 | #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ |
| 29 | #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ |
| 30 | #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ |
| 31 | #define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ |
| 32 | #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ |
| 33 | #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ |
| 34 | #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ |
| 35 | #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ |
| 36 | #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ |
| 37 | |
| 38 | /* |
| 39 | + * Clocking Controller |
| 40 | + */ |
| 41 | #define CPR0_CLKUPD 0x0020 |
| 42 | #define CPR0_PLLC 0x0040 |
| 43 | #define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) |
| 44 | #define CPR0_PLLD 0x0060 |
| 45 | #define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) |
| 46 | #define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) |
| 47 | #define CPR0_CPUD 0x0080 |
| 48 | #define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) |
| 49 | #define CPR0_PLB2D 0x00a0 |
| 50 | #define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) |
| 51 | #define CPR0_OPBD 0x00c0 |
| 52 | #define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) |
| 53 | #define CPR0_PERD 0x00e0 |
| 54 | #define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) |
| 55 | #define CPR0_DDR2D 0x0100 |
| 56 | #define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) |
| 57 | #define CLK_ICFG 0x0140 |
| 58 | |
| 59 | #endif /* _APM821XX_H_ */ |