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Peng Fana2b96ec2018-10-16 04:50:30 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8#ifndef _IMX8IMAGE_H_
9#define _IMX8IMAGE_H_
10
11#include <image.h>
12#include <inttypes.h>
13#include "imagetool.h"
Peng Fana2b96ec2018-10-16 04:50:30 +000014
15#define __packed __attribute__((packed))
16
17#define IV_MAX_LEN 32
18#define HASH_MAX_LEN 64
19#define MAX_NUM_IMGS 6
20#define MAX_NUM_SRK_RECORDS 4
21
22#define IVT_HEADER_TAG_B0 0x87
23#define IVT_VERSION_B0 0x00
24
25#define IMG_FLAG_HASH_SHA256 0x000
26#define IMG_FLAG_HASH_SHA384 0x100
27#define IMG_FLAG_HASH_SHA512 0x200
28
29#define IMG_FLAG_ENCRYPTED_MASK 0x400
30#define IMG_FLAG_ENCRYPTED_SHIFT 0x0A
31
32#define IMG_FLAG_BOOTFLAGS_MASK 0xFFFF0000
33#define IMG_FLAG_BOOTFLAGS_SHIFT 0x10
34
35#define IMG_ARRAY_ENTRY_SIZE 128
36#define HEADER_IMG_ARRAY_OFFSET 0x10
37
38#define HASH_TYPE_SHA_256 256
39#define HASH_TYPE_SHA_384 384
40#define HASH_TYPE_SHA_512 512
41
42#define IMAGE_HASH_ALGO_DEFAULT 384
43#define IMAGE_PADDING_DEFAULT 0x1000
44
45#define DCD_ENTRY_ADDR_IN_SCFW 0x240
46
47#define CONTAINER_ALIGNMENT 0x400
48#define CONTAINER_FLAGS_DEFAULT 0x10
49#define CONTAINER_FUSE_DEFAULT 0x0
50
51#define SIGNATURE_BLOCK_HEADER_LENGTH 0x10
52
53#define MAX_NUM_OF_CONTAINER 2
54
55#define FIRST_CONTAINER_HEADER_LENGTH 0x400
56
57#define BOOT_IMG_META_MU_RID_SHIFT 10
58#define BOOT_IMG_META_PART_ID_SHIFT 20
59
60#define IMAGE_A35_DEFAULT_META(PART) (((PART == 0) ? \
61 PARTITION_ID_AP : PART) << \
62 BOOT_IMG_META_PART_ID_SHIFT | \
63 SC_R_MU_0A << \
64 BOOT_IMG_META_MU_RID_SHIFT | \
65 SC_R_A35_0)
66
67#define IMAGE_A53_DEFAULT_META(PART) (((PART == 0) ? \
68 PARTITION_ID_AP : PART) << \
69 BOOT_IMG_META_PART_ID_SHIFT | \
70 SC_R_MU_0A << \
71 BOOT_IMG_META_MU_RID_SHIFT | \
72 SC_R_A53_0)
73
74#define IMAGE_A72_DEFAULT_META(PART) (((PART == 0) ? \
75 PARTITION_ID_AP : PART) << \
76 BOOT_IMG_META_PART_ID_SHIFT | \
77 SC_R_MU_0A << \
78 BOOT_IMG_META_MU_RID_SHIFT | \
79 SC_R_A72_0)
80
81#define IMAGE_M4_0_DEFAULT_META(PART) (((PART == 0) ? \
82 PARTITION_ID_M4 : PART) << \
83 BOOT_IMG_META_PART_ID_SHIFT | \
84 SC_R_M4_0_MU_1A << \
85 BOOT_IMG_META_MU_RID_SHIFT | \
86 SC_R_M4_0_PID0)
87
88#define IMAGE_M4_1_DEFAULT_META(PART) (((PART == 0) ? \
89 PARTITION_ID_M4 : PART) << \
90 BOOT_IMG_META_PART_ID_SHIFT | \
91 SC_R_M4_1_MU_1A << \
92 BOOT_IMG_META_MU_RID_SHIFT | \
93 SC_R_M4_1_PID0)
94
95#define CONTAINER_IMAGE_ARRAY_START_OFFSET 0x2000
96
97typedef struct {
98 uint8_t version;
99 uint16_t length;
100 uint8_t tag;
101 uint16_t srk_table_offset;
102 uint16_t cert_offset;
103 uint16_t blob_offset;
104 uint16_t signature_offset;
105 uint32_t reserved;
106} __packed sig_blk_hdr_t;
107
108typedef struct {
109 uint32_t offset;
110 uint32_t size;
111 uint64_t dst;
112 uint64_t entry;
113 uint32_t hab_flags;
114 uint32_t meta;
115 uint8_t hash[HASH_MAX_LEN];
116 uint8_t iv[IV_MAX_LEN];
117} __packed boot_img_t;
118
119typedef struct {
120 uint8_t version;
121 uint16_t length;
122 uint8_t tag;
123 uint32_t flags;
124 uint16_t sw_version;
125 uint8_t fuse_version;
126 uint8_t num_images;
127 uint16_t sig_blk_offset;
128 uint16_t reserved;
129 boot_img_t img[MAX_NUM_IMGS];
130 sig_blk_hdr_t sig_blk_hdr;
131 uint32_t sigblk_size;
132 uint32_t padding;
133} __packed flash_header_v3_t;
134
135typedef struct {
136 flash_header_v3_t fhdr[MAX_NUM_OF_CONTAINER];
137} __packed imx_header_v3_t;
138
139struct image_array {
140 char *name;
141 unsigned int core_type;
142 unsigned int core_id;
143 unsigned int load_addr;
144};
145
146enum imx8image_cmd {
147 CMD_INVALID,
148 CMD_BOOT_FROM,
149 CMD_FUSE_VERSION,
150 CMD_SW_VERSION,
151 CMD_MSG_BLOCK,
152 CMD_FILEOFF,
153 CMD_FLAG,
154 CMD_APPEND,
155 CMD_PARTITION,
156 CMD_SOC_TYPE,
157 CMD_CONTAINER,
158 CMD_IMAGE,
159 CMD_DATA
160};
161
162enum imx8image_core_type {
163 CFG_CORE_INVALID,
164 CFG_SCU,
165 CFG_M40,
166 CFG_M41,
167 CFG_A35,
Peng Fan6ec65c82022-07-26 16:41:19 +0800168 CFG_A55,
Peng Fana2b96ec2018-10-16 04:50:30 +0000169 CFG_A53,
170 CFG_A72
171};
172
173enum imx8image_fld_types {
174 CFG_INVALID = -1,
175 CFG_COMMAND,
176 CFG_CORE_TYPE,
177 CFG_IMAGE_NAME,
178 CFG_LOAD_ADDR
179};
180
181typedef enum SOC_TYPE {
182 NONE = 0,
183 QX,
Peng Fan6ec65c82022-07-26 16:41:19 +0800184 QM,
185 ULP,
186 IMX9
Peng Fana2b96ec2018-10-16 04:50:30 +0000187} soc_type_t;
188
189typedef enum option_type {
190 NO_IMG = 0,
191 DCD,
192 SCFW,
193 SECO,
194 M40,
195 M41,
196 AP,
197 OUTPUT,
198 SCD,
199 CSF,
200 FLAG,
201 DEVICE,
202 NEW_CONTAINER,
203 APPEND,
204 DATA,
205 PARTITION,
206 FILEOFF,
Peng Fan6ec65c82022-07-26 16:41:19 +0800207 MSG_BLOCK,
208 SENTINEL,
209 UPOWER
Peng Fana2b96ec2018-10-16 04:50:30 +0000210} option_type_t;
211
212typedef struct {
213 option_type_t option;
214 char *filename;
215 uint64_t src;
216 uint64_t dst;
217 uint64_t entry;
218 uint64_t ext;
219} image_t;
220
221#define CORE_SC 1
222#define CORE_CM4_0 2
223#define CORE_CM4_1 3
224#define CORE_CA53 4
225#define CORE_CA35 4
226#define CORE_CA72 5
227#define CORE_SECO 6
228
Peng Fan6ec65c82022-07-26 16:41:19 +0800229#define CORE_ULP_CM33 0x1
230#define CORE_ULP_CA35 0x2
231#define CORE_ULP_UPOWER 0x4
232#define CORE_ULP_SENTINEL 0x6
233
Peng Fana2b96ec2018-10-16 04:50:30 +0000234#define SC_R_OTP 357U
235#define SC_R_DEBUG 354U
236#define SC_R_ROM_0 236U
237
238#define MSG_DEBUG_EN SC_R_DEBUG
239#define MSG_FUSE SC_R_OTP
240#define MSG_FIELD SC_R_ROM_0
241
242#define IMG_TYPE_CSF 0x01 /* CSF image type */
243#define IMG_TYPE_SCD 0x02 /* SCD image type */
244#define IMG_TYPE_EXEC 0x03 /* Executable image type */
245#define IMG_TYPE_DATA 0x04 /* Data image type */
246#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */
247#define IMG_TYPE_SECO 0x06 /* SECO image type */
Peng Fan6ec65c82022-07-26 16:41:19 +0800248#define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */
Peng Fana2b96ec2018-10-16 04:50:30 +0000249#define IMG_TYPE_PROV 0x07 /* Provisioning image type */
250#define IMG_TYPE_DEK 0x08 /* DEK validation type */
251
252#define IMG_TYPE_SHIFT 0
253#define IMG_TYPE_MASK 0x1f
254#define IMG_TYPE(x) (((x) & IMG_TYPE_MASK) >> IMG_TYPE_SHIFT)
255
256#define BOOT_IMG_FLAGS_CORE_MASK 0xF
257#define BOOT_IMG_FLAGS_CORE_SHIFT 0x04
258#define BOOT_IMG_FLAGS_CPU_RID_MASK 0x3FF0
259#define BOOT_IMG_FLAGS_CPU_RID_SHIFT 4
260#define BOOT_IMG_FLAGS_MU_RID_MASK 0xFFC000
261#define BOOT_IMG_FLAGS_MU_RID_SHIFT 14
262#define BOOT_IMG_FLAGS_PARTITION_ID_MASK 0x1F000000
263#define BOOT_IMG_FLAGS_PARTITION_ID_SHIFT 24
264
265/* Resource id used in scfw */
266#define SC_R_A35_0 508
267#define SC_R_A53_0 1
268#define SC_R_A72_0 6
269#define SC_R_MU_0A 213
270#define SC_R_M4_0_PID0 278
271#define SC_R_M4_0_MU_1A 297
272#define SC_R_M4_1_PID0 298
273#define SC_R_M4_1_MU_1A 317
274#define PARTITION_ID_M4 0
275#define PARTITION_ID_AP 1
276
277#define IMG_STACK_SIZE 32
278
279#define append(p, s, l) do { \
280 memcpy((p), (uint8_t *)(s), (l)); (p) += (l); \
281 } while (0)
282
283#endif