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Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05301/*
2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Based on davinci_dvevm.h. Original Copyrights follow:
5 *
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05309 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * Board
16 */
Ben Gardiner3d248d32010-10-14 17:26:29 -040017#define CONFIG_DRIVER_TI_EMAC
Lad, Prabhakar63777662012-06-24 21:35:23 +000018/* check if direct NOR boot config is used */
19#ifndef CONFIG_DIRECT_NOR_BOOT
Stefano Babicd73a8a12010-11-11 15:38:02 +010020#define CONFIG_USE_SPIFLASH
Lad, Prabhakar63777662012-06-24 21:35:23 +000021#endif
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053022
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -040023
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053024/*
25 * SoC Configuration
26 */
27#define CONFIG_MACH_DAVINCI_DA850_EVM
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053028#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
Christian Riesch52b0f872011-11-28 23:46:18 +000029#define CONFIG_SOC_DA850 /* TI DA850 SoC */
Christian Rieschb67d8812012-02-02 00:44:39 +000030#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053031#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
32#define CONFIG_SYS_OSCIN_FREQ 24000000
33#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
34#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Sughosh Ganu6b873dc2012-02-02 00:44:41 +000035#define CONFIG_SYS_DA850_PLL_INIT
36#define CONFIG_SYS_DA850_DDR_INIT
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053037
Lad, Prabhakar63777662012-06-24 21:35:23 +000038#ifdef CONFIG_DIRECT_NOR_BOOT
39#define CONFIG_ARCH_CPU_INIT
40#define CONFIG_DA8XX_GPIO
41#define CONFIG_SYS_TEXT_BASE 0x60000000
42#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
43#define CONFIG_DA850_LOWLEVEL
44#else
45#define CONFIG_SYS_TEXT_BASE 0xc1080000
46#endif
47
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053048/*
49 * Memory Info
50 */
51#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053052#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
53#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
Ben Gardiner97003752010-08-23 09:08:15 -040054#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053055
56/* memtest start addr */
57#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
58
59/* memtest will be run on 16MB */
60#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
61
62#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053063
Christian Riesch3d2c8e62011-12-09 09:47:37 +000064#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
65 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
66 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
67 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
68 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
69 DAVINCI_SYSCFG_SUSPSRC_I2C)
70
71/*
72 * PLL configuration
73 */
74#define CONFIG_SYS_DV_CLKMODE 0
75#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
76#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
77#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
78#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
79#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
80#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
81#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
82#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
83
84#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
85#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
86#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
87#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
88
89#define CONFIG_SYS_DA850_PLL0_PLLM 24
90#define CONFIG_SYS_DA850_PLL1_PLLM 21
91
92/*
93 * DDR2 memory configuration
94 */
95#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
96 DV_DDR_PHY_EXT_STRBEN | \
97 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
98
99#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
100 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
101 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
102 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
103 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
104 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
105 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
106 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
107
108/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
109#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
110
111#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
112 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
113 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
114 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
115 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
116 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
117 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
118 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
119 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
120
121#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
122 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
123 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
124 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
125 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
126 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
127 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
128 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
129
130#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
131#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
132
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530133/*
134 * Serial Driver info
135 */
136#define CONFIG_SYS_NS16550
137#define CONFIG_SYS_NS16550_SERIAL
138#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
139#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
140#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
141#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
142#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530143
Stefano Babicd73a8a12010-11-11 15:38:02 +0100144#define CONFIG_SPI
Stefano Babicd73a8a12010-11-11 15:38:02 +0100145#define CONFIG_SPI_FLASH_STMICRO
Manjunathappa, Prakash8cf47392011-09-03 22:19:56 -0400146#define CONFIG_SPI_FLASH_WINBOND
Tom Rinidf166cc2013-10-08 15:08:38 -0400147#define CONFIG_CMD_SF
Stefano Babicd73a8a12010-11-11 15:38:02 +0100148#define CONFIG_DAVINCI_SPI
149#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
150#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
151#define CONFIG_SF_DEFAULT_SPEED 30000000
152#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
153
Lad, Prabhakar42612102012-06-24 21:35:19 +0000154#ifdef CONFIG_USE_SPIFLASH
155#define CONFIG_SPL_SPI_SUPPORT
156#define CONFIG_SPL_SPI_FLASH_SUPPORT
157#define CONFIG_SPL_SPI_LOAD
Lad, Prabhakar42612102012-06-24 21:35:19 +0000158#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
Peter Howard2a10f8b2014-12-17 12:14:36 +1100159#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
Lad, Prabhakar42612102012-06-24 21:35:19 +0000160#endif
161
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530162/*
163 * I2C Configuration
164 */
Vitaly Andrianove8459dc2014-04-04 13:16:52 -0400165#define CONFIG_SYS_I2C
166#define CONFIG_SYS_I2C_DAVINCI
167#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
168#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500169#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530170
171/*
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400172 * Flash & Environment
173 */
174#ifdef CONFIG_USE_NAND
175#undef CONFIG_ENV_IS_IN_FLASH
176#define CONFIG_NAND_DAVINCI
177#define CONFIG_SYS_NO_FLASH
178#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
179#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
180#define CONFIG_ENV_SIZE (128 << 10)
181#define CONFIG_SYS_NAND_USE_FLASH_BBT
182#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
183#define CONFIG_SYS_NAND_PAGE_2K
184#define CONFIG_SYS_NAND_CS 3
185#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Eric Benard34fa0702013-04-22 05:55:00 +0000186#define CONFIG_SYS_NAND_MASK_CLE 0x10
187#define CONFIG_SYS_NAND_MASK_ALE 0x8
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400188#undef CONFIG_SYS_NAND_HW_ECC
189#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000190#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
191#define CONFIG_SYS_NAND_5_ADDR_CYCLE
192#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
193#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
194#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
195#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
196#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
197#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
198#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
199 CONFIG_SYS_NAND_U_BOOT_SIZE - \
200 CONFIG_SYS_MALLOC_LEN - \
201 GENERATED_GBL_DATA_SIZE)
202#define CONFIG_SYS_NAND_ECCPOS { \
203 24, 25, 26, 27, 28, \
204 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
205 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
206 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
207 59, 60, 61, 62, 63 }
208#define CONFIG_SYS_NAND_PAGE_COUNT 64
209#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
210#define CONFIG_SYS_NAND_ECCSIZE 512
211#define CONFIG_SYS_NAND_ECCBYTES 10
212#define CONFIG_SYS_NAND_OOBSIZE 64
213#define CONFIG_SPL_NAND_SUPPORT
Scott Wood6f2f01b2012-09-20 19:09:07 -0500214#define CONFIG_SPL_NAND_BASE
215#define CONFIG_SPL_NAND_DRIVERS
216#define CONFIG_SPL_NAND_ECC
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000217#define CONFIG_SPL_NAND_SIMPLE
218#define CONFIG_SPL_NAND_LOAD
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400219#endif
220
221/*
Ben Gardiner3d248d32010-10-14 17:26:29 -0400222 * Network & Ethernet Configuration
223 */
224#ifdef CONFIG_DRIVER_TI_EMAC
Ben Gardiner3d248d32010-10-14 17:26:29 -0400225#define CONFIG_MII
Ben Gardiner3d248d32010-10-14 17:26:29 -0400226#define CONFIG_BOOTP_DNS
227#define CONFIG_BOOTP_DNS2
228#define CONFIG_BOOTP_SEND_HOSTNAME
229#define CONFIG_NET_RETRY_COUNT 10
Ben Gardiner3d248d32010-10-14 17:26:29 -0400230#endif
231
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -0400232#ifdef CONFIG_USE_NOR
233#define CONFIG_ENV_IS_IN_FLASH
234#define CONFIG_FLASH_CFI_DRIVER
235#define CONFIG_SYS_FLASH_CFI
236#define CONFIG_SYS_FLASH_PROTECTION
237#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
238#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
239#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
240#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
241#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
242#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
243#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
244 + 3)
245#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
246#endif
247
Stefano Babicd73a8a12010-11-11 15:38:02 +0100248#ifdef CONFIG_USE_SPIFLASH
249#undef CONFIG_ENV_IS_IN_FLASH
250#undef CONFIG_ENV_IS_IN_NAND
251#define CONFIG_ENV_IS_IN_SPI_FLASH
252#define CONFIG_ENV_SIZE (64 << 10)
Peter Howard2a10f8b2014-12-17 12:14:36 +1100253#define CONFIG_ENV_OFFSET (512 << 10)
Stefano Babicd73a8a12010-11-11 15:38:02 +0100254#define CONFIG_ENV_SECT_SIZE (64 << 10)
255#define CONFIG_SYS_NO_FLASH
256#endif
257
Ben Gardiner3d248d32010-10-14 17:26:29 -0400258/*
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530259 * U-Boot general configuration
260 */
Peter Howard2a10f8b2014-12-17 12:14:36 +1100261#define CONFIG_SYS_GENERIC_BOARD
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400262#define CONFIG_MISC_INIT_R
Christian Rieschae5c77d2011-10-13 00:52:29 +0000263#define CONFIG_BOARD_EARLY_INIT_F
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530264#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Nagabhushana Netagunteac935e52011-09-03 22:18:59 -0400265#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530266#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
267#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
268#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
269#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
270#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
271#define CONFIG_VERSION_VARIABLE
272#define CONFIG_AUTO_COMPLETE
273#define CONFIG_SYS_HUSH_PARSER
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530274#define CONFIG_CMDLINE_EDITING
275#define CONFIG_SYS_LONGHELP
276#define CONFIG_CRC32_VERIFY
277#define CONFIG_MX_CYCLIC
Peter Howard2a10f8b2014-12-17 12:14:36 +1100278#define CONFIG_OF_LIBFDT
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530279
280/*
281 * Linux Information
282 */
Ben Gardiner59e0d612010-10-14 17:26:32 -0400283#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400284#define CONFIG_HWCONFIG /* enable hwconfig */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530285#define CONFIG_CMDLINE_TAG
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500286#define CONFIG_REVISION_TAG
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530287#define CONFIG_SETUP_MEMORY_TAGS
288#define CONFIG_BOOTARGS \
289 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
290#define CONFIG_BOOTDELAY 3
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400291#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530292
293/*
294 * U-Boot commands
295 */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530296#define CONFIG_CMD_ENV
297#define CONFIG_CMD_ASKENV
298#define CONFIG_CMD_DHCP
299#define CONFIG_CMD_DIAG
300#define CONFIG_CMD_MII
301#define CONFIG_CMD_PING
302#define CONFIG_CMD_SAVES
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530303
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000304#ifdef CONFIG_CMD_BDI
305#define CONFIG_CLOCKS
306#endif
307
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530308#ifndef CONFIG_DRIVER_TI_EMAC
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530309#undef CONFIG_CMD_DHCP
310#undef CONFIG_CMD_MII
311#undef CONFIG_CMD_PING
312#endif
313
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400314#ifdef CONFIG_USE_NAND
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400315#define CONFIG_CMD_NAND
Ben Gardiner771d0282010-10-14 17:26:27 -0400316
317#define CONFIG_CMD_MTDPARTS
318#define CONFIG_MTD_DEVICE
319#define CONFIG_MTD_PARTITIONS
320#define CONFIG_LZO
321#define CONFIG_RBTREE
322#define CONFIG_CMD_UBI
323#define CONFIG_CMD_UBIFS
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400324#endif
325
Stefano Babicd73a8a12010-11-11 15:38:02 +0100326#ifdef CONFIG_USE_SPIFLASH
Stefano Babicd73a8a12010-11-11 15:38:02 +0100327#define CONFIG_CMD_SPI
Stefano Babicd73a8a12010-11-11 15:38:02 +0100328#endif
329
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530330#if !defined(CONFIG_USE_NAND) && \
331 !defined(CONFIG_USE_NOR) && \
332 !defined(CONFIG_USE_SPIFLASH)
333#define CONFIG_ENV_IS_NOWHERE
334#define CONFIG_SYS_NO_FLASH
335#define CONFIG_ENV_SIZE (16 << 10)
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530336#undef CONFIG_CMD_ENV
337#endif
338
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000339/* SD/MMC configuration */
Rajashekhara, Sudhakar4a5edda2012-06-24 21:35:17 +0000340#ifndef CONFIG_USE_NOR
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000341#define CONFIG_MMC
342#define CONFIG_DAVINCI_MMC_SD1
343#define CONFIG_GENERIC_MMC
344#define CONFIG_DAVINCI_MMC
Rajashekhara, Sudhakar4a5edda2012-06-24 21:35:17 +0000345#endif
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000346
347/*
348 * Enable MMC commands only when
349 * MMC support is present
350 */
351#ifdef CONFIG_MMC
352#define CONFIG_DOS_PARTITION
353#define CONFIG_CMD_EXT2
354#define CONFIG_CMD_FAT
355#define CONFIG_CMD_MMC
356#endif
357
Lad, Prabhakar63777662012-06-24 21:35:23 +0000358#ifndef CONFIG_DIRECT_NOR_BOOT
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000359/* defines for SPL */
Tom Rini3f7f2412012-08-14 12:27:13 -0700360#define CONFIG_SPL_FRAMEWORK
361#define CONFIG_SPL_BOARD_INIT
362#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
363 CONFIG_SYS_MALLOC_LEN)
364#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
365#define CONFIG_SPL_SPI_SUPPORT
366#define CONFIG_SPL_SPI_FLASH_SUPPORT
367#define CONFIG_SPL_SPI_LOAD
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000368#define CONFIG_SPL_SERIAL_SUPPORT
369#define CONFIG_SPL_LIBCOMMON_SUPPORT
370#define CONFIG_SPL_LIBGENERIC_SUPPORT
Sughosh Ganu6b873dc2012-02-02 00:44:41 +0000371#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000372#define CONFIG_SPL_STACK 0x8001ff00
373#define CONFIG_SPL_TEXT_BASE 0x80000000
Albert ARIBAUDb7b5f1a2013-04-12 05:14:32 +0000374#define CONFIG_SPL_MAX_FOOTPRINT 32768
Christian Riesch532d5312014-05-07 10:16:28 +0200375#define CONFIG_SPL_PAD_TO 32768
Lad, Prabhakar63777662012-06-24 21:35:23 +0000376#endif
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000377
378/* Load U-Boot Image From MMC */
379#ifdef CONFIG_SPL_MMC_LOAD
380#define CONFIG_SPL_MMC_SUPPORT
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000381#define CONFIG_SPL_LIBDISK_SUPPORT
Tom Rini3f7f2412012-08-14 12:27:13 -0700382#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75
383#undef CONFIG_SPL_SPI_SUPPORT
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000384#undef CONFIG_SPL_SPI_LOAD
385#endif
386
Heiko Schocherab86f722010-09-17 13:10:42 +0200387/* additions for new relocation code, must added to all boards */
Heiko Schocherab86f722010-09-17 13:10:42 +0200388#define CONFIG_SYS_SDRAM_BASE 0xc0000000
Lad, Prabhakar63777662012-06-24 21:35:23 +0000389
390#ifdef CONFIG_DIRECT_NOR_BOOT
391#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
392#else
Heiko Schocherab86f722010-09-17 13:10:42 +0200393#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200394 GENERATED_GBL_DATA_SIZE)
Lad, Prabhakar63777662012-06-24 21:35:23 +0000395#endif /* CONFIG_DIRECT_NOR_BOOT */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530396#endif /* __CONFIG_H */