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wdenk2cbe5712004-10-10 17:05:18 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * 2004-2005 Gary Jennejohn <garyj@denx.de>
wdenk2cbe5712004-10-10 17:05:18 +00003 *
wdenk9d5028c2004-11-21 00:06:33 +00004 * Configuration settings for the CMC PU2 board.
wdenk2cbe5712004-10-10 17:05:18 +00005 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk45ea3fc2004-12-14 23:28:24 +000016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk2cbe5712004-10-10 17:05:18 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
wdenk2cbe5712004-10-10 17:05:18 +000028/* ARM asynchronous clock */
Wolfgang Denkdf3c7c82005-08-19 00:36:45 +020029#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
wdenk101e8df2005-04-04 12:08:28 +000030#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
wdenk2cbe5712004-10-10 17:05:18 +000031
32#define AT91_SLOW_CLOCK 32768 /* slow clock */
33
wdenka85f9f22005-04-06 13:52:31 +000034#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
35#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
wdenka85f9f22005-04-06 13:52:31 +000036#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
37#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
38#define USE_920T_MMU 1
39
wdenk2cbe5712004-10-10 17:05:18 +000040#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41#define CONFIG_SETUP_MEMORY_TAGS 1
42#define CONFIG_INITRD_TAG 1
43
wdenk8aa1a2d2005-04-04 12:44:11 +000044#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
wdenkef2807c2005-03-31 23:44:33 +000046/* flash */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010047#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
48#define CONFIG_SYS_MC_PUP_VAL 0x00000000
49#define CONFIG_SYS_MC_PUER_VAL 0x00000000
50#define CONFIG_SYS_MC_ASR_VAL 0x00000000
51#define CONFIG_SYS_MC_AASR_VAL 0x00000000
52#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
53#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
wdenkef2807c2005-03-31 23:44:33 +000054
55/* clocks */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010056#define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
57#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
58#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
wdenkef2807c2005-03-31 23:44:33 +000059
60/* sdram */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010061#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
62#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
63#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
64#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
65#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */
66#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
67#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
68#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
69#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
70#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
71#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
72#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
73#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
Jens Scharsig80523522008-11-18 10:48:46 +010074#else
75#define CONFIG_SKIP_RELOCATE_UBOOT
wdenk8aa1a2d2005-04-04 12:44:11 +000076#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenkef2807c2005-03-31 23:44:33 +000077
wdenk2cbe5712004-10-10 17:05:18 +000078/*
79 * Size of malloc() pool
80 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
82#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk2cbe5712004-10-10 17:05:18 +000083
wdenk45ea3fc2004-12-14 23:28:24 +000084#define CONFIG_BAUDRATE 9600
wdenk2cbe5712004-10-10 17:05:18 +000085
wdenk2cbe5712004-10-10 17:05:18 +000086/*
87 * Hardware drivers
88 */
89
90/* define one of these to choose the DBGU, USART0 or USART1 as console */
91#undef CONFIG_DBGU
wdenk9d5028c2004-11-21 00:06:33 +000092#define CONFIG_USART0
93#undef CONFIG_USART1
wdenk2cbe5712004-10-10 17:05:18 +000094
95#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
96
97#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
98
wdenk9d5028c2004-11-21 00:06:33 +000099#define CONFIG_HARD_I2C
wdenk2cbe5712004-10-10 17:05:18 +0000100
101#ifdef CONFIG_HARD_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_I2C_SPEED 0 /* not used */
103#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
wdenk45ea3fc2004-12-14 23:28:24 +0000104#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_I2C_RTC_ADDR 0x32
106#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
107#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
108#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
Jon Loeliger37e4f242007-07-04 22:31:56 -0500109#else
110#define CONFIG_TIMESTAMP
wdenk2cbe5712004-10-10 17:05:18 +0000111#endif
wdenked54e622004-11-24 23:35:19 +0000112/* still about 20 kB free with this defined */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LONGHELP
wdenk2cbe5712004-10-10 17:05:18 +0000114
Wolfgang Denk1ac7e172006-06-16 16:43:33 +0200115#define CONFIG_BOOTDELAY 1
wdenk2cbe5712004-10-10 17:05:18 +0000116
wdenk2cbe5712004-10-10 17:05:18 +0000117
Jon Loeliger37e4f242007-07-04 22:31:56 -0500118/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500119 * BOOTP options
120 */
121#define CONFIG_BOOTP_BOOTFILESIZE
122#define CONFIG_BOOTP_BOOTPATH
123#define CONFIG_BOOTP_GATEWAY
124#define CONFIG_BOOTP_HOSTNAME
125
126
127/*
Jon Loeliger37e4f242007-07-04 22:31:56 -0500128 * Command line configuration.
129 */
130#include <config_cmd_default.h>
131
132#define CONFIG_CMD_DHCP
133#define CONFIG_CMD_NFS
134#define CONFIG_CMD_SNTP
135
136#undef CONFIG_CMD_FPGA
137#undef CONFIG_CMD_MISC
138
139#if defined(CONFIG_HARD_I2C)
140 #define CONFIG_CMD_DATE
141 #define CONFIG_CMD_EEPROM
142 #define CONFIG_CMD_I2C
143#endif
144
145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_LONGHELP
wdenk2cbe5712004-10-10 17:05:18 +0000147
wdenk45ea3fc2004-12-14 23:28:24 +0000148#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
149#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
wdenk2cbe5712004-10-10 17:05:18 +0000150
wdenk45ea3fc2004-12-14 23:28:24 +0000151#define CONFIG_NR_DRAM_BANKS 1
152#define PHYS_SDRAM 0x20000000
Ladislav Michl2c5260f2007-12-06 23:24:57 +0100153#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
wdenk2cbe5712004-10-10 17:05:18 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
156#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
wdenk2cbe5712004-10-10 17:05:18 +0000157
158#define CONFIG_DRIVER_ETHER
159#define CONFIG_NET_RETRY_COUNT 20
160#define CONFIG_AT91C_USE_RMII
161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
163#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
164#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
165#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
166#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
wdenk2cbe5712004-10-10 17:05:18 +0000167
168#define PHYS_FLASH_1 0x10000000
wdenk9d5028c2004-11-21 00:06:33 +0000169#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
172#define CONFIG_SYS_MAX_FLASH_BANKS 1
173#define CONFIG_SYS_MAX_FLASH_SECT 256
174#define CONFIG_SYS_FLASH_ERASE_TOUT (11 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
175#define CONFIG_SYS_FLASH_WRITE_TOUT ( 2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk2cbe5712004-10-10 17:05:18 +0000176
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200177#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200178#define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */
179#define CONFIG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */
180#define CONFIG_ENV_SIZE (16 << 10) /* Use only 16 kB */
wdenk2cbe5712004-10-10 17:05:18 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
wdenk2cbe5712004-10-10 17:05:18 +0000183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
wdenk2cbe5712004-10-10 17:05:18 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
187#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
188#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
189#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
wdenk2cbe5712004-10-10 17:05:18 +0000190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_HZ 1000
192#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
wdenk59acc292005-04-03 14:18:51 +0000193 /* AT91C_TC_TIMER_DIV1_CLOCK */
wdenk2cbe5712004-10-10 17:05:18 +0000194
195#define CONFIG_STACKSIZE (32*1024) /* regular stack */
196
197#ifdef CONFIG_USE_IRQ
198#error CONFIG_USE_IRQ not supported
199#endif
200
wdenk3dd7f0f2005-04-04 23:43:44 +0000201#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100202 "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
wdenk3dd7f0f2005-04-04 23:43:44 +0000203 "addmtd;bootm\0" \
204 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100205 "nfsroot=${serverip}:${rootpath}\0" \
206 "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
wdenk3dd7f0f2005-04-04 23:43:44 +0000207 "addcons addmtd; bootm\0" \
208 "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
209 "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100210 "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
211 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
212 "${hostname}::off\0" \
213 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
214 "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
wdenk3dd7f0f2005-04-04 23:43:44 +0000215 "64k(environment),768k(linux),4096k(root),-\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100216 "load=tftp ${loadaddr} ${loadfile}\0" \
wdenk3dd7f0f2005-04-04 23:43:44 +0000217 "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100218 "cp.b ${loadaddr} 10000000 ${filesize};" \
wdenk3dd7f0f2005-04-04 23:43:44 +0000219 "protect on 10000000 1001ffff\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100220 "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
221 "cp.b ${loadaddr} 10030000 ${filesize}\0" \
222 "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
223 "cp.b ${loadaddr} 100f0000 ${filesize}\0" \
224 "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
225 "cp.b ${loadaddr} 104f0000 ${filesize}\0" \
wdenk3dd7f0f2005-04-04 23:43:44 +0000226 "cramfsimage=cramfs_cmc-pu2.img\0" \
227 "jffsimage=jffs2_cmc-pu2.img\0" \
228 "loadfile=u-boot_cmc-pu2.bin\0" \
229 "bootfile=uImage_cmc-pu2\0" \
230 "loadaddr=0x20800000\0" \
231 "hostname=CMC-TC-PU2\0" \
232 "bootcmd=run dhcp_start;run flash_cramfs\0" \
233 "autoload=n\0" \
234 "dhcp_start=echo no DHCP\0" \
235 "ipaddr=192.168.0.190\0"
wdenk45ea3fc2004-12-14 23:28:24 +0000236#endif /* __CONFIG_H */