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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenkd4ca31c2004-01-02 14:00:00 +00002 * (C) Copyright 2000-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
wdenkd4ca31c2004-01-02 14:00:00 +000024#if 0
25#define DEBUG
26#endif
wdenk73a8b272003-06-05 19:27:42 +000027
wdenkc6097192002-11-03 00:24:07 +000028#include <common.h>
29#include <mpc8xx.h>
wdenk71f95112003-06-15 22:40:42 +000030#include <environment.h>
wdenkc6097192002-11-03 00:24:07 +000031
wdenke9132ea2004-04-24 23:23:30 +000032#include <asm/processor.h>
33
Wolfgang Denkd87080b2006-03-31 18:32:53 +020034DECLARE_GLOBAL_DATA_PTR;
35
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020036#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
37 && !defined(CONFIG_TQM885D)
wdenke9132ea2004-04-24 23:23:30 +000038# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
39# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
40 OR_SCY_2_CLK | OR_EHTR | OR_BI)
41# endif
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020042#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
wdenke9132ea2004-04-24 23:23:30 +000043
wdenkc6097192002-11-03 00:24:07 +000044#ifndef CFG_ENV_ADDR
45#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
46#endif
47
48flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
49
50/*-----------------------------------------------------------------------
51 * Functions
52 */
53static ulong flash_get_size (vu_long *addr, flash_info_t *info);
54static int write_word (flash_info_t *info, ulong dest, ulong data);
55
56/*-----------------------------------------------------------------------
57 */
58
59unsigned long flash_init (void)
60{
61 volatile immap_t *immap = (immap_t *)CFG_IMMR;
62 volatile memctl8xx_t *memctl = &immap->im_memctl;
63 unsigned long size_b0, size_b1;
64 int i;
65
wdenke9132ea2004-04-24 23:23:30 +000066#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
67 int scy, trlx, flash_or_timing, clk_diff;
68
wdenke9132ea2004-04-24 23:23:30 +000069 scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
70 if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
71 trlx = OR_TRLX;
72 scy *= 2;
73 } else
74 trlx = 0;
75
76 /* We assume that each 10MHz of bus clock require 1-clk SCY
77 * adjustment.
78 */
79 clk_diff = (gd->bus_clk / 1000000) - 50;
80
81 /* We need proper rounding here. This is what the "+5" and "-5"
82 * are here for.
83 */
84 if (clk_diff >= 0)
85 scy += (clk_diff + 5) / 10;
86 else
87 scy += (clk_diff - 5) / 10;
88
89 /* For bus frequencies above 50MHz, we want to use relaxed timing
90 * (OR_TRLX).
91 */
92 if (gd->bus_clk >= 50000000)
93 trlx = OR_TRLX;
94 else
95 trlx = 0;
96
97 if (trlx)
98 scy /= 2;
99
100 if (scy > 0xf)
101 scy = 0xf;
102 if (scy < 1)
103 scy = 1;
104
105 flash_or_timing = (scy << 4) | trlx |
106 (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
107#endif
wdenkc6097192002-11-03 00:24:07 +0000108 /* Init: no FLASHes known */
109 for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
110 flash_info[i].flash_id = FLASH_UNKNOWN;
111 }
112
113 /* Static FLASH Bank configuration here - FIXME XXX */
114
wdenk73a8b272003-06-05 19:27:42 +0000115 debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
116
wdenkc6097192002-11-03 00:24:07 +0000117 size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
118
wdenk73a8b272003-06-05 19:27:42 +0000119 debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
120
wdenkc6097192002-11-03 00:24:07 +0000121 if (flash_info[0].flash_id == FLASH_UNKNOWN) {
122 printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
123 size_b0, size_b0<<20);
124 }
125
126 size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
127
wdenk73a8b272003-06-05 19:27:42 +0000128 debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
129
wdenkc6097192002-11-03 00:24:07 +0000130 if (size_b1 > size_b0) {
131 printf ("## ERROR: "
132 "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
133 size_b1, size_b1<<20,
134 size_b0, size_b0<<20
135 );
136 flash_info[0].flash_id = FLASH_UNKNOWN;
137 flash_info[1].flash_id = FLASH_UNKNOWN;
138 flash_info[0].sector_count = -1;
139 flash_info[1].sector_count = -1;
140 flash_info[0].size = 0;
141 flash_info[1].size = 0;
142 return (0);
143 }
144
wdenk73a8b272003-06-05 19:27:42 +0000145 debug ("## Before remap: "
146 "BR0: 0x%08x OR0: 0x%08x "
147 "BR1: 0x%08x OR1: 0x%08x\n",
148 memctl->memc_br0, memctl->memc_or0,
149 memctl->memc_br1, memctl->memc_or1);
150
wdenkc6097192002-11-03 00:24:07 +0000151 /* Remap FLASH according to real size */
wdenke9132ea2004-04-24 23:23:30 +0000152#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
wdenkc6097192002-11-03 00:24:07 +0000153 memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
wdenke9132ea2004-04-24 23:23:30 +0000154#else
155 memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
156#endif
wdenkc6097192002-11-03 00:24:07 +0000157 memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
158
wdenk73a8b272003-06-05 19:27:42 +0000159 debug ("## BR0: 0x%08x OR0: 0x%08x\n",
160 memctl->memc_br0, memctl->memc_or0);
161
wdenkc6097192002-11-03 00:24:07 +0000162 /* Re-do sizing to get full correct info */
163 size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
164
165#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
166 /* monitor protection ON by default */
wdenk71f95112003-06-15 22:40:42 +0000167 debug ("Protect monitor: %08lx ... %08lx\n",
168 (ulong)CFG_MONITOR_BASE,
169 (ulong)CFG_MONITOR_BASE + monitor_flash_len - 1);
170
wdenkc6097192002-11-03 00:24:07 +0000171 flash_protect(FLAG_PROTECT_SET,
172 CFG_MONITOR_BASE,
wdenk71f95112003-06-15 22:40:42 +0000173 CFG_MONITOR_BASE + monitor_flash_len - 1,
wdenkc6097192002-11-03 00:24:07 +0000174 &flash_info[0]);
175#endif
176
177#ifdef CFG_ENV_IS_IN_FLASH
178 /* ENV protection ON by default */
wdenk71f95112003-06-15 22:40:42 +0000179# ifdef CFG_ENV_ADDR_REDUND
wdenke0ac62d2003-08-17 18:55:18 +0000180 debug ("Protect primary environment: %08lx ... %08lx\n",
wdenk71f95112003-06-15 22:40:42 +0000181 (ulong)CFG_ENV_ADDR,
182 (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
wdenke0ac62d2003-08-17 18:55:18 +0000183# else
184 debug ("Protect environment: %08lx ... %08lx\n",
185 (ulong)CFG_ENV_ADDR,
186 (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
187# endif
wdenk71f95112003-06-15 22:40:42 +0000188
wdenkc6097192002-11-03 00:24:07 +0000189 flash_protect(FLAG_PROTECT_SET,
190 CFG_ENV_ADDR,
wdenk71f95112003-06-15 22:40:42 +0000191 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
192 &flash_info[0]);
193#endif
194
195#ifdef CFG_ENV_ADDR_REDUND
196 debug ("Protect redundand environment: %08lx ... %08lx\n",
197 (ulong)CFG_ENV_ADDR_REDUND,
198 (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1);
199
200 flash_protect(FLAG_PROTECT_SET,
201 CFG_ENV_ADDR_REDUND,
202 CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
wdenkc6097192002-11-03 00:24:07 +0000203 &flash_info[0]);
204#endif
205
206 if (size_b1) {
wdenke9132ea2004-04-24 23:23:30 +0000207#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
wdenkc6097192002-11-03 00:24:07 +0000208 memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
wdenke9132ea2004-04-24 23:23:30 +0000209#else
210 memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000);
211#endif
wdenkc6097192002-11-03 00:24:07 +0000212 memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
213 BR_MS_GPCM | BR_V;
214
wdenk73a8b272003-06-05 19:27:42 +0000215 debug ("## BR1: 0x%08x OR1: 0x%08x\n",
216 memctl->memc_br1, memctl->memc_or1);
217
wdenkc6097192002-11-03 00:24:07 +0000218 /* Re-do sizing to get full correct info */
219 size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
220 &flash_info[1]);
221
222#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
223 /* monitor protection ON by default */
224 flash_protect(FLAG_PROTECT_SET,
225 CFG_MONITOR_BASE,
wdenk3b57fe02003-05-30 12:48:29 +0000226 CFG_MONITOR_BASE+monitor_flash_len-1,
wdenkc6097192002-11-03 00:24:07 +0000227 &flash_info[1]);
228#endif
229
230#ifdef CFG_ENV_IS_IN_FLASH
231 /* ENV protection ON by default */
232 flash_protect(FLAG_PROTECT_SET,
233 CFG_ENV_ADDR,
234 CFG_ENV_ADDR+CFG_ENV_SIZE-1,
235 &flash_info[1]);
236#endif
237 } else {
238 memctl->memc_br1 = 0; /* invalidate bank */
239
240 flash_info[1].flash_id = FLASH_UNKNOWN;
241 flash_info[1].sector_count = -1;
wdenk73a8b272003-06-05 19:27:42 +0000242 flash_info[1].size = 0;
243
244 debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
245 memctl->memc_br1, memctl->memc_or1);
wdenkc6097192002-11-03 00:24:07 +0000246 }
247
wdenk73a8b272003-06-05 19:27:42 +0000248 debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
249
wdenkc6097192002-11-03 00:24:07 +0000250 flash_info[0].size = size_b0;
251 flash_info[1].size = size_b1;
252
253 return (size_b0 + size_b1);
254}
255
256/*-----------------------------------------------------------------------
257 */
258void flash_print_info (flash_info_t *info)
259{
260 int i;
261
262 if (info->flash_id == FLASH_UNKNOWN) {
263 printf ("missing or unknown FLASH type\n");
264 return;
265 }
266
267 switch (info->flash_id & FLASH_VENDMASK) {
268 case FLASH_MAN_AMD: printf ("AMD "); break;
269 case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
270 default: printf ("Unknown Vendor "); break;
271 }
272
273 switch (info->flash_id & FLASH_TYPEMASK) {
wdenk71f95112003-06-15 22:40:42 +0000274#ifdef CONFIG_TQM8xxM /* mirror bit flash */
275 case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
276 break;
wdenkf12e5682003-07-07 20:07:54 +0000277 case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
278 break;
279 case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
280 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000281 case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
282 break;
wdenk71f95112003-06-15 22:40:42 +0000283# else /* ! TQM8xxM */
wdenkc6097192002-11-03 00:24:07 +0000284 case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
285 break;
286 case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
287 break;
288 case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
289 break;
290 case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
291 break;
wdenkc6097192002-11-03 00:24:07 +0000292 case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
293 break;
294 case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
295 break;
wdenk71f95112003-06-15 22:40:42 +0000296#endif /* TQM8xxM */
wdenkf12e5682003-07-07 20:07:54 +0000297 case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
298 break;
299 case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
300 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000301 case FLASH_AMDL163B: printf ("AM29DL163B (16 Mbit, bottom boot sect)\n");
302 break;
wdenkc6097192002-11-03 00:24:07 +0000303 default: printf ("Unknown Chip Type\n");
304 break;
305 }
306
307 printf (" Size: %ld MB in %d Sectors\n",
308 info->size >> 20, info->sector_count);
309
310 printf (" Sector Start Addresses:");
311 for (i=0; i<info->sector_count; ++i) {
312 if ((i % 5) == 0)
313 printf ("\n ");
314 printf (" %08lX%s",
315 info->start[i],
316 info->protect[i] ? " (RO)" : " "
317 );
318 }
319 printf ("\n");
320 return;
321}
322
323/*-----------------------------------------------------------------------
324 */
325
326
327/*-----------------------------------------------------------------------
328 */
329
330/*
331 * The following code cannot be run from FLASH!
332 */
333
334static ulong flash_get_size (vu_long *addr, flash_info_t *info)
335{
336 short i;
337 ulong value;
338 ulong base = (ulong)addr;
339
340 /* Write auto select command: read Manufacturer ID */
341 addr[0x0555] = 0x00AA00AA;
342 addr[0x02AA] = 0x00550055;
343 addr[0x0555] = 0x00900090;
344
345 value = addr[0];
346
wdenk73a8b272003-06-05 19:27:42 +0000347 debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
348
wdenkc6097192002-11-03 00:24:07 +0000349 switch (value) {
350 case AMD_MANUFACT:
wdenkd4ca31c2004-01-02 14:00:00 +0000351 debug ("Manufacturer: AMD\n");
wdenkc6097192002-11-03 00:24:07 +0000352 info->flash_id = FLASH_MAN_AMD;
353 break;
354 case FUJ_MANUFACT:
wdenkd4ca31c2004-01-02 14:00:00 +0000355 debug ("Manufacturer: FUJITSU\n");
wdenkc6097192002-11-03 00:24:07 +0000356 info->flash_id = FLASH_MAN_FUJ;
357 break;
358 default:
wdenkd4ca31c2004-01-02 14:00:00 +0000359 debug ("Manufacturer: *** unknown ***\n");
wdenkc6097192002-11-03 00:24:07 +0000360 info->flash_id = FLASH_UNKNOWN;
361 info->sector_count = 0;
362 info->size = 0;
363 return (0); /* no or unknown flash */
364 }
365
366 value = addr[1]; /* device ID */
367
wdenk73a8b272003-06-05 19:27:42 +0000368 debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
369
wdenkc6097192002-11-03 00:24:07 +0000370 switch (value) {
wdenk71f95112003-06-15 22:40:42 +0000371#ifdef CONFIG_TQM8xxM /* mirror bit flash */
372 case AMD_ID_MIRROR:
wdenkd4ca31c2004-01-02 14:00:00 +0000373 debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
374 addr[14], addr[15]);
wdenkf12e5682003-07-07 20:07:54 +0000375 /* Special case for AMLV320MH/L */
376 if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
wdenkd4ca31c2004-01-02 14:00:00 +0000377 (addr[15] & 0x00ff00ff) == 0x00000000) {
378 debug ("Chip: AMLV320MH/L\n");
wdenkf12e5682003-07-07 20:07:54 +0000379 info->flash_id += FLASH_AMLV320U;
380 info->sector_count = 64;
wdenkd4ca31c2004-01-02 14:00:00 +0000381 info->size = 0x00800000; /* => 8 MB */
wdenkf12e5682003-07-07 20:07:54 +0000382 break;
wdenk945af8d2003-07-16 21:53:01 +0000383 }
wdenk71f95112003-06-15 22:40:42 +0000384 switch(addr[14]) {
385 case AMD_ID_LV128U_2:
386 if (addr[15] != AMD_ID_LV128U_3) {
wdenkd4ca31c2004-01-02 14:00:00 +0000387 debug ("Chip: AMLV128U -> unknown\n");
wdenk71f95112003-06-15 22:40:42 +0000388 info->flash_id = FLASH_UNKNOWN;
wdenkd4ca31c2004-01-02 14:00:00 +0000389 } else {
390 debug ("Chip: AMLV128U\n");
wdenk71f95112003-06-15 22:40:42 +0000391 info->flash_id += FLASH_AMLV128U;
392 info->sector_count = 256;
393 info->size = 0x02000000;
394 }
wdenkd4ca31c2004-01-02 14:00:00 +0000395 break; /* => 32 MB */
wdenkf12e5682003-07-07 20:07:54 +0000396 case AMD_ID_LV640U_2:
397 if (addr[15] != AMD_ID_LV640U_3) {
wdenkd4ca31c2004-01-02 14:00:00 +0000398 debug ("Chip: AMLV640U -> unknown\n");
wdenkf12e5682003-07-07 20:07:54 +0000399 info->flash_id = FLASH_UNKNOWN;
wdenkd4ca31c2004-01-02 14:00:00 +0000400 } else {
401 debug ("Chip: AMLV640U\n");
wdenkf12e5682003-07-07 20:07:54 +0000402 info->flash_id += FLASH_AMLV640U;
403 info->sector_count = 128;
404 info->size = 0x01000000;
405 }
wdenkd4ca31c2004-01-02 14:00:00 +0000406 break; /* => 16 MB */
407 case AMD_ID_LV320B_2:
408 if (addr[15] != AMD_ID_LV320B_3) {
409 debug ("Chip: AMLV320B -> unknown\n");
410 info->flash_id = FLASH_UNKNOWN;
411 } else {
412 debug ("Chip: AMLV320B\n");
413 info->flash_id += FLASH_AMLV320B;
414 info->sector_count = 71;
415 info->size = 0x00800000;
416 }
417 break; /* => 8 MB */
wdenk71f95112003-06-15 22:40:42 +0000418 default:
wdenkd4ca31c2004-01-02 14:00:00 +0000419 debug ("Chip: *** unknown ***\n");
wdenk71f95112003-06-15 22:40:42 +0000420 info->flash_id = FLASH_UNKNOWN;
421 break;
422 }
423 break;
424# else /* ! TQM8xxM */
wdenkc6097192002-11-03 00:24:07 +0000425 case AMD_ID_LV400T:
426 info->flash_id += FLASH_AM400T;
427 info->sector_count = 11;
428 info->size = 0x00100000;
wdenkd4ca31c2004-01-02 14:00:00 +0000429 break; /* => 1 MB */
wdenkc6097192002-11-03 00:24:07 +0000430
431 case AMD_ID_LV400B:
432 info->flash_id += FLASH_AM400B;
433 info->sector_count = 11;
434 info->size = 0x00100000;
wdenkd4ca31c2004-01-02 14:00:00 +0000435 break; /* => 1 MB */
wdenkc6097192002-11-03 00:24:07 +0000436
437 case AMD_ID_LV800T:
438 info->flash_id += FLASH_AM800T;
439 info->sector_count = 19;
440 info->size = 0x00200000;
wdenkd4ca31c2004-01-02 14:00:00 +0000441 break; /* => 2 MB */
wdenkc6097192002-11-03 00:24:07 +0000442
443 case AMD_ID_LV800B:
444 info->flash_id += FLASH_AM800B;
445 info->sector_count = 19;
446 info->size = 0x00200000;
wdenkd4ca31c2004-01-02 14:00:00 +0000447 break; /* => 2 MB */
wdenkc6097192002-11-03 00:24:07 +0000448
wdenkc6097192002-11-03 00:24:07 +0000449 case AMD_ID_LV320T:
450 info->flash_id += FLASH_AM320T;
451 info->sector_count = 71;
452 info->size = 0x00800000;
wdenkd4ca31c2004-01-02 14:00:00 +0000453 break; /* => 8 MB */
wdenkc6097192002-11-03 00:24:07 +0000454
455 case AMD_ID_LV320B:
456 info->flash_id += FLASH_AM320B;
457 info->sector_count = 71;
458 info->size = 0x00800000;
wdenkd4ca31c2004-01-02 14:00:00 +0000459 break; /* => 8 MB */
wdenk71f95112003-06-15 22:40:42 +0000460#endif /* TQM8xxM */
wdenkf12e5682003-07-07 20:07:54 +0000461
462 case AMD_ID_LV160T:
463 info->flash_id += FLASH_AM160T;
464 info->sector_count = 35;
465 info->size = 0x00400000;
wdenkd4ca31c2004-01-02 14:00:00 +0000466 break; /* => 4 MB */
wdenkf12e5682003-07-07 20:07:54 +0000467
468 case AMD_ID_LV160B:
469 info->flash_id += FLASH_AM160B;
470 info->sector_count = 35;
471 info->size = 0x00400000;
wdenkd4ca31c2004-01-02 14:00:00 +0000472 break; /* => 4 MB */
473
474 case AMD_ID_DL163B:
475 info->flash_id += FLASH_AMDL163B;
476 info->sector_count = 39;
477 info->size = 0x00400000;
478 break; /* => 4 MB */
wdenkf12e5682003-07-07 20:07:54 +0000479
wdenkc6097192002-11-03 00:24:07 +0000480 default:
481 info->flash_id = FLASH_UNKNOWN;
482 return (0); /* => no or unknown flash */
483 }
484
485 /* set up sector start address table */
486 switch (value) {
wdenk71f95112003-06-15 22:40:42 +0000487#ifdef CONFIG_TQM8xxM /* mirror bit flash */
488 case AMD_ID_MIRROR:
489 switch (info->flash_id & FLASH_TYPEMASK) {
490 /* only known types here - no default */
491 case FLASH_AMLV128U:
wdenkf12e5682003-07-07 20:07:54 +0000492 case FLASH_AMLV640U:
493 case FLASH_AMLV320U:
wdenk71f95112003-06-15 22:40:42 +0000494 for (i = 0; i < info->sector_count; i++) {
495 info->start[i] = base;
496 base += 0x20000;
497 }
498 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000499 case FLASH_AMLV320B:
500 for (i = 0; i < info->sector_count; i++) {
501 info->start[i] = base;
502 /*
503 * The first 8 sectors are 8 kB,
504 * all the other ones are 64 kB
505 */
506 base += (i < 8)
507 ? 2 * ( 8 << 10)
508 : 2 * (64 << 10);
509 }
510 break;
wdenk71f95112003-06-15 22:40:42 +0000511 }
512 break;
513# else /* ! TQM8xxM */
wdenkc6097192002-11-03 00:24:07 +0000514 case AMD_ID_LV400B:
515 case AMD_ID_LV800B:
wdenkc6097192002-11-03 00:24:07 +0000516 /* set sector offsets for bottom boot block type */
517 info->start[0] = base + 0x00000000;
518 info->start[1] = base + 0x00008000;
519 info->start[2] = base + 0x0000C000;
520 info->start[3] = base + 0x00010000;
521 for (i = 4; i < info->sector_count; i++) {
522 info->start[i] = base + (i * 0x00020000) - 0x00060000;
523 }
524 break;
525 case AMD_ID_LV400T:
526 case AMD_ID_LV800T:
wdenkc6097192002-11-03 00:24:07 +0000527 /* set sector offsets for top boot block type */
528 i = info->sector_count - 1;
529 info->start[i--] = base + info->size - 0x00008000;
530 info->start[i--] = base + info->size - 0x0000C000;
531 info->start[i--] = base + info->size - 0x00010000;
532 for (; i >= 0; i--) {
533 info->start[i] = base + i * 0x00020000;
534 }
535 break;
536 case AMD_ID_LV320B:
537 for (i = 0; i < info->sector_count; i++) {
538 info->start[i] = base;
539 /*
540 * The first 8 sectors are 8 kB,
541 * all the other ones are 64 kB
542 */
543 base += (i < 8)
544 ? 2 * ( 8 << 10)
545 : 2 * (64 << 10);
546 }
547 break;
548 case AMD_ID_LV320T:
549 for (i = 0; i < info->sector_count; i++) {
550 info->start[i] = base;
551 /*
552 * The last 8 sectors are 8 kB,
553 * all the other ones are 64 kB
554 */
555 base += (i < (info->sector_count - 8))
556 ? 2 * (64 << 10)
557 : 2 * ( 8 << 10);
558 }
559 break;
wdenk71f95112003-06-15 22:40:42 +0000560#endif /* TQM8xxM */
wdenkf12e5682003-07-07 20:07:54 +0000561 case AMD_ID_LV160B:
562 /* set sector offsets for bottom boot block type */
563 info->start[0] = base + 0x00000000;
564 info->start[1] = base + 0x00008000;
565 info->start[2] = base + 0x0000C000;
566 info->start[3] = base + 0x00010000;
567 for (i = 4; i < info->sector_count; i++) {
568 info->start[i] = base + (i * 0x00020000) - 0x00060000;
569 }
570 break;
571 case AMD_ID_LV160T:
572 /* set sector offsets for top boot block type */
573 i = info->sector_count - 1;
574 info->start[i--] = base + info->size - 0x00008000;
575 info->start[i--] = base + info->size - 0x0000C000;
576 info->start[i--] = base + info->size - 0x00010000;
577 for (; i >= 0; i--) {
578 info->start[i] = base + i * 0x00020000;
579 }
580 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000581 case AMD_ID_DL163B:
582 for (i = 0; i < info->sector_count; i++) {
583 info->start[i] = base;
584 /*
585 * The first 8 sectors are 8 kB,
586 * all the other ones are 64 kB
587 */
588 base += (i < 8)
589 ? 2 * ( 8 << 10)
590 : 2 * (64 << 10);
591 }
592 break;
wdenkc6097192002-11-03 00:24:07 +0000593 default:
594 return (0);
595 break;
596 }
597
wdenkd4ca31c2004-01-02 14:00:00 +0000598#if 0
wdenkc6097192002-11-03 00:24:07 +0000599 /* check for protected sectors */
600 for (i = 0; i < info->sector_count; i++) {
601 /* read sector protection at sector address, (A7 .. A0) = 0x02 */
602 /* D0 = 1 if protected */
603 addr = (volatile unsigned long *)(info->start[i]);
604 info->protect[i] = addr[2] & 1;
605 }
wdenkd4ca31c2004-01-02 14:00:00 +0000606#endif
wdenkc6097192002-11-03 00:24:07 +0000607
608 /*
609 * Prevent writes to uninitialized FLASH.
610 */
611 if (info->flash_id != FLASH_UNKNOWN) {
612 addr = (volatile unsigned long *)info->start[0];
613
614 *addr = 0x00F000F0; /* reset bank */
615 }
616
617 return (info->size);
618}
619
620
621/*-----------------------------------------------------------------------
622 */
623
624int flash_erase (flash_info_t *info, int s_first, int s_last)
625{
626 vu_long *addr = (vu_long*)(info->start[0]);
627 int flag, prot, sect, l_sect;
628 ulong start, now, last;
629
wdenk73a8b272003-06-05 19:27:42 +0000630 debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
631
wdenkc6097192002-11-03 00:24:07 +0000632 if ((s_first < 0) || (s_first > s_last)) {
633 if (info->flash_id == FLASH_UNKNOWN) {
634 printf ("- missing\n");
635 } else {
636 printf ("- no sectors to erase\n");
637 }
638 return 1;
639 }
640
641 if ((info->flash_id == FLASH_UNKNOWN) ||
642 (info->flash_id > FLASH_AMD_COMP)) {
643 printf ("Can't erase unknown flash type %08lx - aborted\n",
644 info->flash_id);
645 return 1;
646 }
647
648 prot = 0;
649 for (sect=s_first; sect<=s_last; ++sect) {
650 if (info->protect[sect]) {
651 prot++;
652 }
653 }
654
655 if (prot) {
656 printf ("- Warning: %d protected sectors will not be erased!\n",
657 prot);
658 } else {
659 printf ("\n");
660 }
661
662 l_sect = -1;
663
664 /* Disable interrupts which might cause a timeout here */
665 flag = disable_interrupts();
666
667 addr[0x0555] = 0x00AA00AA;
668 addr[0x02AA] = 0x00550055;
669 addr[0x0555] = 0x00800080;
670 addr[0x0555] = 0x00AA00AA;
671 addr[0x02AA] = 0x00550055;
672
673 /* Start erase on unprotected sectors */
674 for (sect = s_first; sect<=s_last; sect++) {
675 if (info->protect[sect] == 0) { /* not protected */
676 addr = (vu_long*)(info->start[sect]);
677 addr[0] = 0x00300030;
678 l_sect = sect;
679 }
680 }
681
682 /* re-enable interrupts if necessary */
683 if (flag)
684 enable_interrupts();
685
686 /* wait at least 80us - let's wait 1 ms */
687 udelay (1000);
688
689 /*
690 * We wait for the last triggered sector
691 */
692 if (l_sect < 0)
693 goto DONE;
694
695 start = get_timer (0);
696 last = start;
697 addr = (vu_long*)(info->start[l_sect]);
698 while ((addr[0] & 0x00800080) != 0x00800080) {
699 if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
700 printf ("Timeout\n");
701 return 1;
702 }
703 /* show that we're waiting */
704 if ((now - last) > 1000) { /* every second */
705 putc ('.');
706 last = now;
707 }
708 }
709
710DONE:
711 /* reset to read mode */
712 addr = (volatile unsigned long *)info->start[0];
713 addr[0] = 0x00F000F0; /* reset bank */
714
715 printf (" done\n");
716 return 0;
717}
718
719/*-----------------------------------------------------------------------
720 * Copy memory to flash, returns:
721 * 0 - OK
722 * 1 - write timeout
723 * 2 - Flash not erased
724 */
725
726int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
727{
728 ulong cp, wp, data;
729 int i, l, rc;
730
731 wp = (addr & ~3); /* get lower word aligned address */
732
733 /*
734 * handle unaligned start bytes
735 */
736 if ((l = addr - wp) != 0) {
737 data = 0;
738 for (i=0, cp=wp; i<l; ++i, ++cp) {
739 data = (data << 8) | (*(uchar *)cp);
740 }
741 for (; i<4 && cnt>0; ++i) {
742 data = (data << 8) | *src++;
743 --cnt;
744 ++cp;
745 }
746 for (; cnt==0 && i<4; ++i, ++cp) {
747 data = (data << 8) | (*(uchar *)cp);
748 }
749
750 if ((rc = write_word(info, wp, data)) != 0) {
751 return (rc);
752 }
753 wp += 4;
754 }
755
756 /*
757 * handle word aligned part
758 */
759 while (cnt >= 4) {
760 data = 0;
761 for (i=0; i<4; ++i) {
762 data = (data << 8) | *src++;
763 }
764 if ((rc = write_word(info, wp, data)) != 0) {
765 return (rc);
766 }
767 wp += 4;
768 cnt -= 4;
769 }
770
771 if (cnt == 0) {
772 return (0);
773 }
774
775 /*
776 * handle unaligned tail bytes
777 */
778 data = 0;
779 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
780 data = (data << 8) | *src++;
781 --cnt;
782 }
783 for (; i<4; ++i, ++cp) {
784 data = (data << 8) | (*(uchar *)cp);
785 }
786
787 return (write_word(info, wp, data));
788}
789
790/*-----------------------------------------------------------------------
791 * Write a word to Flash, returns:
792 * 0 - OK
793 * 1 - write timeout
794 * 2 - Flash not erased
795 */
796static int write_word (flash_info_t *info, ulong dest, ulong data)
797{
798 vu_long *addr = (vu_long*)(info->start[0]);
799 ulong start;
800 int flag;
801
802 /* Check if Flash is (sufficiently) erased */
803 if ((*((vu_long *)dest) & data) != data) {
804 return (2);
805 }
806 /* Disable interrupts which might cause a timeout here */
807 flag = disable_interrupts();
808
809 addr[0x0555] = 0x00AA00AA;
810 addr[0x02AA] = 0x00550055;
811 addr[0x0555] = 0x00A000A0;
812
813 *((vu_long *)dest) = data;
814
815 /* re-enable interrupts if necessary */
816 if (flag)
817 enable_interrupts();
818
819 /* data polling for D7 */
820 start = get_timer (0);
821 while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
822 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
823 return (1);
824 }
825 }
826 return (0);
827}
828
829/*-----------------------------------------------------------------------
830 */