blob: 1f8665768b005bcb8b288b6dd03d707a296dddaa [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wenyou Yang9e5935c2016-07-20 17:55:12 +08002/*
3 * Copyright (C) 2016 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
Wenyou Yang9e5935c2016-07-20 17:55:12 +08005 */
6
7#include <common.h>
8#include <clk-uclass.h>
Simon Glass9d922452017-05-17 17:18:03 -06009#include <dm.h>
Wenyou Yang9e5935c2016-07-20 17:55:12 +080010
11static int at91_slow_clk_enable(struct clk *clk)
12{
13 return 0;
14}
15
16static ulong at91_slow_clk_get_rate(struct clk *clk)
17{
18 return CONFIG_SYS_AT91_SLOW_CLOCK;
19}
20
21static struct clk_ops at91_slow_clk_ops = {
22 .enable = at91_slow_clk_enable,
23 .get_rate = at91_slow_clk_get_rate,
24};
25
26static const struct udevice_id at91_slow_clk_match[] = {
27 { .compatible = "atmel,at91sam9x5-clk-slow" },
28 {}
29};
30
31U_BOOT_DRIVER(at91_slow_clk) = {
32 .name = "at91-slow-clk",
33 .id = UCLASS_CLK,
34 .of_match = at91_slow_clk_match,
35 .ops = &at91_slow_clk_ops,
36};