blob: eef524b45ea8b243a21257b741e6d4db11e599c7 [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2003,Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
wdenk42d1f032003-10-15 23:53:47 +000028#include <common.h>
wdenk9aea9532004-08-01 23:02:45 +000029#include <pci.h>
wdenk42d1f032003-10-15 23:53:47 +000030#include <asm/processor.h>
31#include <asm/immap_85xx.h>
32#include <ioports.h>
33#include <spd.h>
34#include <miiphy.h>
35
Jon Loeligerf5012822006-10-20 15:54:34 -050036#if defined(CONFIG_OF_FLAT_TREE)
37#include <ft_build.h>
38#endif
39
Jon Loeligerd9b94f22005-07-25 14:05:07 -050040#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk0ac6f8b2004-07-09 23:27:13 +000041extern void ddr_enable_ecc(unsigned int dram_size);
42#endif
43
44extern long int spd_sdram(void);
45
wdenk9aea9532004-08-01 23:02:45 +000046void local_bus_init(void);
wdenk0ac6f8b2004-07-09 23:27:13 +000047void sdram_init(void);
48long int fixed_sdram(void);
49
wdenk42d1f032003-10-15 23:53:47 +000050
51/*
52 * I/O Port configuration table
53 *
54 * if conf is 1, then that port pin will be configured at boot time
55 * according to the five values podr/pdir/ppar/psor/pdat for that entry
56 */
57
58const iop_conf_t iop_conf_tab[4][32] = {
59
60 /* Port A configuration */
61 { /* conf ppar psor pdir podr pdat */
62 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
63 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
64 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
65 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
66 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
67 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
68 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
69 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
70 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
71 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
72 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
73 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
74 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
75 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
76 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
77 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
78 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
79 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
80 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
81 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
82 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
83 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
84 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
85 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
86 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
87 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
88 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
89 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
90 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
91 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
92 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
93 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
94 },
95
96 /* Port B configuration */
97 { /* conf ppar psor pdir podr pdat */
98 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
99 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
100 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
101 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
102 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
103 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
104 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
105 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
106 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
107 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
108 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
109 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
110 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
111 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
112 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
113 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
114 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
115 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
116 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
117 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
118 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
119 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
120 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
121 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
122 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
123 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
124 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
125 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
126 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
127 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
128 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
129 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
130 },
131
132 /* Port C */
133 { /* conf ppar psor pdir podr pdat */
134 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
135 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
136 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
137 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
138 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
139 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
140 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
141 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
142 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
143 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
144 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
145 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
146 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
147 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
148 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
149 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
150 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
151 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
152 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
153 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
154 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
155 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
156 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
157 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
158 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
159 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
160 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
161 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
162 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
163 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
164 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
165 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
166 },
167
168 /* Port D */
169 { /* conf ppar psor pdir podr pdat */
170 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
171 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
172 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
173 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
174 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
175 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
176 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
177 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
178 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
179 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
180 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
181 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
182 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
183 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
184 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
185 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
186 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
187 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
188 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
189 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
190 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
191 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
192 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
193 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
194 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
195 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
196 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
197 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
198 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
199 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
200 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
201 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
202 }
203};
204
wdenk0ac6f8b2004-07-09 23:27:13 +0000205
206/*
207 * MPC8560ADS Board Status & Control Registers
208 */
209typedef struct bcsr_ {
wdenk42d1f032003-10-15 23:53:47 +0000210 volatile unsigned char bcsr0;
211 volatile unsigned char bcsr1;
212 volatile unsigned char bcsr2;
213 volatile unsigned char bcsr3;
214 volatile unsigned char bcsr4;
215 volatile unsigned char bcsr5;
216} bcsr_t;
217
wdenk9aea9532004-08-01 23:02:45 +0000218
wdenkc837dcb2004-01-20 23:12:12 +0000219int board_early_init_f (void)
wdenk42d1f032003-10-15 23:53:47 +0000220{
wdenk9aea9532004-08-01 23:02:45 +0000221 return 0;
wdenk42d1f032003-10-15 23:53:47 +0000222}
223
224void reset_phy (void)
225{
226#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
227 volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
228#endif
229 /* reset Giga bit Ethernet port if needed here */
230
231 /* reset the CPM FEC port */
232#if (CONFIG_ETHER_INDEX == 2)
233 bcsr->bcsr2 &= ~FETH2_RST;
234 udelay(2);
235 bcsr->bcsr2 |= FETH2_RST;
236 udelay(1000);
237#elif (CONFIG_ETHER_INDEX == 3)
238 bcsr->bcsr3 &= ~FETH3_RST;
239 udelay(2);
240 bcsr->bcsr3 |= FETH3_RST;
241 udelay(1000);
242#endif
243#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200244 /* reset PHY */
245 miiphy_reset("FCC1 ETHERNET", 0x0);
246
247 /* change PHY address to 0x02 */
248 bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
249
250 bb_miiphy_write(NULL, 0x02, PHY_BMCR,
251 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
wdenk42d1f032003-10-15 23:53:47 +0000252#endif /* CONFIG_MII */
253}
254
wdenk9aea9532004-08-01 23:02:45 +0000255
wdenk42d1f032003-10-15 23:53:47 +0000256int checkboard (void)
257{
wdenk97d80fc2004-06-09 00:34:46 +0000258 puts("Board: ADS\n");
wdenk0ac6f8b2004-07-09 23:27:13 +0000259
260#ifdef CONFIG_PCI
261 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
262 CONFIG_SYS_CLK_FREQ / 1000000);
263#else
264 printf(" PCI1: disabled\n");
265#endif
wdenk9aea9532004-08-01 23:02:45 +0000266
267 /*
268 * Initialize local bus.
269 */
270 local_bus_init();
271
wdenk97d80fc2004-06-09 00:34:46 +0000272 return 0;
wdenk42d1f032003-10-15 23:53:47 +0000273}
274
275
wdenk0ac6f8b2004-07-09 23:27:13 +0000276long int
277initdram(int board_type)
wdenk42d1f032003-10-15 23:53:47 +0000278{
279 long dram_size = 0;
280 extern long spd_sdram (void);
281 volatile immap_t *immap = (immap_t *)CFG_IMMR;
wdenk0ac6f8b2004-07-09 23:27:13 +0000282
283 puts("Initializing\n");
wdenk97d80fc2004-06-09 00:34:46 +0000284
wdenk42d1f032003-10-15 23:53:47 +0000285#if defined(CONFIG_DDR_DLL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000286 {
wdenk9aea9532004-08-01 23:02:45 +0000287 volatile ccsr_gur_t *gur= &immap->im_gur;
288 uint temp_ddrdll = 0;
wdenk42d1f032003-10-15 23:53:47 +0000289
wdenk9aea9532004-08-01 23:02:45 +0000290 /*
291 * Work around to stabilize DDR DLL
292 */
293 temp_ddrdll = gur->ddrdllcr;
294 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
295 asm("sync;isync;msync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000296 }
wdenk42d1f032003-10-15 23:53:47 +0000297#endif
298
299#if defined(CONFIG_SPD_EEPROM)
300 dram_size = spd_sdram ();
301#else
302 dram_size = fixed_sdram ();
303#endif
304
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500305#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk0ac6f8b2004-07-09 23:27:13 +0000306 /*
307 * Initialize and enable DDR ECC.
308 */
309 ddr_enable_ecc(dram_size);
310#endif
311
312 /*
313 * Initialize SDRAM.
314 */
315 sdram_init();
316
317 puts(" DDR: ");
318 return dram_size;
319}
320
321
322/*
wdenk9aea9532004-08-01 23:02:45 +0000323 * Initialize Local Bus
wdenk0ac6f8b2004-07-09 23:27:13 +0000324 */
325
wdenk9aea9532004-08-01 23:02:45 +0000326void
327local_bus_init(void)
wdenk0ac6f8b2004-07-09 23:27:13 +0000328{
wdenk9aea9532004-08-01 23:02:45 +0000329 volatile immap_t *immap = (immap_t *)CFG_IMMR;
330 volatile ccsr_gur_t *gur = &immap->im_gur;
wdenk0ac6f8b2004-07-09 23:27:13 +0000331 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
wdenk0ac6f8b2004-07-09 23:27:13 +0000332
wdenk9aea9532004-08-01 23:02:45 +0000333 uint clkdiv;
334 uint lbc_hz;
335 sys_info_t sysinfo;
wdenk0ac6f8b2004-07-09 23:27:13 +0000336
337 /*
wdenk9aea9532004-08-01 23:02:45 +0000338 * Errata LBC11.
339 * Fix Local Bus clock glitch when DLL is enabled.
wdenk0ac6f8b2004-07-09 23:27:13 +0000340 *
wdenk9aea9532004-08-01 23:02:45 +0000341 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
342 * If localbus freq is > 133Mhz, DLL can be safely enabled.
343 * Between 66 and 133, the DLL is enabled with an override workaround.
wdenk0ac6f8b2004-07-09 23:27:13 +0000344 */
wdenk9aea9532004-08-01 23:02:45 +0000345
346 get_sys_info(&sysinfo);
347 clkdiv = lbc->lcrr & 0x0f;
348 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
349
350 if (lbc_hz < 66) {
351 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
352
353 } else if (lbc_hz >= 133) {
354 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
wdenk0ac6f8b2004-07-09 23:27:13 +0000355
wdenk42d1f032003-10-15 23:53:47 +0000356 } else {
wdenk0ac6f8b2004-07-09 23:27:13 +0000357 /*
358 * On REV1 boards, need to change CLKDIV before enable DLL.
359 * Default CLKDIV is 8, change it to 4 temporarily.
360 */
wdenk9aea9532004-08-01 23:02:45 +0000361 uint pvr = get_pvr();
wdenk0ac6f8b2004-07-09 23:27:13 +0000362 uint temp_lbcdll = 0;
wdenk97d80fc2004-06-09 00:34:46 +0000363
364 if (pvr == PVR_85xx_REV1) {
wdenk9aea9532004-08-01 23:02:45 +0000365 /* FIXME: Justify the high bit here. */
wdenk0ac6f8b2004-07-09 23:27:13 +0000366 lbc->lcrr = 0x10000004;
wdenk97d80fc2004-06-09 00:34:46 +0000367 }
wdenk0ac6f8b2004-07-09 23:27:13 +0000368
wdenk9aea9532004-08-01 23:02:45 +0000369 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
370 udelay(200);
371
372 /*
373 * Sample LBC DLL ctrl reg, upshift it to set the
374 * override bits.
375 */
wdenk42d1f032003-10-15 23:53:47 +0000376 temp_lbcdll = gur->lbcdllcr;
wdenk9aea9532004-08-01 23:02:45 +0000377 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
378 asm("sync;isync;msync");
wdenk42d1f032003-10-15 23:53:47 +0000379 }
wdenk9aea9532004-08-01 23:02:45 +0000380}
381
382
383/*
384 * Initialize SDRAM memory on the Local Bus.
385 */
386
387void
388sdram_init(void)
389{
390 volatile immap_t *immap = (immap_t *)CFG_IMMR;
391 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
392 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
393
394 puts(" SDRAM: ");
395 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
wdenk0ac6f8b2004-07-09 23:27:13 +0000396
397 /*
398 * Setup SDRAM Base and Option Registers
399 */
400 lbc->or2 = CFG_OR2_PRELIM;
wdenk42d1f032003-10-15 23:53:47 +0000401 lbc->br2 = CFG_BR2_PRELIM;
402 lbc->lbcr = CFG_LBC_LBCR;
wdenk9aea9532004-08-01 23:02:45 +0000403 asm("msync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000404
wdenk42d1f032003-10-15 23:53:47 +0000405 lbc->lsrt = CFG_LBC_LSRT;
wdenk42d1f032003-10-15 23:53:47 +0000406 lbc->mrtpr = CFG_LBC_MRTPR;
wdenk9aea9532004-08-01 23:02:45 +0000407 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000408
409 /*
410 * Configure the SDRAM controller.
411 */
412 lbc->lsdmr = CFG_LBC_LSDMR_1;
wdenk9aea9532004-08-01 23:02:45 +0000413 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000414 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000415 ppcDcbf((unsigned long) sdram_addr);
416 udelay(100);
wdenk0ac6f8b2004-07-09 23:27:13 +0000417
418 lbc->lsdmr = CFG_LBC_LSDMR_2;
wdenk9aea9532004-08-01 23:02:45 +0000419 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000420 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000421 ppcDcbf((unsigned long) sdram_addr);
422 udelay(100);
wdenk0ac6f8b2004-07-09 23:27:13 +0000423
424 lbc->lsdmr = CFG_LBC_LSDMR_3;
wdenk9aea9532004-08-01 23:02:45 +0000425 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000426 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000427 ppcDcbf((unsigned long) sdram_addr);
428 udelay(100);
wdenk0ac6f8b2004-07-09 23:27:13 +0000429
430 lbc->lsdmr = CFG_LBC_LSDMR_4;
wdenk9aea9532004-08-01 23:02:45 +0000431 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000432 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000433 ppcDcbf((unsigned long) sdram_addr);
434 udelay(100);
wdenk0ac6f8b2004-07-09 23:27:13 +0000435
436 lbc->lsdmr = CFG_LBC_LSDMR_5;
wdenk9aea9532004-08-01 23:02:45 +0000437 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000438 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000439 ppcDcbf((unsigned long) sdram_addr);
440 udelay(100);
wdenk42d1f032003-10-15 23:53:47 +0000441}
442
443
444#if defined(CFG_DRAM_TEST)
445int testdram (void)
446{
447 uint *pstart = (uint *) CFG_MEMTEST_START;
448 uint *pend = (uint *) CFG_MEMTEST_END;
449 uint *p;
450
451 printf("SDRAM test phase 1:\n");
452 for (p = pstart; p < pend; p++)
453 *p = 0xaaaaaaaa;
454
455 for (p = pstart; p < pend; p++) {
456 if (*p != 0xaaaaaaaa) {
457 printf ("SDRAM test fails at: %08x\n", (uint) p);
458 return 1;
459 }
460 }
461
462 printf("SDRAM test phase 2:\n");
463 for (p = pstart; p < pend; p++)
464 *p = 0x55555555;
465
466 for (p = pstart; p < pend; p++) {
467 if (*p != 0x55555555) {
468 printf ("SDRAM test fails at: %08x\n", (uint) p);
469 return 1;
470 }
471 }
472
473 printf("SDRAM test passed.\n");
474 return 0;
475}
476#endif
477
wdenk0ac6f8b2004-07-09 23:27:13 +0000478
wdenk42d1f032003-10-15 23:53:47 +0000479#if !defined(CONFIG_SPD_EEPROM)
480/*************************************************************************
481 * fixed sdram init -- doesn't use serial presence detect.
482 ************************************************************************/
483long int fixed_sdram (void)
484{
485 #ifndef CFG_RAMBOOT
486 volatile immap_t *immap = (immap_t *)CFG_IMMR;
487 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
488
489 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
490 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
491 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
492 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
493 ddr->sdram_mode = CFG_DDR_MODE;
494 ddr->sdram_interval = CFG_DDR_INTERVAL;
495 #if defined (CONFIG_DDR_ECC)
496 ddr->err_disable = 0x0000000D;
497 ddr->err_sbe = 0x00ff0000;
498 #endif
499 asm("sync;isync;msync");
500 udelay(500);
501 #if defined (CONFIG_DDR_ECC)
502 /* Enable ECC checking */
503 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
504 #else
505 ddr->sdram_cfg = CFG_DDR_CONTROL;
506 #endif
507 asm("sync; isync; msync");
508 udelay(500);
509 #endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000510 return CFG_SDRAM_SIZE * 1024 * 1024;
wdenk42d1f032003-10-15 23:53:47 +0000511}
512#endif /* !defined(CONFIG_SPD_EEPROM) */
wdenk9aea9532004-08-01 23:02:45 +0000513
514
515#if defined(CONFIG_PCI)
516/*
517 * Initialize PCI Devices, report devices found.
518 */
519
520#ifndef CONFIG_PCI_PNP
521static struct pci_config_table pci_mpc85xxads_config_table[] = {
522 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
523 PCI_IDSEL_NUMBER, PCI_ANY_ID,
524 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
525 PCI_ENET0_MEMADDR,
526 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
527 } },
528 { }
529};
530#endif
531
532
533static struct pci_controller hose = {
534#ifndef CONFIG_PCI_PNP
535 config_table: pci_mpc85xxads_config_table,
536#endif
537};
538
539#endif /* CONFIG_PCI */
540
541
542void
543pci_init_board(void)
544{
545#ifdef CONFIG_PCI
wdenk9aea9532004-08-01 23:02:45 +0000546 pci_mpc85xx_init(&hose);
547#endif /* CONFIG_PCI */
548}
Matthew McClintock0e163872006-06-28 10:43:36 -0500549
550
551#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
552void
Andy Flemingccc091a2007-05-08 17:27:43 -0500553ft_soc_setup(void *blob, bd_t *bd)
554{
555 u32 *p;
556 int len;
Andy Flemingccc091a2007-05-08 17:27:43 -0500557
558 p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
559
560 if (p != NULL)
561 *p = cpu_to_be32(bd->bi_brgfreq);
562
563 p = ft_get_prop(blob,
564 "/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed",
565 &len);
566 if (p != NULL)
567 *p = cpu_to_be32(bd->bi_baudrate);
568
569 p = ft_get_prop(blob,
570 "/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed",
571 &len);
572 if (p != NULL)
573 *p = cpu_to_be32(bd->bi_baudrate);
574}
575
576void
Matthew McClintock0e163872006-06-28 10:43:36 -0500577ft_board_setup(void *blob, bd_t *bd)
578{
579 ft_cpu_setup(blob, bd);
Andy Flemingccc091a2007-05-08 17:27:43 -0500580 ft_soc_setup(blob, bd);
Matthew McClintock0e163872006-06-28 10:43:36 -0500581}
582#endif