| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* DO NOT EDIT THIS FILE |
| 2 | * Automatically generated by generate-def-headers.xsl |
| 3 | * DO NOT EDIT THIS FILE |
| 4 | */ |
| 5 | |
| 6 | #ifndef __BFIN_DEF_ADSP_BF533_proc__ |
| 7 | #define __BFIN_DEF_ADSP_BF533_proc__ |
| 8 | |
| 9 | #include "../mach-common/ADSP-EDN-core_def.h" |
| 10 | |
| 11 | #include "../mach-common/ADSP-EDN-extended_def.h" |
| 12 | |
| 13 | #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ |
| 14 | #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) |
| 15 | #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) |
| 16 | #define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ |
| 17 | #define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) |
| 18 | #define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) |
| 19 | #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ |
| 20 | #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) |
| 21 | #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) |
| 22 | #define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ |
| 23 | #define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) |
| 24 | #define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) |
| 25 | #define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ |
| 26 | #define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) |
| 27 | #define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) |
| 28 | |
| 29 | #endif /* __BFIN_DEF_ADSP_BF533_proc__ */ |