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Tom Warren3f82b1d2011-01-27 10:58:05 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef _TEGRA2_H_
25#define _TEGRA2_H_
26
27#define NV_PA_SDRAM_BASE 0x00000000
Tom Warren74652cf2011-04-14 12:18:06 +000028#define NV_PA_ARM_PERIPHBASE 0x50040000
29#define NV_PA_PG_UP_BASE 0x60000000
Tom Warren3f82b1d2011-01-27 10:58:05 +000030#define NV_PA_TMRUS_BASE 0x60005010
31#define NV_PA_CLK_RST_BASE 0x60006000
Tom Warren74652cf2011-04-14 12:18:06 +000032#define NV_PA_FLOW_BASE 0x60007000
Tom Warrenc5e93132011-04-14 12:09:40 +000033#define NV_PA_GPIO_BASE 0x6000D000
Tom Warren74652cf2011-04-14 12:18:06 +000034#define NV_PA_EVP_BASE 0x6000F000
Tom Warren3f82b1d2011-01-27 10:58:05 +000035#define NV_PA_APB_MISC_BASE 0x70000000
36#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
37#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
38#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
39#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
40#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
41#define NV_PA_PMC_BASE 0x7000E400
Tom Warren74652cf2011-04-14 12:18:06 +000042#define NV_PA_CSITE_BASE 0x70040000
Tom Warren3f82b1d2011-01-27 10:58:05 +000043
44#define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE
45#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
Tom Warren74652cf2011-04-14 12:18:06 +000046#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
47#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
48#define PG_UP_TAG_AVP 0xAAAAAAAA
Tom Warren3f82b1d2011-01-27 10:58:05 +000049
50#ifndef __ASSEMBLY__
51struct timerus {
52 unsigned int cntr_1us;
53};
54#else /* __ASSEMBLY__ */
55#define PRM_RSTCTRL NV_PA_PMC_BASE
56#endif
57
58#endif /* TEGRA2_H */