wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 8 | * Alex Zuepke <azu@sysgo.de> |
| 9 | * |
| 10 | * (C) Copyright 2002 |
| 11 | * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
| 12 | * |
| 13 | * See file CREDITS for list of people who contributed to this |
| 14 | * project. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or |
| 17 | * modify it under the terms of the GNU General Public License as |
| 18 | * published by the Free Software Foundation; either version 2 of |
| 19 | * the License, or (at your option) any later version. |
| 20 | * |
| 21 | * This program is distributed in the hope that it will be useful, |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 24 | * GNU General Public License for more details. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License |
| 27 | * along with this program; if not, write to the Free Software |
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 29 | * MA 02111-1307 USA |
| 30 | */ |
| 31 | |
| 32 | #include <common.h> |
| 33 | #include <arm920t.h> |
| 34 | #include <lh7a40x.h> |
| 35 | |
| 36 | #include <asm/proc-armv/ptrace.h> |
| 37 | |
| 38 | extern void reset_cpu(ulong addr); |
| 39 | static ulong timer_load_val = 0; |
| 40 | |
| 41 | /* macro to read the 16 bit timer */ |
| 42 | static inline ulong READ_TIMER(void) |
| 43 | { |
wdenk | f832d8a | 2004-06-10 21:55:33 +0000 | [diff] [blame^] | 44 | lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 45 | lh7a40x_timer_t* timer = &timers->timer1; |
| 46 | |
| 47 | return (timer->value & 0x0000ffff); |
| 48 | } |
| 49 | |
| 50 | #ifdef CONFIG_USE_IRQ |
| 51 | /* enable IRQ interrupts */ |
| 52 | void enable_interrupts (void) |
| 53 | { |
| 54 | unsigned long temp; |
| 55 | __asm__ __volatile__("mrs %0, cpsr\n" |
| 56 | "bic %0, %0, #0x80\n" |
| 57 | "msr cpsr_c, %0" |
| 58 | : "=r" (temp) |
| 59 | : |
| 60 | : "memory"); |
| 61 | } |
| 62 | |
| 63 | |
| 64 | /* |
| 65 | * disable IRQ/FIQ interrupts |
| 66 | * returns true if interrupts had been enabled before we disabled them |
| 67 | */ |
| 68 | int disable_interrupts (void) |
| 69 | { |
| 70 | unsigned long old,temp; |
| 71 | __asm__ __volatile__("mrs %0, cpsr\n" |
| 72 | "orr %1, %0, #0xc0\n" |
| 73 | "msr cpsr_c, %1" |
| 74 | : "=r" (old), "=r" (temp) |
| 75 | : |
| 76 | : "memory"); |
| 77 | return (old & 0x80) == 0; |
| 78 | } |
| 79 | #else |
| 80 | void enable_interrupts (void) |
| 81 | { |
| 82 | return; |
| 83 | } |
| 84 | int disable_interrupts (void) |
| 85 | { |
| 86 | return 0; |
| 87 | } |
| 88 | #endif |
| 89 | |
| 90 | |
| 91 | void bad_mode (void) |
| 92 | { |
| 93 | panic ("Resetting CPU ...\n"); |
| 94 | reset_cpu (0); |
| 95 | } |
| 96 | |
| 97 | void show_regs (struct pt_regs *regs) |
| 98 | { |
| 99 | unsigned long flags; |
| 100 | const char *processor_modes[] = { |
| 101 | "USER_26", "FIQ_26", "IRQ_26", "SVC_26", |
| 102 | "UK4_26", "UK5_26", "UK6_26", "UK7_26", |
| 103 | "UK8_26", "UK9_26", "UK10_26", "UK11_26", |
| 104 | "UK12_26", "UK13_26", "UK14_26", "UK15_26", |
| 105 | "USER_32", "FIQ_32", "IRQ_32", "SVC_32", |
| 106 | "UK4_32", "UK5_32", "UK6_32", "ABT_32", |
| 107 | "UK8_32", "UK9_32", "UK10_32", "UND_32", |
| 108 | "UK12_32", "UK13_32", "UK14_32", "SYS_32", |
| 109 | }; |
| 110 | |
| 111 | flags = condition_codes (regs); |
| 112 | |
| 113 | printf ("pc : [<%08lx>] lr : [<%08lx>]\n" |
| 114 | "sp : %08lx ip : %08lx fp : %08lx\n", |
| 115 | instruction_pointer (regs), |
| 116 | regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); |
| 117 | printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", |
| 118 | regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); |
| 119 | printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", |
| 120 | regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); |
| 121 | printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", |
| 122 | regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); |
| 123 | printf ("Flags: %c%c%c%c", |
| 124 | flags & CC_N_BIT ? 'N' : 'n', |
| 125 | flags & CC_Z_BIT ? 'Z' : 'z', |
| 126 | flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); |
| 127 | printf (" IRQs %s FIQs %s Mode %s%s\n", |
| 128 | interrupts_enabled (regs) ? "on" : "off", |
| 129 | fast_interrupts_enabled (regs) ? "on" : "off", |
| 130 | processor_modes[processor_mode (regs)], |
| 131 | thumb_mode (regs) ? " (T)" : ""); |
| 132 | } |
| 133 | |
| 134 | void do_undefined_instruction (struct pt_regs *pt_regs) |
| 135 | { |
| 136 | printf ("undefined instruction\n"); |
| 137 | show_regs (pt_regs); |
| 138 | bad_mode (); |
| 139 | } |
| 140 | |
| 141 | void do_software_interrupt (struct pt_regs *pt_regs) |
| 142 | { |
| 143 | printf ("software interrupt\n"); |
| 144 | show_regs (pt_regs); |
| 145 | bad_mode (); |
| 146 | } |
| 147 | |
| 148 | void do_prefetch_abort (struct pt_regs *pt_regs) |
| 149 | { |
| 150 | printf ("prefetch abort\n"); |
| 151 | show_regs (pt_regs); |
| 152 | bad_mode (); |
| 153 | } |
| 154 | |
| 155 | void do_data_abort (struct pt_regs *pt_regs) |
| 156 | { |
| 157 | printf ("data abort\n"); |
| 158 | show_regs (pt_regs); |
| 159 | bad_mode (); |
| 160 | } |
| 161 | |
| 162 | void do_not_used (struct pt_regs *pt_regs) |
| 163 | { |
| 164 | printf ("not used\n"); |
| 165 | show_regs (pt_regs); |
| 166 | bad_mode (); |
| 167 | } |
| 168 | |
| 169 | void do_fiq (struct pt_regs *pt_regs) |
| 170 | { |
| 171 | printf ("fast interrupt request\n"); |
| 172 | show_regs (pt_regs); |
| 173 | bad_mode (); |
| 174 | } |
| 175 | |
| 176 | void do_irq (struct pt_regs *pt_regs) |
| 177 | { |
| 178 | printf ("interrupt request\n"); |
| 179 | show_regs (pt_regs); |
| 180 | bad_mode (); |
| 181 | } |
| 182 | |
| 183 | static ulong timestamp; |
| 184 | static ulong lastdec; |
| 185 | |
| 186 | int interrupt_init (void) |
| 187 | { |
wdenk | f832d8a | 2004-06-10 21:55:33 +0000 | [diff] [blame^] | 188 | lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 189 | lh7a40x_timer_t* timer = &timers->timer1; |
| 190 | |
| 191 | /* a periodic timer using the 508kHz source */ |
| 192 | timer->control = (TIMER_PER | TIMER_CLK508K); |
| 193 | |
| 194 | if (timer_load_val == 0) { |
| 195 | /* |
| 196 | * 10ms period with 508.469kHz clock = 5084 |
| 197 | */ |
| 198 | timer_load_val = CFG_HZ/100; |
| 199 | } |
| 200 | |
| 201 | /* load value for 10 ms timeout */ |
| 202 | lastdec = timer->load = timer_load_val; |
| 203 | |
| 204 | /* auto load, start timer */ |
| 205 | timer->control = timer->control | TIMER_EN; |
| 206 | timestamp = 0; |
| 207 | |
| 208 | return (0); |
| 209 | } |
| 210 | |
| 211 | /* |
| 212 | * timer without interrupts |
| 213 | */ |
| 214 | |
| 215 | void reset_timer (void) |
| 216 | { |
| 217 | reset_timer_masked (); |
| 218 | } |
| 219 | |
| 220 | ulong get_timer (ulong base) |
| 221 | { |
| 222 | return (get_timer_masked() - base); |
| 223 | } |
| 224 | |
| 225 | void set_timer (ulong t) |
| 226 | { |
| 227 | timestamp = t; |
| 228 | } |
| 229 | |
| 230 | void udelay (unsigned long usec) |
| 231 | { |
| 232 | ulong tmo,tmp; |
| 233 | |
| 234 | /* normalize */ |
| 235 | if (usec >= 1000) { |
| 236 | tmo = usec / 1000; |
| 237 | tmo *= CFG_HZ; |
| 238 | tmo /= 1000; |
| 239 | } |
| 240 | else { |
| 241 | if (usec > 1) { |
| 242 | tmo = usec * CFG_HZ; |
| 243 | tmo /= (1000*1000); |
| 244 | } |
| 245 | else |
| 246 | tmo = 1; |
| 247 | } |
| 248 | |
| 249 | /* check for rollover during this delay */ |
| 250 | tmp = get_timer (0); |
| 251 | if ((tmp + tmo) < tmp ) |
| 252 | reset_timer_masked(); /* timer would roll over */ |
| 253 | else |
| 254 | tmo += tmp; |
| 255 | |
| 256 | while (get_timer_masked () < tmo); |
| 257 | } |
| 258 | |
| 259 | void reset_timer_masked (void) |
| 260 | { |
| 261 | /* reset time */ |
| 262 | lastdec = READ_TIMER(); |
| 263 | timestamp = 0; |
| 264 | } |
| 265 | |
| 266 | ulong get_timer_masked (void) |
| 267 | { |
| 268 | ulong now = READ_TIMER(); |
| 269 | |
| 270 | if (lastdec >= now) { |
| 271 | /* normal mode */ |
| 272 | timestamp += (lastdec - now); |
| 273 | } else { |
| 274 | /* we have an overflow ... */ |
| 275 | timestamp += ((lastdec + timer_load_val) - now); |
| 276 | } |
| 277 | lastdec = now; |
| 278 | |
| 279 | return timestamp; |
| 280 | } |
| 281 | |
| 282 | void udelay_masked (unsigned long usec) |
| 283 | { |
| 284 | ulong tmo; |
| 285 | |
| 286 | /* normalize */ |
| 287 | if (usec >= 1000) { |
| 288 | tmo = usec / 1000; |
| 289 | tmo *= CFG_HZ; |
| 290 | tmo /= 1000; |
| 291 | } |
| 292 | else { |
| 293 | if (usec > 1) { |
| 294 | tmo = usec * CFG_HZ; |
| 295 | tmo /= (1000*1000); |
| 296 | } |
| 297 | else |
| 298 | tmo = 1; |
| 299 | } |
| 300 | |
| 301 | reset_timer_masked (); |
| 302 | |
| 303 | while (get_timer_masked () < tmo); |
| 304 | } |
| 305 | |
| 306 | /* |
| 307 | * This function is derived from PowerPC code (read timebase as long long). |
| 308 | * On ARM it just returns the timer value. |
| 309 | */ |
| 310 | unsigned long long get_ticks(void) |
| 311 | { |
| 312 | return get_timer(0); |
| 313 | } |
| 314 | |
| 315 | /* |
| 316 | * This function is derived from PowerPC code (timebase clock frequency). |
| 317 | * On ARM it returns the number of timer ticks per second. |
| 318 | */ |
| 319 | ulong get_tbclk (void) |
| 320 | { |
| 321 | ulong tbclk; |
| 322 | |
| 323 | tbclk = timer_load_val * 100; |
| 324 | |
| 325 | return tbclk; |
| 326 | } |