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Kumar Gala58e5e9a2008-08-26 15:01:29 -05001/*
York Sun34e026f2014-03-27 17:54:47 -07002 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala58e5e9a2008-08-26 15:01:29 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala58e5e9a2008-08-26 15:01:29 -05005 */
6
7/*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13#include <common.h>
York Sun5614e712013-09-30 09:22:09 -070014#include <fsl_ddr_sdram.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050015
York Sun5614e712013-09-30 09:22:09 -070016#include <fsl_ddr.h>
York Sun9a17eb52013-11-18 10:29:32 -080017#include <fsl_immap.h>
York Sun5614e712013-09-30 09:22:09 -070018#include <asm/io.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050019
York Sune1fd16b2011-01-10 12:03:00 +000020unsigned int picos_to_mclk(unsigned int picos);
21
Kumar Gala58e5e9a2008-08-26 15:01:29 -050022/*
23 * Determine Rtt value.
24 *
25 * This should likely be either board or controller specific.
26 *
Dave Liuc360cea2009-03-14 12:48:30 +080027 * Rtt(nominal) - DDR2:
Kumar Gala58e5e9a2008-08-26 15:01:29 -050028 * 0 = Rtt disabled
29 * 1 = 75 ohm
30 * 2 = 150 ohm
31 * 3 = 50 ohm
Dave Liuc360cea2009-03-14 12:48:30 +080032 * Rtt(nominal) - DDR3:
33 * 0 = Rtt disabled
34 * 1 = 60 ohm
35 * 2 = 120 ohm
36 * 3 = 40 ohm
37 * 4 = 20 ohm
38 * 5 = 30 ohm
Kumar Gala58e5e9a2008-08-26 15:01:29 -050039 *
40 * FIXME: Apparently 8641 needs a value of 2
41 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
42 *
43 * FIXME: There was some effort down this line earlier:
44 *
45 * unsigned int i;
46 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
47 * if (popts->dimmslot[i].num_valid_cs
48 * && (popts->cs_local_opts[2*i].odt_rd_cfg
49 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
50 * rtt = 2;
51 * break;
52 * }
53 * }
54 */
55static inline int fsl_ddr_get_rtt(void)
56{
57 int rtt;
58
York Sun5614e712013-09-30 09:22:09 -070059#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050060 rtt = 0;
York Sun5614e712013-09-30 09:22:09 -070061#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050062 rtt = 3;
63#else
Dave Liuc360cea2009-03-14 12:48:30 +080064 rtt = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -050065#endif
66
67 return rtt;
68}
69
York Sun34e026f2014-03-27 17:54:47 -070070#ifdef CONFIG_SYS_FSL_DDR4
71/*
72 * compute CAS write latency according to DDR4 spec
73 * CWL = 9 for <= 1600MT/s
74 * 10 for <= 1866MT/s
75 * 11 for <= 2133MT/s
76 * 12 for <= 2400MT/s
77 * 14 for <= 2667MT/s
78 * 16 for <= 2933MT/s
79 * 18 for higher
80 */
81static inline unsigned int compute_cas_write_latency(void)
82{
83 unsigned int cwl;
84 const unsigned int mclk_ps = get_memory_clk_period_ps();
85 if (mclk_ps >= 1250)
86 cwl = 9;
87 else if (mclk_ps >= 1070)
88 cwl = 10;
89 else if (mclk_ps >= 935)
90 cwl = 11;
91 else if (mclk_ps >= 833)
92 cwl = 12;
93 else if (mclk_ps >= 750)
94 cwl = 14;
95 else if (mclk_ps >= 681)
96 cwl = 16;
97 else
98 cwl = 18;
99
100 return cwl;
101}
102#else
Dave Liuc360cea2009-03-14 12:48:30 +0800103/*
104 * compute the CAS write latency according to DDR3 spec
105 * CWL = 5 if tCK >= 2.5ns
106 * 6 if 2.5ns > tCK >= 1.875ns
107 * 7 if 1.875ns > tCK >= 1.5ns
108 * 8 if 1.5ns > tCK >= 1.25ns
York Sun2bba85f2011-08-24 09:40:25 -0700109 * 9 if 1.25ns > tCK >= 1.07ns
110 * 10 if 1.07ns > tCK >= 0.935ns
111 * 11 if 0.935ns > tCK >= 0.833ns
112 * 12 if 0.833ns > tCK >= 0.75ns
Dave Liuc360cea2009-03-14 12:48:30 +0800113 */
114static inline unsigned int compute_cas_write_latency(void)
115{
116 unsigned int cwl;
117 const unsigned int mclk_ps = get_memory_clk_period_ps();
118
119 if (mclk_ps >= 2500)
120 cwl = 5;
121 else if (mclk_ps >= 1875)
122 cwl = 6;
123 else if (mclk_ps >= 1500)
124 cwl = 7;
125 else if (mclk_ps >= 1250)
126 cwl = 8;
York Sun2bba85f2011-08-24 09:40:25 -0700127 else if (mclk_ps >= 1070)
128 cwl = 9;
129 else if (mclk_ps >= 935)
130 cwl = 10;
131 else if (mclk_ps >= 833)
132 cwl = 11;
133 else if (mclk_ps >= 750)
134 cwl = 12;
135 else {
136 cwl = 12;
137 printf("Warning: CWL is out of range\n");
138 }
Dave Liuc360cea2009-03-14 12:48:30 +0800139 return cwl;
140}
York Sun34e026f2014-03-27 17:54:47 -0700141#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800142
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500143/* Chip Select Configuration (CSn_CONFIG) */
york5800e7a2010-07-02 22:25:53 +0000144static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500145 const memctl_options_t *popts,
146 const dimm_params_t *dimm_params)
147{
148 unsigned int cs_n_en = 0; /* Chip Select enable */
149 unsigned int intlv_en = 0; /* Memory controller interleave enable */
150 unsigned int intlv_ctl = 0; /* Interleaving control */
151 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
152 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
153 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
154 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
155 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
156 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
york5800e7a2010-07-02 22:25:53 +0000157 int go_config = 0;
York Sun34e026f2014-03-27 17:54:47 -0700158#ifdef CONFIG_SYS_FSL_DDR4
159 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
160#else
161 unsigned int n_banks_per_sdram_device;
162#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500163
164 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
york5800e7a2010-07-02 22:25:53 +0000165 switch (i) {
166 case 0:
167 if (dimm_params[dimm_number].n_ranks > 0) {
168 go_config = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500169 /* These fields only available in CS0_CONFIG */
York Suna4c66502012-08-17 08:22:39 +0000170 if (!popts->memctl_interleaving)
171 break;
172 switch (popts->memctl_interleaving_mode) {
York Sun6b1e1252014-02-10 13:59:44 -0800173 case FSL_DDR_256B_INTERLEAVING:
York Suna4c66502012-08-17 08:22:39 +0000174 case FSL_DDR_CACHE_LINE_INTERLEAVING:
175 case FSL_DDR_PAGE_INTERLEAVING:
176 case FSL_DDR_BANK_INTERLEAVING:
177 case FSL_DDR_SUPERBANK_INTERLEAVING:
178 intlv_en = popts->memctl_interleaving;
179 intlv_ctl = popts->memctl_interleaving_mode;
180 break;
181 default:
182 break;
183 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500184 }
york5800e7a2010-07-02 22:25:53 +0000185 break;
186 case 1:
187 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
188 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
189 go_config = 1;
190 break;
191 case 2:
192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
York Suncae7c1b2011-08-26 11:32:40 -0700193 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
york5800e7a2010-07-02 22:25:53 +0000194 go_config = 1;
195 break;
196 case 3:
197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
198 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
199 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
200 go_config = 1;
201 break;
202 default:
203 break;
204 }
205 if (go_config) {
york5800e7a2010-07-02 22:25:53 +0000206 cs_n_en = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500207 ap_n_en = popts->cs_local_opts[i].auto_precharge;
208 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
209 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
York Sun34e026f2014-03-27 17:54:47 -0700210#ifdef CONFIG_SYS_FSL_DDR4
211 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
212 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
213#else
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500214 n_banks_per_sdram_device
york5800e7a2010-07-02 22:25:53 +0000215 = dimm_params[dimm_number].n_banks_per_sdram_device;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500216 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
York Sun34e026f2014-03-27 17:54:47 -0700217#endif
york5800e7a2010-07-02 22:25:53 +0000218 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
219 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500220 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500221 ddr->cs[i].config = (0
222 | ((cs_n_en & 0x1) << 31)
223 | ((intlv_en & 0x3) << 29)
Haiying Wangdbbbb3a2008-10-03 12:36:39 -0400224 | ((intlv_ctl & 0xf) << 24)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500225 | ((ap_n_en & 0x1) << 23)
226
227 /* XXX: some implementation only have 1 bit starting at left */
228 | ((odt_rd_cfg & 0x7) << 20)
229
230 /* XXX: Some implementation only have 1 bit starting at left */
231 | ((odt_wr_cfg & 0x7) << 16)
232
233 | ((ba_bits_cs_n & 0x3) << 14)
234 | ((row_bits_cs_n & 0x7) << 8)
York Sun34e026f2014-03-27 17:54:47 -0700235#ifdef CONFIG_SYS_FSL_DDR4
236 | ((bg_bits_cs_n & 0x3) << 4)
237#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500238 | ((col_bits_cs_n & 0x7) << 0)
239 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400240 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500241}
242
243/* Chip Select Configuration 2 (CSn_CONFIG_2) */
244/* FIXME: 8572 */
245static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
246{
247 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
248
249 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
Haiying Wang1f293b42008-10-03 12:37:26 -0400250 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500251}
252
253/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
254
York Sun5614e712013-09-30 09:22:09 -0700255#if !defined(CONFIG_SYS_FSL_DDR1)
York Sun123922b2012-10-08 07:44:23 +0000256static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
257{
258#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
259 if (dimm_params[0].n_ranks == 4)
260 return 1;
261#endif
262
263#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
264 if ((dimm_params[0].n_ranks == 2) &&
265 (dimm_params[1].n_ranks == 2))
266 return 1;
267
268#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
269 if (dimm_params[0].n_ranks == 4)
270 return 1;
271#endif
272#endif
273 return 0;
274}
275
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500276/*
277 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
278 *
279 * Avoid writing for DDR I. The new PQ38 DDR controller
280 * dreams up non-zero default values to be backwards compatible.
281 */
York Sune1fd16b2011-01-10 12:03:00 +0000282static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
York Sun123922b2012-10-08 07:44:23 +0000283 const memctl_options_t *popts,
284 const dimm_params_t *dimm_params)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500285{
286 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
287 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
288 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
289 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
290 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
291
292 /* Active powerdown exit timing (tXARD and tXARDS). */
293 unsigned char act_pd_exit_mclk;
294 /* Precharge powerdown exit timing (tXP). */
295 unsigned char pre_pd_exit_mclk;
york5fb8a8a2010-07-02 22:25:56 +0000296 /* ODT powerdown exit timing (tAXPD). */
York Sun34e026f2014-03-27 17:54:47 -0700297 unsigned char taxpd_mclk = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500298 /* Mode register set cycle time (tMRD). */
299 unsigned char tmrd_mclk;
York Sunbb578322014-08-21 16:13:22 -0700300#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
301 const unsigned int mclk_ps = get_memory_clk_period_ps();
302#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500303
York Sun34e026f2014-03-27 17:54:47 -0700304#ifdef CONFIG_SYS_FSL_DDR4
305 /* tXP=max(4nCK, 6ns) */
York Sunbb578322014-08-21 16:13:22 -0700306 int txp = max(mclk_ps * 4, 6000); /* unit=ps */
York Sun34e026f2014-03-27 17:54:47 -0700307 trwt_mclk = 2;
308 twrt_mclk = 1;
309 act_pd_exit_mclk = picos_to_mclk(txp);
310 pre_pd_exit_mclk = act_pd_exit_mclk;
311 /*
312 * MRS_CYC = max(tMRD, tMOD)
313 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
314 */
315 tmrd_mclk = max(24, picos_to_mclk(15000));
316#elif defined(CONFIG_SYS_FSL_DDR3)
York Sunbb578322014-08-21 16:13:22 -0700317 unsigned int data_rate = get_ddr_freq(0);
318 int txp;
Dave Liuc360cea2009-03-14 12:48:30 +0800319 /*
320 * (tXARD and tXARDS). Empirical?
321 * The DDR3 spec has not tXARD,
322 * we use the tXP instead of it.
York Sunbb578322014-08-21 16:13:22 -0700323 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
324 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
Dave Liuc360cea2009-03-14 12:48:30 +0800325 * spec has not the tAXPD, we use
york5fb8a8a2010-07-02 22:25:56 +0000326 * tAXPD=1, need design to confirm.
Dave Liuc360cea2009-03-14 12:48:30 +0800327 */
York Sunbb578322014-08-21 16:13:22 -0700328 txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
329
Dave Liuc360cea2009-03-14 12:48:30 +0800330 tmrd_mclk = 4;
Dave Liu99bac472009-12-08 11:56:48 +0800331 /* set the turnaround time */
York Sun123922b2012-10-08 07:44:23 +0000332
333 /*
334 * for single quad-rank DIMM and two dual-rank DIMMs
335 * to avoid ODT overlap
336 */
337 if (avoid_odt_overlap(dimm_params)) {
338 twwt_mclk = 2;
339 trrt_mclk = 1;
340 }
341 /* for faster clock, need more time for data setup */
342 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
343
York Sun856e4b02011-02-10 10:13:10 -0800344 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
345 twrt_mclk = 1;
York Sune1fd16b2011-01-10 12:03:00 +0000346
347 if (popts->dynamic_power == 0) { /* powerdown is not used */
348 act_pd_exit_mclk = 1;
349 pre_pd_exit_mclk = 1;
350 taxpd_mclk = 1;
351 } else {
352 /* act_pd_exit_mclk = tXARD, see above */
York Sun34e026f2014-03-27 17:54:47 -0700353 act_pd_exit_mclk = picos_to_mclk(txp);
York Sune1fd16b2011-01-10 12:03:00 +0000354 /* Mode register MR0[A12] is '1' - fast exit */
355 pre_pd_exit_mclk = act_pd_exit_mclk;
356 taxpd_mclk = 1;
357 }
York Sun5614e712013-09-30 09:22:09 -0700358#else /* CONFIG_SYS_FSL_DDR2 */
Dave Liuc360cea2009-03-14 12:48:30 +0800359 /*
360 * (tXARD and tXARDS). Empirical?
361 * tXARD = 2 for DDR2
362 * tXP=2
363 * tAXPD=8
364 */
365 act_pd_exit_mclk = 2;
366 pre_pd_exit_mclk = 2;
367 taxpd_mclk = 8;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500368 tmrd_mclk = 2;
Dave Liuc360cea2009-03-14 12:48:30 +0800369#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500370
York Sun23f96702011-05-27 13:44:28 +0800371 if (popts->trwt_override)
372 trwt_mclk = popts->trwt;
373
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500374 ddr->timing_cfg_0 = (0
375 | ((trwt_mclk & 0x3) << 30) /* RWT */
376 | ((twrt_mclk & 0x3) << 28) /* WRT */
377 | ((trrt_mclk & 0x3) << 26) /* RRT */
378 | ((twwt_mclk & 0x3) << 24) /* WWT */
York Sund4263b82013-06-03 12:39:06 -0700379 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
Dave Liu22ff3d02008-11-21 16:31:29 +0800380 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500381 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
York Sund4263b82013-06-03 12:39:06 -0700382 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500383 );
384 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
385}
York Sun5614e712013-09-30 09:22:09 -0700386#endif /* defined(CONFIG_SYS_FSL_DDR2) */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500387
388/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
389static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
York Sun45064ad2012-08-17 08:22:40 +0000390 const memctl_options_t *popts,
Dave Liuc360cea2009-03-14 12:48:30 +0800391 const common_timing_params_t *common_dimm,
York Sund4263b82013-06-03 12:39:06 -0700392 unsigned int cas_latency,
393 unsigned int additive_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500394{
York Sun45064ad2012-08-17 08:22:40 +0000395 /* Extended precharge to activate interval (tRP) */
396 unsigned int ext_pretoact = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500397 /* Extended Activate to precharge interval (tRAS) */
398 unsigned int ext_acttopre = 0;
York Sun45064ad2012-08-17 08:22:40 +0000399 /* Extended activate to read/write interval (tRCD) */
400 unsigned int ext_acttorw = 0;
401 /* Extended refresh recovery time (tRFC) */
402 unsigned int ext_refrec;
403 /* Extended MCAS latency from READ cmd */
404 unsigned int ext_caslat = 0;
York Sund4263b82013-06-03 12:39:06 -0700405 /* Extended additive latency */
406 unsigned int ext_add_lat = 0;
York Sun45064ad2012-08-17 08:22:40 +0000407 /* Extended last data to precharge interval (tWR) */
408 unsigned int ext_wrrec = 0;
409 /* Control Adjust */
410 unsigned int cntl_adj = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500411
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530412 ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
413 ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
414 ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
York Sun45064ad2012-08-17 08:22:40 +0000415 ext_caslat = (2 * cas_latency - 1) >> 4;
York Sund4263b82013-06-03 12:39:06 -0700416 ext_add_lat = additive_latency >> 4;
York Sun34e026f2014-03-27 17:54:47 -0700417#ifdef CONFIG_SYS_FSL_DDR4
418 ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
419#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530420 ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
York Sun45064ad2012-08-17 08:22:40 +0000421 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
York Sun34e026f2014-03-27 17:54:47 -0700422#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530423 ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
424 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
Dave Liuc360cea2009-03-14 12:48:30 +0800425
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500426 ddr->timing_cfg_3 = (0
York Sun45064ad2012-08-17 08:22:40 +0000427 | ((ext_pretoact & 0x1) << 28)
James Yangc45f5c02013-07-22 09:35:26 -0700428 | ((ext_acttopre & 0x3) << 24)
York Sun45064ad2012-08-17 08:22:40 +0000429 | ((ext_acttorw & 0x1) << 22)
430 | ((ext_refrec & 0x1F) << 16)
431 | ((ext_caslat & 0x3) << 12)
York Sund4263b82013-06-03 12:39:06 -0700432 | ((ext_add_lat & 0x1) << 10)
York Sun45064ad2012-08-17 08:22:40 +0000433 | ((ext_wrrec & 0x1) << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500434 | ((cntl_adj & 0x7) << 0)
435 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400436 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500437}
438
439/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
440static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
Dave Liuc360cea2009-03-14 12:48:30 +0800441 const memctl_options_t *popts,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500442 const common_timing_params_t *common_dimm,
443 unsigned int cas_latency)
444{
445 /* Precharge-to-activate interval (tRP) */
446 unsigned char pretoact_mclk;
447 /* Activate to precharge interval (tRAS) */
448 unsigned char acttopre_mclk;
449 /* Activate to read/write interval (tRCD) */
450 unsigned char acttorw_mclk;
451 /* CASLAT */
452 unsigned char caslat_ctrl;
453 /* Refresh recovery time (tRFC) ; trfc_low */
454 unsigned char refrec_ctrl;
455 /* Last data to precharge minimum interval (tWR) */
456 unsigned char wrrec_mclk;
457 /* Activate-to-activate interval (tRRD) */
458 unsigned char acttoact_mclk;
459 /* Last write data pair to read command issue interval (tWTR) */
460 unsigned char wrtord_mclk;
York Sun34e026f2014-03-27 17:54:47 -0700461#ifdef CONFIG_SYS_FSL_DDR4
462 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
463 static const u8 wrrec_table[] = {
464 10, 10, 10, 10, 10,
465 10, 10, 10, 10, 10,
466 12, 12, 14, 14, 16,
467 16, 18, 18, 20, 20,
468 24, 24, 24, 24};
469#else
York Sunf5b6fb72011-03-02 14:24:11 -0800470 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
471 static const u8 wrrec_table[] = {
472 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
York Sun34e026f2014-03-27 17:54:47 -0700473#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500474
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530475 pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
476 acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
477 acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500478
479 /*
480 * Translate CAS Latency to a DDR controller field value:
481 *
482 * CAS Lat DDR I DDR II Ctrl
483 * Clocks SPD Bit SPD Bit Value
484 * ------- ------- ------- -----
485 * 1.0 0 0001
486 * 1.5 1 0010
487 * 2.0 2 2 0011
488 * 2.5 3 0100
489 * 3.0 4 3 0101
490 * 3.5 5 0110
491 * 4.0 4 0111
492 * 4.5 1000
493 * 5.0 5 1001
494 */
York Sun5614e712013-09-30 09:22:09 -0700495#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500496 caslat_ctrl = (cas_latency + 1) & 0x07;
York Sun5614e712013-09-30 09:22:09 -0700497#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500498 caslat_ctrl = 2 * cas_latency - 1;
499#else
Dave Liuc360cea2009-03-14 12:48:30 +0800500 /*
501 * if the CAS latency more than 8 cycle,
502 * we need set extend bit for it at
503 * TIMING_CFG_3[EXT_CASLAT]
504 */
York Sun34e026f2014-03-27 17:54:47 -0700505 if (fsl_ddr_get_version() <= 0x40400)
506 caslat_ctrl = 2 * cas_latency - 1;
507 else
508 caslat_ctrl = (cas_latency - 1) << 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500509#endif
510
York Sun34e026f2014-03-27 17:54:47 -0700511#ifdef CONFIG_SYS_FSL_DDR4
512 refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
513 wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
514 acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4);
515 wrtord_mclk = max(2, picos_to_mclk(2500));
York Sun349689b2014-04-01 14:20:49 -0700516 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
517 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
York Sun34e026f2014-03-27 17:54:47 -0700518 else
519 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
520#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530521 refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
522 wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
York Sun34e026f2014-03-27 17:54:47 -0700523 acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
524 wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
York Sun349689b2014-04-01 14:20:49 -0700525 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
526 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
York Sun45064ad2012-08-17 08:22:40 +0000527 else
528 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
York Sun34e026f2014-03-27 17:54:47 -0700529#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530530 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800531 wrrec_mclk += 2;
532
Dave Liuc360cea2009-03-14 12:48:30 +0800533 /*
534 * JEDEC has min requirement for tRRD
535 */
York Sun5614e712013-09-30 09:22:09 -0700536#if defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +0800537 if (acttoact_mclk < 4)
538 acttoact_mclk = 4;
539#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800540 /*
541 * JEDEC has some min requirements for tWTR
542 */
York Sun5614e712013-09-30 09:22:09 -0700543#if defined(CONFIG_SYS_FSL_DDR2)
Dave Liuc360cea2009-03-14 12:48:30 +0800544 if (wrtord_mclk < 2)
545 wrtord_mclk = 2;
York Sun5614e712013-09-30 09:22:09 -0700546#elif defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +0800547 if (wrtord_mclk < 4)
548 wrtord_mclk = 4;
549#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530550 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800551 wrtord_mclk += 2;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500552
553 ddr->timing_cfg_1 = (0
Dave Liu80ee3ce2008-11-21 16:31:22 +0800554 | ((pretoact_mclk & 0x0F) << 28)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500555 | ((acttopre_mclk & 0x0F) << 24)
Dave Liu80ee3ce2008-11-21 16:31:22 +0800556 | ((acttorw_mclk & 0xF) << 20)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500557 | ((caslat_ctrl & 0xF) << 16)
558 | ((refrec_ctrl & 0xF) << 12)
Dave Liu80ee3ce2008-11-21 16:31:22 +0800559 | ((wrrec_mclk & 0x0F) << 8)
York Sun57495e42012-10-08 07:44:22 +0000560 | ((acttoact_mclk & 0x0F) << 4)
561 | ((wrtord_mclk & 0x0F) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500562 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400563 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500564}
565
566/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
567static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
568 const memctl_options_t *popts,
569 const common_timing_params_t *common_dimm,
570 unsigned int cas_latency,
571 unsigned int additive_latency)
572{
573 /* Additive latency */
574 unsigned char add_lat_mclk;
575 /* CAS-to-preamble override */
576 unsigned short cpo;
577 /* Write latency */
578 unsigned char wr_lat;
579 /* Read to precharge (tRTP) */
580 unsigned char rd_to_pre;
581 /* Write command to write data strobe timing adjustment */
582 unsigned char wr_data_delay;
583 /* Minimum CKE pulse width (tCKE) */
584 unsigned char cke_pls;
585 /* Window for four activates (tFAW) */
586 unsigned short four_act;
York Sunbb578322014-08-21 16:13:22 -0700587#ifdef CONFIG_SYS_FSL_DDR3
588 const unsigned int mclk_ps = get_memory_clk_period_ps();
589#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500590
591 /* FIXME add check that this must be less than acttorw_mclk */
592 add_lat_mclk = additive_latency;
593 cpo = popts->cpo_override;
594
York Sun5614e712013-09-30 09:22:09 -0700595#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500596 /*
597 * This is a lie. It should really be 1, but if it is
598 * set to 1, bits overlap into the old controller's
599 * otherwise unused ACSM field. If we leave it 0, then
600 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
601 */
602 wr_lat = 0;
York Sun5614e712013-09-30 09:22:09 -0700603#elif defined(CONFIG_SYS_FSL_DDR2)
Dave Liu6a819782009-03-14 12:48:19 +0800604 wr_lat = cas_latency - 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500605#else
Dave Liuc360cea2009-03-14 12:48:30 +0800606 wr_lat = compute_cas_write_latency();
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500607#endif
608
York Sun34e026f2014-03-27 17:54:47 -0700609#ifdef CONFIG_SYS_FSL_DDR4
610 rd_to_pre = picos_to_mclk(7500);
611#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530612 rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
York Sun34e026f2014-03-27 17:54:47 -0700613#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800614 /*
615 * JEDEC has some min requirements for tRTP
616 */
York Sun5614e712013-09-30 09:22:09 -0700617#if defined(CONFIG_SYS_FSL_DDR2)
Dave Liuc360cea2009-03-14 12:48:30 +0800618 if (rd_to_pre < 2)
619 rd_to_pre = 2;
York Sun34e026f2014-03-27 17:54:47 -0700620#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800621 if (rd_to_pre < 4)
622 rd_to_pre = 4;
Dave Liu6a819782009-03-14 12:48:19 +0800623#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530624 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800625 rd_to_pre += 2; /* according to UM */
626
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500627 wr_data_delay = popts->write_data_delay;
York Sun34e026f2014-03-27 17:54:47 -0700628#ifdef CONFIG_SYS_FSL_DDR4
629 cpo = 0;
630 cke_pls = max(3, picos_to_mclk(5000));
York Sunbb578322014-08-21 16:13:22 -0700631#elif defined(CONFIG_SYS_FSL_DDR3)
632 /*
633 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
634 * max(3nCK, 5.625ns) for DDR3-1066, 1333
635 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
636 */
637 cke_pls = max(3, picos_to_mclk(mclk_ps > 1870 ? 7500 :
638 (mclk_ps > 1245 ? 5625 : 5000)));
York Sun34e026f2014-03-27 17:54:47 -0700639#else
York Sunbb578322014-08-21 16:13:22 -0700640 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
York Sun34e026f2014-03-27 17:54:47 -0700641#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530642 four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500643
644 ddr->timing_cfg_2 = (0
Dave Liu22ff3d02008-11-21 16:31:29 +0800645 | ((add_lat_mclk & 0xf) << 28)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500646 | ((cpo & 0x1f) << 23)
Dave Liu22ff3d02008-11-21 16:31:29 +0800647 | ((wr_lat & 0xf) << 19)
York Sun34e026f2014-03-27 17:54:47 -0700648 | ((wr_lat & 0x10) << 14)
Dave Liuc360cea2009-03-14 12:48:30 +0800649 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
650 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500651 | ((cke_pls & 0x7) << 6)
Dave Liu22ff3d02008-11-21 16:31:29 +0800652 | ((four_act & 0x3f) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500653 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400654 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500655}
656
york9490ff42010-07-02 22:25:55 +0000657/* DDR SDRAM Register Control Word */
658static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000659 const memctl_options_t *popts,
york9490ff42010-07-02 22:25:55 +0000660 const common_timing_params_t *common_dimm)
661{
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530662 if (common_dimm->all_dimms_registered &&
663 !common_dimm->all_dimms_unbuffered) {
York Sune1fd16b2011-01-10 12:03:00 +0000664 if (popts->rcw_override) {
665 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
666 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
667 } else {
668 ddr->ddr_sdram_rcw_1 =
669 common_dimm->rcw[0] << 28 | \
670 common_dimm->rcw[1] << 24 | \
671 common_dimm->rcw[2] << 20 | \
672 common_dimm->rcw[3] << 16 | \
673 common_dimm->rcw[4] << 12 | \
674 common_dimm->rcw[5] << 8 | \
675 common_dimm->rcw[6] << 4 | \
676 common_dimm->rcw[7];
677 ddr->ddr_sdram_rcw_2 =
678 common_dimm->rcw[8] << 28 | \
679 common_dimm->rcw[9] << 24 | \
680 common_dimm->rcw[10] << 20 | \
681 common_dimm->rcw[11] << 16 | \
682 common_dimm->rcw[12] << 12 | \
683 common_dimm->rcw[13] << 8 | \
684 common_dimm->rcw[14] << 4 | \
685 common_dimm->rcw[15];
686 }
york9490ff42010-07-02 22:25:55 +0000687 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
688 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
689 }
690}
691
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500692/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
693static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
694 const memctl_options_t *popts,
695 const common_timing_params_t *common_dimm)
696{
697 unsigned int mem_en; /* DDR SDRAM interface logic enable */
698 unsigned int sren; /* Self refresh enable (during sleep) */
699 unsigned int ecc_en; /* ECC enable. */
700 unsigned int rd_en; /* Registered DIMM enable */
701 unsigned int sdram_type; /* Type of SDRAM */
702 unsigned int dyn_pwr; /* Dynamic power management mode */
703 unsigned int dbw; /* DRAM dta bus width */
Dave Liu22ff3d02008-11-21 16:31:29 +0800704 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500705 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530706 unsigned int threet_en; /* Enable 3T timing */
707 unsigned int twot_en; /* Enable 2T timing */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500708 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
709 unsigned int x32_en = 0; /* x32 enable */
710 unsigned int pchb8 = 0; /* precharge bit 8 enable */
711 unsigned int hse; /* Global half strength override */
York Sund28cb672014-09-05 13:52:41 +0800712 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500713 unsigned int mem_halt = 0; /* memory controller halt */
714 unsigned int bi = 0; /* Bypass initialization */
715
716 mem_en = 1;
717 sren = popts->self_refresh_in_sleep;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530718 if (common_dimm->all_dimms_ecc_capable) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500719 /* Allow setting of ECC only if all DIMMs are ECC. */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530720 ecc_en = popts->ecc_mode;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500721 } else {
722 ecc_en = 0;
723 }
724
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530725 if (common_dimm->all_dimms_registered &&
726 !common_dimm->all_dimms_unbuffered) {
York Sune1fd16b2011-01-10 12:03:00 +0000727 rd_en = 1;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530728 twot_en = 0;
York Sune1fd16b2011-01-10 12:03:00 +0000729 } else {
730 rd_en = 0;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530731 twot_en = popts->twot_en;
York Sune1fd16b2011-01-10 12:03:00 +0000732 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500733
734 sdram_type = CONFIG_FSL_SDRAM_TYPE;
735
736 dyn_pwr = popts->dynamic_power;
737 dbw = popts->data_bus_width;
Dave Liuc360cea2009-03-14 12:48:30 +0800738 /* 8-beat burst enable DDR-III case
739 * we must clear it when use the on-the-fly mode,
740 * must set it when use the 32-bits bus mode.
741 */
York Sun34e026f2014-03-27 17:54:47 -0700742 if ((sdram_type == SDRAM_TYPE_DDR3) ||
743 (sdram_type == SDRAM_TYPE_DDR4)) {
Dave Liuc360cea2009-03-14 12:48:30 +0800744 if (popts->burst_length == DDR_BL8)
745 eight_be = 1;
746 if (popts->burst_length == DDR_OTF)
747 eight_be = 0;
748 if (dbw == 0x1)
749 eight_be = 1;
750 }
751
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530752 threet_en = popts->threet_en;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500753 ba_intlv_ctl = popts->ba_intlv_ctl;
754 hse = popts->half_strength_driver_enable;
755
York Sund28cb672014-09-05 13:52:41 +0800756 /* set when ddr bus width < 64 */
757 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
758
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500759 ddr->ddr_sdram_cfg = (0
760 | ((mem_en & 0x1) << 31)
761 | ((sren & 0x1) << 30)
762 | ((ecc_en & 0x1) << 29)
763 | ((rd_en & 0x1) << 28)
764 | ((sdram_type & 0x7) << 24)
765 | ((dyn_pwr & 0x1) << 21)
766 | ((dbw & 0x3) << 19)
767 | ((eight_be & 0x1) << 18)
768 | ((ncap & 0x1) << 17)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530769 | ((threet_en & 0x1) << 16)
770 | ((twot_en & 0x1) << 15)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500771 | ((ba_intlv_ctl & 0x7F) << 8)
772 | ((x32_en & 0x1) << 5)
773 | ((pchb8 & 0x1) << 4)
774 | ((hse & 0x1) << 3)
York Sund28cb672014-09-05 13:52:41 +0800775 | ((acc_ecc_en & 0x1) << 2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500776 | ((mem_halt & 0x1) << 1)
777 | ((bi & 0x1) << 0)
778 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400779 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500780}
781
782/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
783static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000784 const memctl_options_t *popts,
785 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500786{
787 unsigned int frc_sr = 0; /* Force self refresh */
788 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
York Suncae7c1b2011-08-26 11:32:40 -0700789 unsigned int odt_cfg = 0; /* ODT configuration */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500790 unsigned int num_pr; /* Number of posted refreshes */
York Sun57495e42012-10-08 07:44:22 +0000791 unsigned int slow = 0; /* DDR will be run less than 1250 */
York Sunb61e0612013-06-25 11:37:47 -0700792 unsigned int x4_en = 0; /* x4 DRAM enable */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500793 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
794 unsigned int ap_en; /* Address Parity Enable */
795 unsigned int d_init; /* DRAM data initialization */
796 unsigned int rcw_en = 0; /* Register Control Word Enable */
797 unsigned int md_en = 0; /* Mirrored DIMM Enable */
york5800e7a2010-07-02 22:25:53 +0000798 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
York Suncae7c1b2011-08-26 11:32:40 -0700799 int i;
York Sun34e026f2014-03-27 17:54:47 -0700800#ifndef CONFIG_SYS_FSL_DDR4
801 unsigned int dll_rst_dis = 1; /* DLL reset disable */
802 unsigned int dqs_cfg; /* DQS configuration */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500803
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530804 dqs_cfg = popts->dqs_config;
York Sun34e026f2014-03-27 17:54:47 -0700805#endif
York Suncae7c1b2011-08-26 11:32:40 -0700806 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
807 if (popts->cs_local_opts[i].odt_rd_cfg
808 || popts->cs_local_opts[i].odt_wr_cfg) {
809 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
810 break;
811 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500812 }
813
814 num_pr = 1; /* Make this configurable */
815
816 /*
817 * 8572 manual says
818 * {TIMING_CFG_1[PRETOACT]
819 * + [DDR_SDRAM_CFG_2[NUM_PR]
820 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
821 * << DDR_SDRAM_INTERVAL[REFINT]
822 */
York Sun34e026f2014-03-27 17:54:47 -0700823#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530824 obc_cfg = popts->otf_burst_chop_en;
Dave Liuc360cea2009-03-14 12:48:30 +0800825#else
826 obc_cfg = 0;
827#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500828
York Sun57495e42012-10-08 07:44:22 +0000829#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
830 slow = get_ddr_freq(0) < 1249000000;
831#endif
832
York Sune1fd16b2011-01-10 12:03:00 +0000833 if (popts->registered_dimm_en) {
834 rcw_en = 1;
835 ap_en = popts->ap_en;
836 } else {
York Sune1fd16b2011-01-10 12:03:00 +0000837 ap_en = 0;
838 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500839
York Sunb61e0612013-06-25 11:37:47 -0700840 x4_en = popts->x4_en ? 1 : 0;
841
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500842#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
843 /* Use the DDR controller to auto initialize memory. */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530844 d_init = popts->ecc_init_using_memctl;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500845 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
846 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
847#else
848 /* Memory will be initialized via DMA, or not at all. */
849 d_init = 0;
850#endif
851
York Sun34e026f2014-03-27 17:54:47 -0700852#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800853 md_en = popts->mirrored_dimm;
854#endif
york5800e7a2010-07-02 22:25:53 +0000855 qd_en = popts->quad_rank_present ? 1 : 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500856 ddr->ddr_sdram_cfg_2 = (0
857 | ((frc_sr & 0x1) << 31)
858 | ((sr_ie & 0x1) << 30)
York Sun34e026f2014-03-27 17:54:47 -0700859#ifndef CONFIG_SYS_FSL_DDR4
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500860 | ((dll_rst_dis & 0x1) << 29)
861 | ((dqs_cfg & 0x3) << 26)
York Sun34e026f2014-03-27 17:54:47 -0700862#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500863 | ((odt_cfg & 0x3) << 21)
864 | ((num_pr & 0xf) << 12)
York Sun57495e42012-10-08 07:44:22 +0000865 | ((slow & 1) << 11)
York Sunb61e0612013-06-25 11:37:47 -0700866 | (x4_en << 10)
york5800e7a2010-07-02 22:25:53 +0000867 | (qd_en << 9)
York Sune1fd16b2011-01-10 12:03:00 +0000868 | (unq_mrs_en << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500869 | ((obc_cfg & 0x1) << 6)
870 | ((ap_en & 0x1) << 5)
871 | ((d_init & 0x1) << 4)
872 | ((rcw_en & 0x1) << 2)
873 | ((md_en & 0x1) << 0)
874 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400875 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500876}
877
York Sun34e026f2014-03-27 17:54:47 -0700878#ifdef CONFIG_SYS_FSL_DDR4
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500879/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
Dave Liu1aa3d082009-12-16 10:24:38 -0600880static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000881 const memctl_options_t *popts,
Valentin Longchamp7e157b02013-10-18 11:47:20 +0200882 const common_timing_params_t *common_dimm,
York Sune1fd16b2011-01-10 12:03:00 +0000883 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500884{
885 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
886 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
York Sun34e026f2014-03-27 17:54:47 -0700887 int i;
888 unsigned int wr_crc = 0; /* Disable */
889 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
890 unsigned int srt = 0; /* self-refresh temerature, normal range */
891 unsigned int cwl = compute_cas_write_latency() - 9;
892 unsigned int mpr = 0; /* serial */
893 unsigned int wc_lat;
894 const unsigned int mclk_ps = get_memory_clk_period_ps();
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500895
York Sun34e026f2014-03-27 17:54:47 -0700896 if (popts->rtt_override)
897 rtt_wr = popts->rtt_wr_override_value;
898 else
899 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
900
901 if (common_dimm->extended_op_srt)
902 srt = common_dimm->extended_op_srt;
903
904 esdmode2 = (0
905 | ((wr_crc & 0x1) << 12)
906 | ((rtt_wr & 0x3) << 9)
907 | ((srt & 0x3) << 6)
908 | ((cwl & 0x7) << 3));
909
910 if (mclk_ps >= 1250)
911 wc_lat = 0;
912 else if (mclk_ps >= 833)
913 wc_lat = 1;
914 else
915 wc_lat = 2;
916
917 esdmode3 = (0
918 | ((mpr & 0x3) << 11)
919 | ((wc_lat & 0x3) << 9));
920
921 ddr->ddr_sdram_mode_2 = (0
922 | ((esdmode2 & 0xFFFF) << 16)
923 | ((esdmode3 & 0xFFFF) << 0)
924 );
925 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
926
927 if (unq_mrs_en) { /* unique mode registers are supported */
928 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
929 if (popts->rtt_override)
930 rtt_wr = popts->rtt_wr_override_value;
931 else
932 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
933
934 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
935 esdmode2 |= (rtt_wr & 0x3) << 9;
936 switch (i) {
937 case 1:
938 ddr->ddr_sdram_mode_4 = (0
939 | ((esdmode2 & 0xFFFF) << 16)
940 | ((esdmode3 & 0xFFFF) << 0)
941 );
942 break;
943 case 2:
944 ddr->ddr_sdram_mode_6 = (0
945 | ((esdmode2 & 0xFFFF) << 16)
946 | ((esdmode3 & 0xFFFF) << 0)
947 );
948 break;
949 case 3:
950 ddr->ddr_sdram_mode_8 = (0
951 | ((esdmode2 & 0xFFFF) << 16)
952 | ((esdmode3 & 0xFFFF) << 0)
953 );
954 break;
955 }
956 }
957 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
958 ddr->ddr_sdram_mode_4);
959 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
960 ddr->ddr_sdram_mode_6);
961 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
962 ddr->ddr_sdram_mode_8);
963 }
964}
965#elif defined(CONFIG_SYS_FSL_DDR3)
966/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
967static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
968 const memctl_options_t *popts,
969 const common_timing_params_t *common_dimm,
970 const unsigned int unq_mrs_en)
971{
972 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
973 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
Kumar Gala92966832011-01-20 01:53:15 -0600974 int i;
Dave Liu1aa3d082009-12-16 10:24:38 -0600975 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
Dave Liuc360cea2009-03-14 12:48:30 +0800976 unsigned int srt = 0; /* self-refresh temerature, normal range */
977 unsigned int asr = 0; /* auto self-refresh disable */
978 unsigned int cwl = compute_cas_write_latency() - 5;
979 unsigned int pasr = 0; /* partial array self refresh disable */
980
Dave Liu1aa3d082009-12-16 10:24:38 -0600981 if (popts->rtt_override)
982 rtt_wr = popts->rtt_wr_override_value;
York Sune1fd16b2011-01-10 12:03:00 +0000983 else
984 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
Valentin Longchamp7e157b02013-10-18 11:47:20 +0200985
986 if (common_dimm->extended_op_srt)
987 srt = common_dimm->extended_op_srt;
988
Dave Liuc360cea2009-03-14 12:48:30 +0800989 esdmode2 = (0
990 | ((rtt_wr & 0x3) << 9)
991 | ((srt & 0x1) << 7)
992 | ((asr & 0x1) << 6)
993 | ((cwl & 0x7) << 3)
994 | ((pasr & 0x7) << 0));
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500995 ddr->ddr_sdram_mode_2 = (0
996 | ((esdmode2 & 0xFFFF) << 16)
997 | ((esdmode3 & 0xFFFF) << 0)
998 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400999 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
York Sune1fd16b2011-01-10 12:03:00 +00001000
York Sune1fd16b2011-01-10 12:03:00 +00001001 if (unq_mrs_en) { /* unique mode registers are supported */
Kumar Galadea7f882011-11-09 10:05:10 -06001002 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sune1fd16b2011-01-10 12:03:00 +00001003 if (popts->rtt_override)
1004 rtt_wr = popts->rtt_wr_override_value;
1005 else
1006 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1007
1008 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1009 esdmode2 |= (rtt_wr & 0x3) << 9;
1010 switch (i) {
1011 case 1:
1012 ddr->ddr_sdram_mode_4 = (0
1013 | ((esdmode2 & 0xFFFF) << 16)
1014 | ((esdmode3 & 0xFFFF) << 0)
1015 );
1016 break;
1017 case 2:
1018 ddr->ddr_sdram_mode_6 = (0
1019 | ((esdmode2 & 0xFFFF) << 16)
1020 | ((esdmode3 & 0xFFFF) << 0)
1021 );
1022 break;
1023 case 3:
1024 ddr->ddr_sdram_mode_8 = (0
1025 | ((esdmode2 & 0xFFFF) << 16)
1026 | ((esdmode3 & 0xFFFF) << 0)
1027 );
1028 break;
1029 }
1030 }
1031 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1032 ddr->ddr_sdram_mode_4);
1033 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1034 ddr->ddr_sdram_mode_6);
1035 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1036 ddr->ddr_sdram_mode_8);
1037 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001038}
1039
York Sun34e026f2014-03-27 17:54:47 -07001040#else /* for DDR2 and DDR1 */
1041/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1042static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
1043 const memctl_options_t *popts,
1044 const common_timing_params_t *common_dimm,
1045 const unsigned int unq_mrs_en)
1046{
1047 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1048 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1049
1050 ddr->ddr_sdram_mode_2 = (0
1051 | ((esdmode2 & 0xFFFF) << 16)
1052 | ((esdmode3 & 0xFFFF) << 0)
1053 );
1054 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1055}
1056#endif
1057
1058#ifdef CONFIG_SYS_FSL_DDR4
1059/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1060static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1061 const memctl_options_t *popts,
1062 const common_timing_params_t *common_dimm,
1063 const unsigned int unq_mrs_en)
1064{
1065 int i;
1066 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1067 unsigned short esdmode5; /* Extended SDRAM mode 5 */
1068
1069 esdmode5 = 0x00000400; /* Data mask enabled */
1070
1071 ddr->ddr_sdram_mode_9 = (0
1072 | ((esdmode4 & 0xffff) << 16)
1073 | ((esdmode5 & 0xffff) << 0)
1074 );
1075 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1076 if (unq_mrs_en) { /* unique mode registers are supported */
1077 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1078 switch (i) {
1079 case 1:
1080 ddr->ddr_sdram_mode_11 = (0
1081 | ((esdmode4 & 0xFFFF) << 16)
1082 | ((esdmode5 & 0xFFFF) << 0)
1083 );
1084 break;
1085 case 2:
1086 ddr->ddr_sdram_mode_13 = (0
1087 | ((esdmode4 & 0xFFFF) << 16)
1088 | ((esdmode5 & 0xFFFF) << 0)
1089 );
1090 break;
1091 case 3:
1092 ddr->ddr_sdram_mode_15 = (0
1093 | ((esdmode4 & 0xFFFF) << 16)
1094 | ((esdmode5 & 0xFFFF) << 0)
1095 );
1096 break;
1097 }
1098 }
1099 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1100 ddr->ddr_sdram_mode_11);
1101 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1102 ddr->ddr_sdram_mode_13);
1103 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1104 ddr->ddr_sdram_mode_15);
1105 }
1106}
1107
1108/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1109static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
1110 const memctl_options_t *popts,
1111 const common_timing_params_t *common_dimm,
1112 const unsigned int unq_mrs_en)
1113{
1114 int i;
1115 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1116 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
1117 unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
1118
1119 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1120
1121 ddr->ddr_sdram_mode_10 = (0
1122 | ((esdmode6 & 0xffff) << 16)
1123 | ((esdmode7 & 0xffff) << 0)
1124 );
1125 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1126 if (unq_mrs_en) { /* unique mode registers are supported */
1127 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1128 switch (i) {
1129 case 1:
1130 ddr->ddr_sdram_mode_12 = (0
1131 | ((esdmode6 & 0xFFFF) << 16)
1132 | ((esdmode7 & 0xFFFF) << 0)
1133 );
1134 break;
1135 case 2:
1136 ddr->ddr_sdram_mode_14 = (0
1137 | ((esdmode6 & 0xFFFF) << 16)
1138 | ((esdmode7 & 0xFFFF) << 0)
1139 );
1140 break;
1141 case 3:
1142 ddr->ddr_sdram_mode_16 = (0
1143 | ((esdmode6 & 0xFFFF) << 16)
1144 | ((esdmode7 & 0xFFFF) << 0)
1145 );
1146 break;
1147 }
1148 }
1149 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1150 ddr->ddr_sdram_mode_12);
1151 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1152 ddr->ddr_sdram_mode_14);
1153 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1154 ddr->ddr_sdram_mode_16);
1155 }
1156}
1157
1158#endif
1159
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001160/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1161static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
1162 const memctl_options_t *popts,
1163 const common_timing_params_t *common_dimm)
1164{
1165 unsigned int refint; /* Refresh interval */
1166 unsigned int bstopre; /* Precharge interval */
1167
1168 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
1169
1170 bstopre = popts->bstopre;
1171
1172 /* refint field used 0x3FFF in earlier controllers */
1173 ddr->ddr_sdram_interval = (0
1174 | ((refint & 0xFFFF) << 16)
1175 | ((bstopre & 0x3FFF) << 0)
1176 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001177 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001178}
1179
York Sun34e026f2014-03-27 17:54:47 -07001180#ifdef CONFIG_SYS_FSL_DDR4
Dave Liuc360cea2009-03-14 12:48:30 +08001181/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1182static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1183 const memctl_options_t *popts,
1184 const common_timing_params_t *common_dimm,
1185 unsigned int cas_latency,
York Sune1fd16b2011-01-10 12:03:00 +00001186 unsigned int additive_latency,
1187 const unsigned int unq_mrs_en)
Dave Liuc360cea2009-03-14 12:48:30 +08001188{
York Sun34e026f2014-03-27 17:54:47 -07001189 int i;
1190 unsigned short esdmode; /* Extended SDRAM mode */
1191 unsigned short sdmode; /* SDRAM mode */
1192
1193 /* Mode Register - MR1 */
1194 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1195 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1196 unsigned int rtt;
1197 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1198 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1199 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1200 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1201 0=Disable (Test/Debug) */
1202
1203 /* Mode Register - MR0 */
1204 unsigned int wr = 0; /* Write Recovery */
1205 unsigned int dll_rst; /* DLL Reset */
1206 unsigned int mode; /* Normal=0 or Test=1 */
1207 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1208 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1209 unsigned int bt;
1210 unsigned int bl; /* BL: Burst Length */
1211
1212 unsigned int wr_mclk;
1213 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1214 static const u8 wr_table[] = {
1215 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1216 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1217 static const u8 cas_latency_table[] = {
1218 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1219 9, 9, 10, 10, 11, 11};
1220
1221 if (popts->rtt_override)
1222 rtt = popts->rtt_override_value;
1223 else
1224 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1225
1226 if (additive_latency == (cas_latency - 1))
1227 al = 1;
1228 if (additive_latency == (cas_latency - 2))
1229 al = 2;
1230
1231 if (popts->quad_rank_present)
1232 dic = 1; /* output driver impedance 240/7 ohm */
1233
1234 /*
1235 * The esdmode value will also be used for writing
1236 * MR1 during write leveling for DDR3, although the
1237 * bits specifically related to the write leveling
1238 * scheme will be handled automatically by the DDR
1239 * controller. so we set the wrlvl_en = 0 here.
1240 */
1241 esdmode = (0
1242 | ((qoff & 0x1) << 12)
1243 | ((tdqs_en & 0x1) << 11)
1244 | ((rtt & 0x7) << 8)
1245 | ((wrlvl_en & 0x1) << 7)
1246 | ((al & 0x3) << 3)
1247 | ((dic & 0x3) << 1) /* DIC field is split */
1248 | ((dll_en & 0x1) << 0)
1249 );
1250
1251 /*
1252 * DLL control for precharge PD
1253 * 0=slow exit DLL off (tXPDLL)
1254 * 1=fast exit DLL on (tXP)
1255 */
1256
1257 wr_mclk = picos_to_mclk(common_dimm->twr_ps);
1258 if (wr_mclk <= 24) {
1259 wr = wr_table[wr_mclk - 10];
1260 } else {
1261 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1262 wr_mclk);
1263 }
1264
1265 dll_rst = 0; /* dll no reset */
1266 mode = 0; /* normal mode */
1267
1268 /* look up table to get the cas latency bits */
1269 if (cas_latency >= 9 && cas_latency <= 24)
1270 caslat = cas_latency_table[cas_latency - 9];
1271 else
1272 printf("Error: unsupported cas latency for mode register\n");
1273
1274 bt = 0; /* Nibble sequential */
1275
1276 switch (popts->burst_length) {
1277 case DDR_BL8:
1278 bl = 0;
1279 break;
1280 case DDR_OTF:
1281 bl = 1;
1282 break;
1283 case DDR_BC4:
1284 bl = 2;
1285 break;
1286 default:
1287 printf("Error: invalid burst length of %u specified. ",
1288 popts->burst_length);
1289 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1290 bl = 1;
1291 break;
1292 }
1293
1294 sdmode = (0
1295 | ((wr & 0x7) << 9)
1296 | ((dll_rst & 0x1) << 8)
1297 | ((mode & 0x1) << 7)
1298 | (((caslat >> 1) & 0x7) << 4)
1299 | ((bt & 0x1) << 3)
1300 | ((caslat & 1) << 2)
1301 | ((bl & 0x3) << 0)
1302 );
1303
1304 ddr->ddr_sdram_mode = (0
1305 | ((esdmode & 0xFFFF) << 16)
1306 | ((sdmode & 0xFFFF) << 0)
1307 );
1308
1309 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1310
1311 if (unq_mrs_en) { /* unique mode registers are supported */
1312 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1313 if (popts->rtt_override)
1314 rtt = popts->rtt_override_value;
1315 else
1316 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1317
1318 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1319 esdmode |= (rtt & 0x7) << 8;
1320 switch (i) {
1321 case 1:
1322 ddr->ddr_sdram_mode_3 = (0
1323 | ((esdmode & 0xFFFF) << 16)
1324 | ((sdmode & 0xFFFF) << 0)
1325 );
1326 break;
1327 case 2:
1328 ddr->ddr_sdram_mode_5 = (0
1329 | ((esdmode & 0xFFFF) << 16)
1330 | ((sdmode & 0xFFFF) << 0)
1331 );
1332 break;
1333 case 3:
1334 ddr->ddr_sdram_mode_7 = (0
1335 | ((esdmode & 0xFFFF) << 16)
1336 | ((sdmode & 0xFFFF) << 0)
1337 );
1338 break;
1339 }
1340 }
1341 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1342 ddr->ddr_sdram_mode_3);
1343 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1344 ddr->ddr_sdram_mode_5);
1345 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1346 ddr->ddr_sdram_mode_5);
1347 }
1348}
1349
1350#elif defined(CONFIG_SYS_FSL_DDR3)
1351/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1352static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1353 const memctl_options_t *popts,
1354 const common_timing_params_t *common_dimm,
1355 unsigned int cas_latency,
1356 unsigned int additive_latency,
1357 const unsigned int unq_mrs_en)
1358{
1359 int i;
Dave Liuc360cea2009-03-14 12:48:30 +08001360 unsigned short esdmode; /* Extended SDRAM mode */
1361 unsigned short sdmode; /* SDRAM mode */
1362
1363 /* Mode Register - MR1 */
1364 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1365 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1366 unsigned int rtt;
1367 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1368 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
York Sune1fd16b2011-01-10 12:03:00 +00001369 unsigned int dic = 0; /* Output driver impedance, 40ohm */
Dave Liuc360cea2009-03-14 12:48:30 +08001370 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1371 1=Disable (Test/Debug) */
1372
1373 /* Mode Register - MR0 */
1374 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
York Sunfcea3062012-08-17 08:22:38 +00001375 unsigned int wr = 0; /* Write Recovery */
Dave Liuc360cea2009-03-14 12:48:30 +08001376 unsigned int dll_rst; /* DLL Reset */
1377 unsigned int mode; /* Normal=0 or Test=1 */
1378 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1379 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1380 unsigned int bt;
1381 unsigned int bl; /* BL: Burst Length */
1382
1383 unsigned int wr_mclk;
York Sunf5b6fb72011-03-02 14:24:11 -08001384 /*
1385 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1386 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1387 * for this table
1388 */
1389 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
Dave Liuc360cea2009-03-14 12:48:30 +08001390
Dave Liuc360cea2009-03-14 12:48:30 +08001391 if (popts->rtt_override)
1392 rtt = popts->rtt_override_value;
York Sune1fd16b2011-01-10 12:03:00 +00001393 else
1394 rtt = popts->cs_local_opts[0].odt_rtt_norm;
Dave Liuc360cea2009-03-14 12:48:30 +08001395
1396 if (additive_latency == (cas_latency - 1))
1397 al = 1;
1398 if (additive_latency == (cas_latency - 2))
1399 al = 2;
1400
York Sune1fd16b2011-01-10 12:03:00 +00001401 if (popts->quad_rank_present)
1402 dic = 1; /* output driver impedance 240/7 ohm */
1403
Dave Liuc360cea2009-03-14 12:48:30 +08001404 /*
1405 * The esdmode value will also be used for writing
1406 * MR1 during write leveling for DDR3, although the
1407 * bits specifically related to the write leveling
1408 * scheme will be handled automatically by the DDR
1409 * controller. so we set the wrlvl_en = 0 here.
1410 */
1411 esdmode = (0
1412 | ((qoff & 0x1) << 12)
1413 | ((tdqs_en & 0x1) << 11)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001414 | ((rtt & 0x4) << 7) /* rtt field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001415 | ((wrlvl_en & 0x1) << 7)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001416 | ((rtt & 0x2) << 5) /* rtt field is split */
1417 | ((dic & 0x2) << 4) /* DIC field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001418 | ((al & 0x3) << 3)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001419 | ((rtt & 0x1) << 2) /* rtt field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001420 | ((dic & 0x1) << 1) /* DIC field is split */
1421 | ((dll_en & 0x1) << 0)
1422 );
1423
1424 /*
1425 * DLL control for precharge PD
1426 * 0=slow exit DLL off (tXPDLL)
1427 * 1=fast exit DLL on (tXP)
1428 */
1429 dll_on = 1;
York Sunf5b6fb72011-03-02 14:24:11 -08001430
York Sun34e026f2014-03-27 17:54:47 -07001431 wr_mclk = picos_to_mclk(common_dimm->twr_ps);
York Sunfcea3062012-08-17 08:22:38 +00001432 if (wr_mclk <= 16) {
1433 wr = wr_table[wr_mclk - 5];
1434 } else {
1435 printf("Error: unsupported write recovery for mode register "
1436 "wr_mclk = %d\n", wr_mclk);
1437 }
York Sunf5b6fb72011-03-02 14:24:11 -08001438
Dave Liuc360cea2009-03-14 12:48:30 +08001439 dll_rst = 0; /* dll no reset */
1440 mode = 0; /* normal mode */
1441
1442 /* look up table to get the cas latency bits */
York Sunfcea3062012-08-17 08:22:38 +00001443 if (cas_latency >= 5 && cas_latency <= 16) {
1444 unsigned char cas_latency_table[] = {
Dave Liuc360cea2009-03-14 12:48:30 +08001445 0x2, /* 5 clocks */
1446 0x4, /* 6 clocks */
1447 0x6, /* 7 clocks */
1448 0x8, /* 8 clocks */
1449 0xa, /* 9 clocks */
1450 0xc, /* 10 clocks */
York Sunfcea3062012-08-17 08:22:38 +00001451 0xe, /* 11 clocks */
1452 0x1, /* 12 clocks */
1453 0x3, /* 13 clocks */
1454 0x5, /* 14 clocks */
1455 0x7, /* 15 clocks */
1456 0x9, /* 16 clocks */
Dave Liuc360cea2009-03-14 12:48:30 +08001457 };
1458 caslat = cas_latency_table[cas_latency - 5];
York Sunfcea3062012-08-17 08:22:38 +00001459 } else {
1460 printf("Error: unsupported cas latency for mode register\n");
Dave Liuc360cea2009-03-14 12:48:30 +08001461 }
York Sunfcea3062012-08-17 08:22:38 +00001462
Dave Liuc360cea2009-03-14 12:48:30 +08001463 bt = 0; /* Nibble sequential */
1464
1465 switch (popts->burst_length) {
1466 case DDR_BL8:
1467 bl = 0;
1468 break;
1469 case DDR_OTF:
1470 bl = 1;
1471 break;
1472 case DDR_BC4:
1473 bl = 2;
1474 break;
1475 default:
1476 printf("Error: invalid burst length of %u specified. "
1477 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1478 popts->burst_length);
1479 bl = 1;
1480 break;
1481 }
1482
1483 sdmode = (0
1484 | ((dll_on & 0x1) << 12)
1485 | ((wr & 0x7) << 9)
1486 | ((dll_rst & 0x1) << 8)
1487 | ((mode & 0x1) << 7)
1488 | (((caslat >> 1) & 0x7) << 4)
1489 | ((bt & 0x1) << 3)
York Sunfcea3062012-08-17 08:22:38 +00001490 | ((caslat & 1) << 2)
Dave Liuc360cea2009-03-14 12:48:30 +08001491 | ((bl & 0x3) << 0)
1492 );
1493
1494 ddr->ddr_sdram_mode = (0
1495 | ((esdmode & 0xFFFF) << 16)
1496 | ((sdmode & 0xFFFF) << 0)
1497 );
1498
1499 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
York Sune1fd16b2011-01-10 12:03:00 +00001500
1501 if (unq_mrs_en) { /* unique mode registers are supported */
Kumar Galadea7f882011-11-09 10:05:10 -06001502 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sune1fd16b2011-01-10 12:03:00 +00001503 if (popts->rtt_override)
1504 rtt = popts->rtt_override_value;
1505 else
1506 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1507
1508 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1509 esdmode |= (0
1510 | ((rtt & 0x4) << 7) /* rtt field is split */
1511 | ((rtt & 0x2) << 5) /* rtt field is split */
1512 | ((rtt & 0x1) << 2) /* rtt field is split */
1513 );
1514 switch (i) {
1515 case 1:
1516 ddr->ddr_sdram_mode_3 = (0
1517 | ((esdmode & 0xFFFF) << 16)
1518 | ((sdmode & 0xFFFF) << 0)
1519 );
1520 break;
1521 case 2:
1522 ddr->ddr_sdram_mode_5 = (0
1523 | ((esdmode & 0xFFFF) << 16)
1524 | ((sdmode & 0xFFFF) << 0)
1525 );
1526 break;
1527 case 3:
1528 ddr->ddr_sdram_mode_7 = (0
1529 | ((esdmode & 0xFFFF) << 16)
1530 | ((sdmode & 0xFFFF) << 0)
1531 );
1532 break;
1533 }
1534 }
1535 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1536 ddr->ddr_sdram_mode_3);
1537 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1538 ddr->ddr_sdram_mode_5);
1539 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1540 ddr->ddr_sdram_mode_5);
1541 }
Dave Liuc360cea2009-03-14 12:48:30 +08001542}
1543
York Sun5614e712013-09-30 09:22:09 -07001544#else /* !CONFIG_SYS_FSL_DDR3 */
Dave Liuc360cea2009-03-14 12:48:30 +08001545
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001546/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1547static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1548 const memctl_options_t *popts,
1549 const common_timing_params_t *common_dimm,
1550 unsigned int cas_latency,
York Sune1fd16b2011-01-10 12:03:00 +00001551 unsigned int additive_latency,
1552 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001553{
1554 unsigned short esdmode; /* Extended SDRAM mode */
1555 unsigned short sdmode; /* SDRAM mode */
1556
1557 /*
1558 * FIXME: This ought to be pre-calculated in a
1559 * technology-specific routine,
1560 * e.g. compute_DDR2_mode_register(), and then the
1561 * sdmode and esdmode passed in as part of common_dimm.
1562 */
1563
1564 /* Extended Mode Register */
1565 unsigned int mrs = 0; /* Mode Register Set */
1566 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1567 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1568 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1569 unsigned int ocd = 0; /* 0x0=OCD not supported,
1570 0x7=OCD default state */
1571 unsigned int rtt;
1572 unsigned int al; /* Posted CAS# additive latency (AL) */
1573 unsigned int ods = 0; /* Output Drive Strength:
1574 0 = Full strength (18ohm)
1575 1 = Reduced strength (4ohm) */
1576 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1577 1=Disable (Test/Debug) */
1578
1579 /* Mode Register (MR) */
1580 unsigned int mr; /* Mode Register Definition */
1581 unsigned int pd; /* Power-Down Mode */
1582 unsigned int wr; /* Write Recovery */
1583 unsigned int dll_res; /* DLL Reset */
1584 unsigned int mode; /* Normal=0 or Test=1 */
Kumar Gala302e52e2008-09-05 14:40:29 -05001585 unsigned int caslat = 0;/* CAS# latency */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001586 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1587 unsigned int bt;
1588 unsigned int bl; /* BL: Burst Length */
1589
Priyanka Jain0dd38a32013-09-25 10:41:19 +05301590 dqs_en = !popts->dqs_config;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001591 rtt = fsl_ddr_get_rtt();
1592
1593 al = additive_latency;
1594
1595 esdmode = (0
1596 | ((mrs & 0x3) << 14)
1597 | ((outputs & 0x1) << 12)
1598 | ((rdqs_en & 0x1) << 11)
1599 | ((dqs_en & 0x1) << 10)
1600 | ((ocd & 0x7) << 7)
1601 | ((rtt & 0x2) << 5) /* rtt field is split */
1602 | ((al & 0x7) << 3)
1603 | ((rtt & 0x1) << 2) /* rtt field is split */
1604 | ((ods & 0x1) << 1)
1605 | ((dll_en & 0x1) << 0)
1606 );
1607
1608 mr = 0; /* FIXME: CHECKME */
1609
1610 /*
1611 * 0 = Fast Exit (Normal)
1612 * 1 = Slow Exit (Low Power)
1613 */
1614 pd = 0;
1615
York Sun5614e712013-09-30 09:22:09 -07001616#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001617 wr = 0; /* Historical */
York Sun5614e712013-09-30 09:22:09 -07001618#elif defined(CONFIG_SYS_FSL_DDR2)
York Sun34e026f2014-03-27 17:54:47 -07001619 wr = picos_to_mclk(common_dimm->twr_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001620#endif
1621 dll_res = 0;
1622 mode = 0;
1623
York Sun5614e712013-09-30 09:22:09 -07001624#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001625 if (1 <= cas_latency && cas_latency <= 4) {
1626 unsigned char mode_caslat_table[4] = {
1627 0x5, /* 1.5 clocks */
1628 0x2, /* 2.0 clocks */
1629 0x6, /* 2.5 clocks */
1630 0x3 /* 3.0 clocks */
1631 };
Kumar Gala302e52e2008-09-05 14:40:29 -05001632 caslat = mode_caslat_table[cas_latency - 1];
1633 } else {
1634 printf("Warning: unknown cas_latency %d\n", cas_latency);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001635 }
York Sun5614e712013-09-30 09:22:09 -07001636#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001637 caslat = cas_latency;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001638#endif
1639 bt = 0;
1640
1641 switch (popts->burst_length) {
Dave Liuc360cea2009-03-14 12:48:30 +08001642 case DDR_BL4:
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001643 bl = 2;
1644 break;
Dave Liuc360cea2009-03-14 12:48:30 +08001645 case DDR_BL8:
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001646 bl = 3;
1647 break;
1648 default:
1649 printf("Error: invalid burst length of %u specified. "
1650 " Defaulting to 4 beats.\n",
1651 popts->burst_length);
1652 bl = 2;
1653 break;
1654 }
1655
1656 sdmode = (0
1657 | ((mr & 0x3) << 14)
1658 | ((pd & 0x1) << 12)
1659 | ((wr & 0x7) << 9)
1660 | ((dll_res & 0x1) << 8)
1661 | ((mode & 0x1) << 7)
1662 | ((caslat & 0x7) << 4)
1663 | ((bt & 0x1) << 3)
1664 | ((bl & 0x7) << 0)
1665 );
1666
1667 ddr->ddr_sdram_mode = (0
1668 | ((esdmode & 0xFFFF) << 16)
1669 | ((sdmode & 0xFFFF) << 0)
1670 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001671 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001672}
Dave Liuc360cea2009-03-14 12:48:30 +08001673#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001674
1675/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1676static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1677{
1678 unsigned int init_value; /* Initialization value */
1679
Anatolij Gustschin5b933942013-01-21 23:50:27 +00001680#ifdef CONFIG_MEM_INIT_VALUE
1681 init_value = CONFIG_MEM_INIT_VALUE;
1682#else
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001683 init_value = 0xDEADBEEF;
Anatolij Gustschin5b933942013-01-21 23:50:27 +00001684#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001685 ddr->ddr_data_init = init_value;
1686}
1687
1688/*
1689 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1690 * The old controller on the 8540/60 doesn't have this register.
1691 * Hope it's OK to set it (to 0) anyway.
1692 */
1693static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1694 const memctl_options_t *popts)
1695{
1696 unsigned int clk_adjust; /* Clock adjust */
1697
1698 clk_adjust = popts->clk_adjust;
1699 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
york9490ff42010-07-02 22:25:55 +00001700 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001701}
1702
1703/* DDR Initialization Address (DDR_INIT_ADDR) */
1704static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1705{
1706 unsigned int init_addr = 0; /* Initialization address */
1707
1708 ddr->ddr_init_addr = init_addr;
1709}
1710
1711/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1712static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1713{
1714 unsigned int uia = 0; /* Use initialization address */
1715 unsigned int init_ext_addr = 0; /* Initialization address */
1716
1717 ddr->ddr_init_ext_addr = (0
1718 | ((uia & 0x1) << 31)
1719 | (init_ext_addr & 0xF)
1720 );
1721}
1722
1723/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
Dave Liuec145e82010-03-05 12:22:00 +08001724static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1725 const memctl_options_t *popts)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001726{
1727 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1728 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1729 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1730 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1731 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1732
York Sun34e026f2014-03-27 17:54:47 -07001733#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuec145e82010-03-05 12:22:00 +08001734 if (popts->burst_length == DDR_BL8) {
1735 /* We set BL/2 for fixed BL8 */
1736 rrt = 0; /* BL/2 clocks */
1737 wwt = 0; /* BL/2 clocks */
1738 } else {
1739 /* We need to set BL/2 + 2 to BC4 and OTF */
1740 rrt = 2; /* BL/2 + 2 clocks */
1741 wwt = 2; /* BL/2 + 2 clocks */
1742 }
York Sun34e026f2014-03-27 17:54:47 -07001743#endif
1744
1745#ifdef CONFIG_SYS_FSL_DDR4
1746 dll_lock = 2; /* tDLLK = 1024 clocks */
1747#elif defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +08001748 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1749#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001750 ddr->timing_cfg_4 = (0
1751 | ((rwt & 0xf) << 28)
1752 | ((wrt & 0xf) << 24)
1753 | ((rrt & 0xf) << 20)
1754 | ((wwt & 0xf) << 16)
1755 | (dll_lock & 0x3)
1756 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001757 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001758}
1759
1760/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
York Sune1fd16b2011-01-10 12:03:00 +00001761static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001762{
1763 unsigned int rodt_on = 0; /* Read to ODT on */
1764 unsigned int rodt_off = 0; /* Read to ODT off */
1765 unsigned int wodt_on = 0; /* Write to ODT on */
1766 unsigned int wodt_off = 0; /* Write to ODT off */
1767
York Sun34e026f2014-03-27 17:54:47 -07001768#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1769 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1770 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
York Sune1fd16b2011-01-10 12:03:00 +00001771 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
York Sun34e026f2014-03-27 17:54:47 -07001772 if (cas_latency >= wr_lat)
1773 rodt_on = cas_latency - wr_lat + 1;
Dave Liuc360cea2009-03-14 12:48:30 +08001774 rodt_off = 4; /* 4 clocks */
york5fb8a8a2010-07-02 22:25:56 +00001775 wodt_on = 1; /* 1 clocks */
Dave Liuc360cea2009-03-14 12:48:30 +08001776 wodt_off = 4; /* 4 clocks */
1777#endif
1778
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001779 ddr->timing_cfg_5 = (0
Dave Liu22ff3d02008-11-21 16:31:29 +08001780 | ((rodt_on & 0x1f) << 24)
1781 | ((rodt_off & 0x7) << 20)
1782 | ((wodt_on & 0x1f) << 12)
1783 | ((wodt_off & 0x7) << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001784 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001785 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001786}
1787
York Sun34e026f2014-03-27 17:54:47 -07001788#ifdef CONFIG_SYS_FSL_DDR4
1789static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1790{
1791 unsigned int hs_caslat = 0;
1792 unsigned int hs_wrlat = 0;
1793 unsigned int hs_wrrec = 0;
1794 unsigned int hs_clkadj = 0;
1795 unsigned int hs_wrlvl_start = 0;
1796
1797 ddr->timing_cfg_6 = (0
1798 | ((hs_caslat & 0x1f) << 24)
1799 | ((hs_wrlat & 0x1f) << 19)
1800 | ((hs_wrrec & 0x1f) << 12)
1801 | ((hs_clkadj & 0x1f) << 6)
1802 | ((hs_wrlvl_start & 0x1f) << 0)
1803 );
1804 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1805}
1806
1807static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
1808 const common_timing_params_t *common_dimm)
1809{
1810 unsigned int txpr, tcksre, tcksrx;
1811 unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1812
1813 txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000));
1814 tcksre = max(5, picos_to_mclk(10000));
1815 tcksrx = max(5, picos_to_mclk(10000));
1816 par_lat = 0;
1817 cs_to_cmd = 0;
1818
1819 if (txpr <= 200)
1820 cke_rst = 0;
1821 else if (txpr <= 256)
1822 cke_rst = 1;
1823 else if (txpr <= 512)
1824 cke_rst = 2;
1825 else
1826 cke_rst = 3;
1827
1828 if (tcksre <= 19)
1829 cksre = tcksre - 5;
1830 else
1831 cksre = 15;
1832
1833 if (tcksrx <= 19)
1834 cksrx = tcksrx - 5;
1835 else
1836 cksrx = 15;
1837
1838 ddr->timing_cfg_7 = (0
1839 | ((cke_rst & 0x3) << 28)
1840 | ((cksre & 0xf) << 24)
1841 | ((cksrx & 0xf) << 20)
1842 | ((par_lat & 0xf) << 16)
1843 | ((cs_to_cmd & 0xf) << 4)
1844 );
1845 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1846}
1847
1848static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
1849 const memctl_options_t *popts,
1850 const common_timing_params_t *common_dimm,
1851 unsigned int cas_latency)
1852{
1853 unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1854 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1855 unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
1856 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1857 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1858
1859 rwt_bg = cas_latency + 2 + 4 - wr_lat;
1860 if (rwt_bg < tccdl)
1861 rwt_bg = tccdl - rwt_bg;
1862 else
1863 rwt_bg = 0;
1864
1865 wrt_bg = wr_lat + 4 + 1 - cas_latency;
1866 if (wrt_bg < tccdl)
1867 wrt_bg = tccdl - wrt_bg;
1868 else
1869 wrt_bg = 0;
1870
1871 if (popts->burst_length == DDR_BL8) {
1872 rrt_bg = tccdl - 4;
1873 wwt_bg = tccdl - 4;
1874 } else {
1875 rrt_bg = tccdl - 2;
1876 wwt_bg = tccdl - 4;
1877 }
1878
1879 acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
1880 wrtord_bg = max(4, picos_to_mclk(7500));
York Sun3d75ec92014-06-26 11:14:44 -07001881 if (popts->otf_burst_chop_en)
1882 wrtord_bg += 2;
1883
York Sun34e026f2014-03-27 17:54:47 -07001884 pre_all_rec = 0;
1885
1886 ddr->timing_cfg_8 = (0
1887 | ((rwt_bg & 0xf) << 28)
1888 | ((wrt_bg & 0xf) << 24)
1889 | ((rrt_bg & 0xf) << 20)
1890 | ((wwt_bg & 0xf) << 16)
1891 | ((acttoact_bg & 0xf) << 12)
1892 | ((wrtord_bg & 0xf) << 8)
1893 | ((pre_all_rec & 0x1f) << 0)
1894 );
1895
1896 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1897}
1898
1899static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1900{
1901 ddr->timing_cfg_9 = 0;
1902 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1903}
1904
1905static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1906 const dimm_params_t *dimm_params)
1907{
1908 ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
1909 ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
1910 ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
1911 ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
1912 ((dimm_params->dq_mapping[4] & 0x3F) << 2);
1913
1914 ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
1915 ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
1916 ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
1917 ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
1918 ((dimm_params->dq_mapping[11] & 0x3F) << 2);
1919
1920 ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
1921 ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
1922 ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
1923 ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
1924 ((dimm_params->dq_mapping[16] & 0x3F) << 2);
1925
1926 ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
1927 ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
1928 ((dimm_params->dq_mapping[9] & 0x3F) << 14) |
1929 dimm_params->dq_mapping_ors;
1930
1931 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
1932 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
1933 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
1934 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
1935}
1936static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
1937 const memctl_options_t *popts)
1938{
1939 int rd_pre;
1940
1941 rd_pre = popts->quad_rank_present ? 1 : 0;
1942
1943 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
1944
1945 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
1946}
1947#endif /* CONFIG_SYS_FSL_DDR4 */
1948
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001949/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
Dave Liuc360cea2009-03-14 12:48:30 +08001950static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001951{
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001952 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1953 /* Normal Operation Full Calibration Time (tZQoper) */
1954 unsigned int zqoper = 0;
1955 /* Normal Operation Short Calibration Time (tZQCS) */
1956 unsigned int zqcs = 0;
York Sun34e026f2014-03-27 17:54:47 -07001957#ifdef CONFIG_SYS_FSL_DDR4
1958 unsigned int zqcs_init;
1959#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001960
Dave Liuc360cea2009-03-14 12:48:30 +08001961 if (zq_en) {
York Sun34e026f2014-03-27 17:54:47 -07001962#ifdef CONFIG_SYS_FSL_DDR4
1963 zqinit = 10; /* 1024 clocks */
1964 zqoper = 9; /* 512 clocks */
1965 zqcs = 7; /* 128 clocks */
1966 zqcs_init = 5; /* 1024 refresh sequences */
1967#else
Dave Liuc360cea2009-03-14 12:48:30 +08001968 zqinit = 9; /* 512 clocks */
1969 zqoper = 8; /* 256 clocks */
1970 zqcs = 6; /* 64 clocks */
York Sun34e026f2014-03-27 17:54:47 -07001971#endif
Dave Liuc360cea2009-03-14 12:48:30 +08001972 }
1973
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001974 ddr->ddr_zq_cntl = (0
1975 | ((zq_en & 0x1) << 31)
1976 | ((zqinit & 0xF) << 24)
1977 | ((zqoper & 0xF) << 16)
1978 | ((zqcs & 0xF) << 8)
York Sun34e026f2014-03-27 17:54:47 -07001979#ifdef CONFIG_SYS_FSL_DDR4
1980 | ((zqcs_init & 0xF) << 0)
1981#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001982 );
York Sune1fd16b2011-01-10 12:03:00 +00001983 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001984}
1985
1986/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
Dave Liubdc9f7b2009-12-16 10:24:37 -06001987static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1988 const memctl_options_t *popts)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001989{
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001990 /*
1991 * First DQS pulse rising edge after margining mode
1992 * is programmed (tWL_MRD)
1993 */
1994 unsigned int wrlvl_mrd = 0;
1995 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1996 unsigned int wrlvl_odten = 0;
1997 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1998 unsigned int wrlvl_dqsen = 0;
1999 /* WRLVL_SMPL: Write leveling sample time */
2000 unsigned int wrlvl_smpl = 0;
2001 /* WRLVL_WLR: Write leveling repeition time */
2002 unsigned int wrlvl_wlr = 0;
2003 /* WRLVL_START: Write leveling start time */
2004 unsigned int wrlvl_start = 0;
2005
Dave Liuc360cea2009-03-14 12:48:30 +08002006 /* suggest enable write leveling for DDR3 due to fly-by topology */
2007 if (wrlvl_en) {
2008 /* tWL_MRD min = 40 nCK, we set it 64 */
2009 wrlvl_mrd = 0x6;
2010 /* tWL_ODTEN 128 */
2011 wrlvl_odten = 0x7;
2012 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2013 wrlvl_dqsen = 0x5;
2014 /*
Dave Liubdc9f7b2009-12-16 10:24:37 -06002015 * Write leveling sample time at least need 6 clocks
2016 * higher than tWLO to allow enough time for progagation
2017 * delay and sampling the prime data bits.
Dave Liuc360cea2009-03-14 12:48:30 +08002018 */
2019 wrlvl_smpl = 0xf;
2020 /*
2021 * Write leveling repetition time
2022 * at least tWLO + 6 clocks clocks
york5fb8a8a2010-07-02 22:25:56 +00002023 * we set it 64
Dave Liuc360cea2009-03-14 12:48:30 +08002024 */
york5fb8a8a2010-07-02 22:25:56 +00002025 wrlvl_wlr = 0x6;
Dave Liuc360cea2009-03-14 12:48:30 +08002026 /*
2027 * Write leveling start time
2028 * The value use for the DQS_ADJUST for the first sample
York Sune1fd16b2011-01-10 12:03:00 +00002029 * when write leveling is enabled. It probably needs to be
2030 * overriden per platform.
Dave Liuc360cea2009-03-14 12:48:30 +08002031 */
2032 wrlvl_start = 0x8;
Dave Liubdc9f7b2009-12-16 10:24:37 -06002033 /*
2034 * Override the write leveling sample and start time
2035 * according to specific board
2036 */
2037 if (popts->wrlvl_override) {
2038 wrlvl_smpl = popts->wrlvl_sample;
2039 wrlvl_start = popts->wrlvl_start;
2040 }
Dave Liuc360cea2009-03-14 12:48:30 +08002041 }
2042
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002043 ddr->ddr_wrlvl_cntl = (0
2044 | ((wrlvl_en & 0x1) << 31)
2045 | ((wrlvl_mrd & 0x7) << 24)
2046 | ((wrlvl_odten & 0x7) << 20)
2047 | ((wrlvl_dqsen & 0x7) << 16)
2048 | ((wrlvl_smpl & 0xf) << 12)
2049 | ((wrlvl_wlr & 0x7) << 8)
Dave Liu22ff3d02008-11-21 16:31:29 +08002050 | ((wrlvl_start & 0x1F) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002051 );
York Sune1fd16b2011-01-10 12:03:00 +00002052 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
York Sun57495e42012-10-08 07:44:22 +00002053 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2054 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2055 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2056 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2057
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002058}
2059
2060/* DDR Self Refresh Counter (DDR_SR_CNTR) */
Dave Liu22cca7e2008-11-21 16:31:35 +08002061static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002062{
Dave Liu22cca7e2008-11-21 16:31:35 +08002063 /* Self Refresh Idle Threshold */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002064 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2065}
2066
york7fd101c2010-07-02 22:25:54 +00002067static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2068{
2069 if (popts->addr_hash) {
2070 ddr->ddr_eor = 0x40000000; /* address hash enable */
Kumar Galac2a63f42011-03-18 11:53:06 -05002071 puts("Address hashing enabled.\n");
york7fd101c2010-07-02 22:25:54 +00002072 }
2073}
2074
York Sune1fd16b2011-01-10 12:03:00 +00002075static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2076{
2077 ddr->ddr_cdr1 = popts->ddr_cdr1;
2078 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2079}
2080
York Sun57495e42012-10-08 07:44:22 +00002081static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2082{
2083 ddr->ddr_cdr2 = popts->ddr_cdr2;
2084 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2085}
2086
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002087unsigned int
2088check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2089{
2090 unsigned int res = 0;
2091
2092 /*
2093 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2094 * not set at the same time.
2095 */
2096 if (ddr->ddr_sdram_cfg & 0x10000000
2097 && ddr->ddr_sdram_cfg & 0x00008000) {
2098 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2099 " should not be set at the same time.\n");
2100 res++;
2101 }
2102
2103 return res;
2104}
2105
2106unsigned int
2107compute_fsl_memctl_config_regs(const memctl_options_t *popts,
2108 fsl_ddr_cfg_regs_t *ddr,
2109 const common_timing_params_t *common_dimm,
2110 const dimm_params_t *dimm_params,
Haiying Wangfc0c2b62010-12-01 10:35:31 -05002111 unsigned int dbw_cap_adj,
2112 unsigned int size_only)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002113{
2114 unsigned int i;
2115 unsigned int cas_latency;
2116 unsigned int additive_latency;
Dave Liu22cca7e2008-11-21 16:31:35 +08002117 unsigned int sr_it;
Dave Liuc360cea2009-03-14 12:48:30 +08002118 unsigned int zq_en;
2119 unsigned int wrlvl_en;
York Sune1fd16b2011-01-10 12:03:00 +00002120 unsigned int ip_rev = 0;
2121 unsigned int unq_mrs_en = 0;
York Sun58edbc92010-10-18 13:46:50 -07002122 int cs_en = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002123
2124 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2125
2126 if (common_dimm == NULL) {
2127 printf("Error: subset DIMM params struct null pointer\n");
2128 return 1;
2129 }
2130
2131 /*
2132 * Process overrides first.
2133 *
2134 * FIXME: somehow add dereated caslat to this
2135 */
2136 cas_latency = (popts->cas_latency_override)
2137 ? popts->cas_latency_override_value
York Sun34e026f2014-03-27 17:54:47 -07002138 : common_dimm->lowest_common_spd_caslat;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002139
2140 additive_latency = (popts->additive_latency_override)
2141 ? popts->additive_latency_override_value
2142 : common_dimm->additive_latency;
2143
Dave Liu22cca7e2008-11-21 16:31:35 +08002144 sr_it = (popts->auto_self_refresh_en)
2145 ? popts->sr_it
2146 : 0;
Dave Liuc360cea2009-03-14 12:48:30 +08002147 /* ZQ calibration */
2148 zq_en = (popts->zq_en) ? 1 : 0;
2149 /* write leveling */
2150 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
Dave Liu22cca7e2008-11-21 16:31:35 +08002151
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002152 /* Chip Select Memory Bounds (CSn_BNDS) */
2153 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Suna4c66502012-08-17 08:22:39 +00002154 unsigned long long ea, sa;
york076bff82010-07-02 22:25:52 +00002155 unsigned int cs_per_dimm
2156 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2157 unsigned int dimm_number
2158 = i / cs_per_dimm;
2159 unsigned long long rank_density
York Suna4c66502012-08-17 08:22:39 +00002160 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002161
york076bff82010-07-02 22:25:52 +00002162 if (dimm_params[dimm_number].n_ranks == 0) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002163 debug("Skipping setup of CS%u "
york5800e7a2010-07-02 22:25:53 +00002164 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002165 continue;
2166 }
York Suna4c66502012-08-17 08:22:39 +00002167 if (popts->memctl_interleaving) {
york076bff82010-07-02 22:25:52 +00002168 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
York Suna4c66502012-08-17 08:22:39 +00002169 case FSL_DDR_CS0_CS1_CS2_CS3:
2170 break;
york076bff82010-07-02 22:25:52 +00002171 case FSL_DDR_CS0_CS1:
2172 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
York Sun58edbc92010-10-18 13:46:50 -07002173 if (i > 1)
2174 cs_en = 0;
york076bff82010-07-02 22:25:52 +00002175 break;
2176 case FSL_DDR_CS2_CS3:
York Suna4c66502012-08-17 08:22:39 +00002177 default:
York Sun58edbc92010-10-18 13:46:50 -07002178 if (i > 0)
2179 cs_en = 0;
york076bff82010-07-02 22:25:52 +00002180 break;
york076bff82010-07-02 22:25:52 +00002181 }
York Suna4c66502012-08-17 08:22:39 +00002182 sa = common_dimm->base_address;
York Sun123922b2012-10-08 07:44:23 +00002183 ea = sa + common_dimm->total_mem - 1;
York Suna4c66502012-08-17 08:22:39 +00002184 } else if (!popts->memctl_interleaving) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002185 /*
2186 * If memory interleaving between controllers is NOT
2187 * enabled, the starting address for each memory
2188 * controller is distinct. However, because rank
2189 * interleaving is enabled, the starting and ending
2190 * addresses of the total memory on that memory
2191 * controller needs to be programmed into its
2192 * respective CS0_BNDS.
2193 */
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002194 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2195 case FSL_DDR_CS0_CS1_CS2_CS3:
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002196 sa = common_dimm->base_address;
York Sun123922b2012-10-08 07:44:23 +00002197 ea = sa + common_dimm->total_mem - 1;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002198 break;
2199 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
York Suna4c66502012-08-17 08:22:39 +00002200 if ((i >= 2) && (dimm_number == 0)) {
york076bff82010-07-02 22:25:52 +00002201 sa = dimm_params[dimm_number].base_address +
York Suna4c66502012-08-17 08:22:39 +00002202 2 * rank_density;
2203 ea = sa + 2 * rank_density - 1;
york076bff82010-07-02 22:25:52 +00002204 } else {
2205 sa = dimm_params[dimm_number].base_address;
York Suna4c66502012-08-17 08:22:39 +00002206 ea = sa + 2 * rank_density - 1;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002207 }
2208 break;
2209 case FSL_DDR_CS0_CS1:
york076bff82010-07-02 22:25:52 +00002210 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2211 sa = dimm_params[dimm_number].base_address;
York Suna4c66502012-08-17 08:22:39 +00002212 ea = sa + rank_density - 1;
2213 if (i != 1)
2214 sa += (i % cs_per_dimm) * rank_density;
2215 ea += (i % cs_per_dimm) * rank_density;
york076bff82010-07-02 22:25:52 +00002216 } else {
2217 sa = 0;
2218 ea = 0;
2219 }
2220 if (i == 0)
York Suna4c66502012-08-17 08:22:39 +00002221 ea += rank_density;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002222 break;
2223 case FSL_DDR_CS2_CS3:
york076bff82010-07-02 22:25:52 +00002224 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2225 sa = dimm_params[dimm_number].base_address;
York Suna4c66502012-08-17 08:22:39 +00002226 ea = sa + rank_density - 1;
2227 if (i != 3)
2228 sa += (i % cs_per_dimm) * rank_density;
2229 ea += (i % cs_per_dimm) * rank_density;
york076bff82010-07-02 22:25:52 +00002230 } else {
2231 sa = 0;
2232 ea = 0;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002233 }
york076bff82010-07-02 22:25:52 +00002234 if (i == 2)
2235 ea += (rank_density >> dbw_cap_adj);
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002236 break;
2237 default: /* No bank(chip-select) interleaving */
York Suna4c66502012-08-17 08:22:39 +00002238 sa = dimm_params[dimm_number].base_address;
2239 ea = sa + rank_density - 1;
2240 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2241 sa += (i % cs_per_dimm) * rank_density;
2242 ea += (i % cs_per_dimm) * rank_density;
2243 } else {
2244 sa = 0;
2245 ea = 0;
2246 }
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002247 break;
2248 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002249 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002250
2251 sa >>= 24;
2252 ea >>= 24;
2253
York Sun123922b2012-10-08 07:44:23 +00002254 if (cs_en) {
2255 ddr->cs[i].bnds = (0
York Sund4263b82013-06-03 12:39:06 -07002256 | ((sa & 0xffff) << 16) /* starting address */
2257 | ((ea & 0xffff) << 0) /* ending address */
York Sun123922b2012-10-08 07:44:23 +00002258 );
2259 } else {
York Sund8556db2013-06-25 11:37:45 -07002260 /* setting bnds to 0xffffffff for inactive CS */
2261 ddr->cs[i].bnds = 0xffffffff;
York Sun123922b2012-10-08 07:44:23 +00002262 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002263
Haiying Wang1f293b42008-10-03 12:37:26 -04002264 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
York Sun123922b2012-10-08 07:44:23 +00002265 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2266 set_csn_config_2(i, ddr);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002267 }
2268
Haiying Wangfc0c2b62010-12-01 10:35:31 -05002269 /*
2270 * In the case we only need to compute the ddr sdram size, we only need
2271 * to set csn registers, so return from here.
2272 */
2273 if (size_only)
2274 return 0;
2275
york7fd101c2010-07-02 22:25:54 +00002276 set_ddr_eor(ddr, popts);
2277
York Sun5614e712013-09-30 09:22:09 -07002278#if !defined(CONFIG_SYS_FSL_DDR1)
York Sun123922b2012-10-08 07:44:23 +00002279 set_timing_cfg_0(ddr, popts, dimm_params);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002280#endif
2281
York Sund4263b82013-06-03 12:39:06 -07002282 set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
2283 additive_latency);
Dave Liuc360cea2009-03-14 12:48:30 +08002284 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002285 set_timing_cfg_2(ddr, popts, common_dimm,
2286 cas_latency, additive_latency);
2287
York Sune1fd16b2011-01-10 12:03:00 +00002288 set_ddr_cdr1(ddr, popts);
York Sun57495e42012-10-08 07:44:22 +00002289 set_ddr_cdr2(ddr, popts);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002290 set_ddr_sdram_cfg(ddr, popts, common_dimm);
York Sune1fd16b2011-01-10 12:03:00 +00002291 ip_rev = fsl_ddr_get_version();
2292 if (ip_rev > 0x40400)
2293 unq_mrs_en = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002294
York Sunef87cab2014-09-05 13:52:43 +08002295 if (ip_rev > 0x40700)
2296 ddr->debug[18] = popts->cswl_override;
2297
York Sune1fd16b2011-01-10 12:03:00 +00002298 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002299 set_ddr_sdram_mode(ddr, popts, common_dimm,
York Sune1fd16b2011-01-10 12:03:00 +00002300 cas_latency, additive_latency, unq_mrs_en);
Valentin Longchamp7e157b02013-10-18 11:47:20 +02002301 set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
York Sun34e026f2014-03-27 17:54:47 -07002302#ifdef CONFIG_SYS_FSL_DDR4
2303 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2304 set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
2305#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002306 set_ddr_sdram_interval(ddr, popts, common_dimm);
2307 set_ddr_data_init(ddr);
2308 set_ddr_sdram_clk_cntl(ddr, popts);
2309 set_ddr_init_addr(ddr);
2310 set_ddr_init_ext_addr(ddr);
Dave Liuec145e82010-03-05 12:22:00 +08002311 set_timing_cfg_4(ddr, popts);
York Sune1fd16b2011-01-10 12:03:00 +00002312 set_timing_cfg_5(ddr, cas_latency);
York Sun34e026f2014-03-27 17:54:47 -07002313#ifdef CONFIG_SYS_FSL_DDR4
2314 set_ddr_sdram_cfg_3(ddr, popts);
2315 set_timing_cfg_6(ddr);
2316 set_timing_cfg_7(ddr, common_dimm);
2317 set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
2318 set_timing_cfg_9(ddr);
2319 set_ddr_dq_mapping(ddr, dimm_params);
2320#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002321
Dave Liuc360cea2009-03-14 12:48:30 +08002322 set_ddr_zq_cntl(ddr, zq_en);
Dave Liubdc9f7b2009-12-16 10:24:37 -06002323 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002324
Dave Liu22cca7e2008-11-21 16:31:35 +08002325 set_ddr_sr_cntr(ddr, sr_it);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002326
York Sune1fd16b2011-01-10 12:03:00 +00002327 set_ddr_sdram_rcw(ddr, popts, common_dimm);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002328
York Suncb930712013-06-25 11:37:41 -07002329#ifdef CONFIG_SYS_FSL_DDR_EMU
2330 /* disble DDR training for emulator */
2331 ddr->debug[2] = 0x00000400;
2332 ddr->debug[4] = 0xff800000;
2333#endif
York Sun9855b3b2014-05-23 13:15:00 -07002334#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2335 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2336 ddr->debug[2] |= 0x00000200; /* set bit 22 */
2337#endif
2338
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002339 return check_fsl_memctl_config_regs(ddr);
2340}