blob: 78e82bba3d4302a3f34efe1ea0df8a70b0c406fc [file] [log] [blame]
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001/*
York Sun34e026f2014-03-27 17:54:47 -07002 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala58e5e9a2008-08-26 15:01:29 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala58e5e9a2008-08-26 15:01:29 -05005 */
6
7/*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13#include <common.h>
York Sun5614e712013-09-30 09:22:09 -070014#include <fsl_ddr_sdram.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050015
York Sun5614e712013-09-30 09:22:09 -070016#include <fsl_ddr.h>
York Sun9a17eb52013-11-18 10:29:32 -080017#include <fsl_immap.h>
York Sun5614e712013-09-30 09:22:09 -070018#include <asm/io.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050019
York Sune1fd16b2011-01-10 12:03:00 +000020unsigned int picos_to_mclk(unsigned int picos);
21
Kumar Gala58e5e9a2008-08-26 15:01:29 -050022/*
23 * Determine Rtt value.
24 *
25 * This should likely be either board or controller specific.
26 *
Dave Liuc360cea2009-03-14 12:48:30 +080027 * Rtt(nominal) - DDR2:
Kumar Gala58e5e9a2008-08-26 15:01:29 -050028 * 0 = Rtt disabled
29 * 1 = 75 ohm
30 * 2 = 150 ohm
31 * 3 = 50 ohm
Dave Liuc360cea2009-03-14 12:48:30 +080032 * Rtt(nominal) - DDR3:
33 * 0 = Rtt disabled
34 * 1 = 60 ohm
35 * 2 = 120 ohm
36 * 3 = 40 ohm
37 * 4 = 20 ohm
38 * 5 = 30 ohm
Kumar Gala58e5e9a2008-08-26 15:01:29 -050039 *
40 * FIXME: Apparently 8641 needs a value of 2
41 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
42 *
43 * FIXME: There was some effort down this line earlier:
44 *
45 * unsigned int i;
46 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
47 * if (popts->dimmslot[i].num_valid_cs
48 * && (popts->cs_local_opts[2*i].odt_rd_cfg
49 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
50 * rtt = 2;
51 * break;
52 * }
53 * }
54 */
55static inline int fsl_ddr_get_rtt(void)
56{
57 int rtt;
58
York Sun5614e712013-09-30 09:22:09 -070059#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050060 rtt = 0;
York Sun5614e712013-09-30 09:22:09 -070061#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050062 rtt = 3;
63#else
Dave Liuc360cea2009-03-14 12:48:30 +080064 rtt = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -050065#endif
66
67 return rtt;
68}
69
York Sun34e026f2014-03-27 17:54:47 -070070#ifdef CONFIG_SYS_FSL_DDR4
71/*
72 * compute CAS write latency according to DDR4 spec
73 * CWL = 9 for <= 1600MT/s
74 * 10 for <= 1866MT/s
75 * 11 for <= 2133MT/s
76 * 12 for <= 2400MT/s
77 * 14 for <= 2667MT/s
78 * 16 for <= 2933MT/s
79 * 18 for higher
80 */
81static inline unsigned int compute_cas_write_latency(void)
82{
83 unsigned int cwl;
84 const unsigned int mclk_ps = get_memory_clk_period_ps();
85 if (mclk_ps >= 1250)
86 cwl = 9;
87 else if (mclk_ps >= 1070)
88 cwl = 10;
89 else if (mclk_ps >= 935)
90 cwl = 11;
91 else if (mclk_ps >= 833)
92 cwl = 12;
93 else if (mclk_ps >= 750)
94 cwl = 14;
95 else if (mclk_ps >= 681)
96 cwl = 16;
97 else
98 cwl = 18;
99
100 return cwl;
101}
102#else
Dave Liuc360cea2009-03-14 12:48:30 +0800103/*
104 * compute the CAS write latency according to DDR3 spec
105 * CWL = 5 if tCK >= 2.5ns
106 * 6 if 2.5ns > tCK >= 1.875ns
107 * 7 if 1.875ns > tCK >= 1.5ns
108 * 8 if 1.5ns > tCK >= 1.25ns
York Sun2bba85f2011-08-24 09:40:25 -0700109 * 9 if 1.25ns > tCK >= 1.07ns
110 * 10 if 1.07ns > tCK >= 0.935ns
111 * 11 if 0.935ns > tCK >= 0.833ns
112 * 12 if 0.833ns > tCK >= 0.75ns
Dave Liuc360cea2009-03-14 12:48:30 +0800113 */
114static inline unsigned int compute_cas_write_latency(void)
115{
116 unsigned int cwl;
117 const unsigned int mclk_ps = get_memory_clk_period_ps();
118
119 if (mclk_ps >= 2500)
120 cwl = 5;
121 else if (mclk_ps >= 1875)
122 cwl = 6;
123 else if (mclk_ps >= 1500)
124 cwl = 7;
125 else if (mclk_ps >= 1250)
126 cwl = 8;
York Sun2bba85f2011-08-24 09:40:25 -0700127 else if (mclk_ps >= 1070)
128 cwl = 9;
129 else if (mclk_ps >= 935)
130 cwl = 10;
131 else if (mclk_ps >= 833)
132 cwl = 11;
133 else if (mclk_ps >= 750)
134 cwl = 12;
135 else {
136 cwl = 12;
137 printf("Warning: CWL is out of range\n");
138 }
Dave Liuc360cea2009-03-14 12:48:30 +0800139 return cwl;
140}
York Sun34e026f2014-03-27 17:54:47 -0700141#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800142
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500143/* Chip Select Configuration (CSn_CONFIG) */
york5800e7a2010-07-02 22:25:53 +0000144static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500145 const memctl_options_t *popts,
146 const dimm_params_t *dimm_params)
147{
148 unsigned int cs_n_en = 0; /* Chip Select enable */
149 unsigned int intlv_en = 0; /* Memory controller interleave enable */
150 unsigned int intlv_ctl = 0; /* Interleaving control */
151 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
152 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
153 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
154 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
155 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
156 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
york5800e7a2010-07-02 22:25:53 +0000157 int go_config = 0;
York Sun34e026f2014-03-27 17:54:47 -0700158#ifdef CONFIG_SYS_FSL_DDR4
159 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
160#else
161 unsigned int n_banks_per_sdram_device;
162#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500163
164 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
york5800e7a2010-07-02 22:25:53 +0000165 switch (i) {
166 case 0:
167 if (dimm_params[dimm_number].n_ranks > 0) {
168 go_config = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500169 /* These fields only available in CS0_CONFIG */
York Suna4c66502012-08-17 08:22:39 +0000170 if (!popts->memctl_interleaving)
171 break;
172 switch (popts->memctl_interleaving_mode) {
York Sun6b1e1252014-02-10 13:59:44 -0800173 case FSL_DDR_256B_INTERLEAVING:
York Suna4c66502012-08-17 08:22:39 +0000174 case FSL_DDR_CACHE_LINE_INTERLEAVING:
175 case FSL_DDR_PAGE_INTERLEAVING:
176 case FSL_DDR_BANK_INTERLEAVING:
177 case FSL_DDR_SUPERBANK_INTERLEAVING:
178 intlv_en = popts->memctl_interleaving;
179 intlv_ctl = popts->memctl_interleaving_mode;
180 break;
181 default:
182 break;
183 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500184 }
york5800e7a2010-07-02 22:25:53 +0000185 break;
186 case 1:
187 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
188 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
189 go_config = 1;
190 break;
191 case 2:
192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
York Suncae7c1b2011-08-26 11:32:40 -0700193 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
york5800e7a2010-07-02 22:25:53 +0000194 go_config = 1;
195 break;
196 case 3:
197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
198 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
199 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
200 go_config = 1;
201 break;
202 default:
203 break;
204 }
205 if (go_config) {
york5800e7a2010-07-02 22:25:53 +0000206 cs_n_en = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500207 ap_n_en = popts->cs_local_opts[i].auto_precharge;
208 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
209 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
York Sun34e026f2014-03-27 17:54:47 -0700210#ifdef CONFIG_SYS_FSL_DDR4
211 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
212 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
213#else
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500214 n_banks_per_sdram_device
york5800e7a2010-07-02 22:25:53 +0000215 = dimm_params[dimm_number].n_banks_per_sdram_device;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500216 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
York Sun34e026f2014-03-27 17:54:47 -0700217#endif
york5800e7a2010-07-02 22:25:53 +0000218 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
219 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500220 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500221 ddr->cs[i].config = (0
222 | ((cs_n_en & 0x1) << 31)
223 | ((intlv_en & 0x3) << 29)
Haiying Wangdbbbb3a2008-10-03 12:36:39 -0400224 | ((intlv_ctl & 0xf) << 24)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500225 | ((ap_n_en & 0x1) << 23)
226
227 /* XXX: some implementation only have 1 bit starting at left */
228 | ((odt_rd_cfg & 0x7) << 20)
229
230 /* XXX: Some implementation only have 1 bit starting at left */
231 | ((odt_wr_cfg & 0x7) << 16)
232
233 | ((ba_bits_cs_n & 0x3) << 14)
234 | ((row_bits_cs_n & 0x7) << 8)
York Sun34e026f2014-03-27 17:54:47 -0700235#ifdef CONFIG_SYS_FSL_DDR4
236 | ((bg_bits_cs_n & 0x3) << 4)
237#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500238 | ((col_bits_cs_n & 0x7) << 0)
239 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400240 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500241}
242
243/* Chip Select Configuration 2 (CSn_CONFIG_2) */
244/* FIXME: 8572 */
245static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
246{
247 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
248
249 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
Haiying Wang1f293b42008-10-03 12:37:26 -0400250 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500251}
252
253/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
254
York Sun5614e712013-09-30 09:22:09 -0700255#if !defined(CONFIG_SYS_FSL_DDR1)
York Sun123922b2012-10-08 07:44:23 +0000256static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
257{
258#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
259 if (dimm_params[0].n_ranks == 4)
260 return 1;
261#endif
262
263#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
264 if ((dimm_params[0].n_ranks == 2) &&
265 (dimm_params[1].n_ranks == 2))
266 return 1;
267
268#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
269 if (dimm_params[0].n_ranks == 4)
270 return 1;
271#endif
272#endif
273 return 0;
274}
275
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500276/*
277 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
278 *
279 * Avoid writing for DDR I. The new PQ38 DDR controller
280 * dreams up non-zero default values to be backwards compatible.
281 */
York Sune1fd16b2011-01-10 12:03:00 +0000282static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
York Sun123922b2012-10-08 07:44:23 +0000283 const memctl_options_t *popts,
284 const dimm_params_t *dimm_params)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500285{
286 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
287 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
288 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
289 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
290 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
291
292 /* Active powerdown exit timing (tXARD and tXARDS). */
293 unsigned char act_pd_exit_mclk;
294 /* Precharge powerdown exit timing (tXP). */
295 unsigned char pre_pd_exit_mclk;
york5fb8a8a2010-07-02 22:25:56 +0000296 /* ODT powerdown exit timing (tAXPD). */
York Sun34e026f2014-03-27 17:54:47 -0700297 unsigned char taxpd_mclk = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500298 /* Mode register set cycle time (tMRD). */
299 unsigned char tmrd_mclk;
300
York Sun34e026f2014-03-27 17:54:47 -0700301#ifdef CONFIG_SYS_FSL_DDR4
302 /* tXP=max(4nCK, 6ns) */
303 int txp = max((get_memory_clk_period_ps() * 4), 6000); /* unit=ps */
304 trwt_mclk = 2;
305 twrt_mclk = 1;
306 act_pd_exit_mclk = picos_to_mclk(txp);
307 pre_pd_exit_mclk = act_pd_exit_mclk;
308 /*
309 * MRS_CYC = max(tMRD, tMOD)
310 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
311 */
312 tmrd_mclk = max(24, picos_to_mclk(15000));
313#elif defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +0800314 /*
315 * (tXARD and tXARDS). Empirical?
316 * The DDR3 spec has not tXARD,
317 * we use the tXP instead of it.
318 * tXP=max(3nCK, 7.5ns) for DDR3.
Dave Liuc360cea2009-03-14 12:48:30 +0800319 * spec has not the tAXPD, we use
york5fb8a8a2010-07-02 22:25:56 +0000320 * tAXPD=1, need design to confirm.
Dave Liuc360cea2009-03-14 12:48:30 +0800321 */
York Sun34e026f2014-03-27 17:54:47 -0700322 int txp = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
Kumar Gala5df4b0a2011-01-31 20:36:02 -0600323 unsigned int data_rate = get_ddr_freq(0);
Dave Liuc360cea2009-03-14 12:48:30 +0800324 tmrd_mclk = 4;
Dave Liu99bac472009-12-08 11:56:48 +0800325 /* set the turnaround time */
York Sun123922b2012-10-08 07:44:23 +0000326
327 /*
328 * for single quad-rank DIMM and two dual-rank DIMMs
329 * to avoid ODT overlap
330 */
331 if (avoid_odt_overlap(dimm_params)) {
332 twwt_mclk = 2;
333 trrt_mclk = 1;
334 }
335 /* for faster clock, need more time for data setup */
336 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
337
York Sun856e4b02011-02-10 10:13:10 -0800338 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
339 twrt_mclk = 1;
York Sune1fd16b2011-01-10 12:03:00 +0000340
341 if (popts->dynamic_power == 0) { /* powerdown is not used */
342 act_pd_exit_mclk = 1;
343 pre_pd_exit_mclk = 1;
344 taxpd_mclk = 1;
345 } else {
346 /* act_pd_exit_mclk = tXARD, see above */
York Sun34e026f2014-03-27 17:54:47 -0700347 act_pd_exit_mclk = picos_to_mclk(txp);
York Sune1fd16b2011-01-10 12:03:00 +0000348 /* Mode register MR0[A12] is '1' - fast exit */
349 pre_pd_exit_mclk = act_pd_exit_mclk;
350 taxpd_mclk = 1;
351 }
York Sun5614e712013-09-30 09:22:09 -0700352#else /* CONFIG_SYS_FSL_DDR2 */
Dave Liuc360cea2009-03-14 12:48:30 +0800353 /*
354 * (tXARD and tXARDS). Empirical?
355 * tXARD = 2 for DDR2
356 * tXP=2
357 * tAXPD=8
358 */
359 act_pd_exit_mclk = 2;
360 pre_pd_exit_mclk = 2;
361 taxpd_mclk = 8;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500362 tmrd_mclk = 2;
Dave Liuc360cea2009-03-14 12:48:30 +0800363#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500364
York Sun23f96702011-05-27 13:44:28 +0800365 if (popts->trwt_override)
366 trwt_mclk = popts->trwt;
367
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500368 ddr->timing_cfg_0 = (0
369 | ((trwt_mclk & 0x3) << 30) /* RWT */
370 | ((twrt_mclk & 0x3) << 28) /* WRT */
371 | ((trrt_mclk & 0x3) << 26) /* RRT */
372 | ((twwt_mclk & 0x3) << 24) /* WWT */
York Sund4263b82013-06-03 12:39:06 -0700373 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
Dave Liu22ff3d02008-11-21 16:31:29 +0800374 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500375 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
York Sund4263b82013-06-03 12:39:06 -0700376 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500377 );
378 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
379}
York Sun5614e712013-09-30 09:22:09 -0700380#endif /* defined(CONFIG_SYS_FSL_DDR2) */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500381
382/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
383static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
York Sun45064ad2012-08-17 08:22:40 +0000384 const memctl_options_t *popts,
Dave Liuc360cea2009-03-14 12:48:30 +0800385 const common_timing_params_t *common_dimm,
York Sund4263b82013-06-03 12:39:06 -0700386 unsigned int cas_latency,
387 unsigned int additive_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500388{
York Sun45064ad2012-08-17 08:22:40 +0000389 /* Extended precharge to activate interval (tRP) */
390 unsigned int ext_pretoact = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500391 /* Extended Activate to precharge interval (tRAS) */
392 unsigned int ext_acttopre = 0;
York Sun45064ad2012-08-17 08:22:40 +0000393 /* Extended activate to read/write interval (tRCD) */
394 unsigned int ext_acttorw = 0;
395 /* Extended refresh recovery time (tRFC) */
396 unsigned int ext_refrec;
397 /* Extended MCAS latency from READ cmd */
398 unsigned int ext_caslat = 0;
York Sund4263b82013-06-03 12:39:06 -0700399 /* Extended additive latency */
400 unsigned int ext_add_lat = 0;
York Sun45064ad2012-08-17 08:22:40 +0000401 /* Extended last data to precharge interval (tWR) */
402 unsigned int ext_wrrec = 0;
403 /* Control Adjust */
404 unsigned int cntl_adj = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500405
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530406 ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
407 ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
408 ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
York Sun45064ad2012-08-17 08:22:40 +0000409 ext_caslat = (2 * cas_latency - 1) >> 4;
York Sund4263b82013-06-03 12:39:06 -0700410 ext_add_lat = additive_latency >> 4;
York Sun34e026f2014-03-27 17:54:47 -0700411#ifdef CONFIG_SYS_FSL_DDR4
412 ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
413#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530414 ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
York Sun45064ad2012-08-17 08:22:40 +0000415 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
York Sun34e026f2014-03-27 17:54:47 -0700416#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530417 ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
418 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
Dave Liuc360cea2009-03-14 12:48:30 +0800419
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500420 ddr->timing_cfg_3 = (0
York Sun45064ad2012-08-17 08:22:40 +0000421 | ((ext_pretoact & 0x1) << 28)
James Yangc45f5c02013-07-22 09:35:26 -0700422 | ((ext_acttopre & 0x3) << 24)
York Sun45064ad2012-08-17 08:22:40 +0000423 | ((ext_acttorw & 0x1) << 22)
424 | ((ext_refrec & 0x1F) << 16)
425 | ((ext_caslat & 0x3) << 12)
York Sund4263b82013-06-03 12:39:06 -0700426 | ((ext_add_lat & 0x1) << 10)
York Sun45064ad2012-08-17 08:22:40 +0000427 | ((ext_wrrec & 0x1) << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500428 | ((cntl_adj & 0x7) << 0)
429 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400430 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500431}
432
433/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
434static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
Dave Liuc360cea2009-03-14 12:48:30 +0800435 const memctl_options_t *popts,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500436 const common_timing_params_t *common_dimm,
437 unsigned int cas_latency)
438{
439 /* Precharge-to-activate interval (tRP) */
440 unsigned char pretoact_mclk;
441 /* Activate to precharge interval (tRAS) */
442 unsigned char acttopre_mclk;
443 /* Activate to read/write interval (tRCD) */
444 unsigned char acttorw_mclk;
445 /* CASLAT */
446 unsigned char caslat_ctrl;
447 /* Refresh recovery time (tRFC) ; trfc_low */
448 unsigned char refrec_ctrl;
449 /* Last data to precharge minimum interval (tWR) */
450 unsigned char wrrec_mclk;
451 /* Activate-to-activate interval (tRRD) */
452 unsigned char acttoact_mclk;
453 /* Last write data pair to read command issue interval (tWTR) */
454 unsigned char wrtord_mclk;
York Sun34e026f2014-03-27 17:54:47 -0700455#ifdef CONFIG_SYS_FSL_DDR4
456 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
457 static const u8 wrrec_table[] = {
458 10, 10, 10, 10, 10,
459 10, 10, 10, 10, 10,
460 12, 12, 14, 14, 16,
461 16, 18, 18, 20, 20,
462 24, 24, 24, 24};
463#else
York Sunf5b6fb72011-03-02 14:24:11 -0800464 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
465 static const u8 wrrec_table[] = {
466 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
York Sun34e026f2014-03-27 17:54:47 -0700467#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500468
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530469 pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
470 acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
471 acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500472
473 /*
474 * Translate CAS Latency to a DDR controller field value:
475 *
476 * CAS Lat DDR I DDR II Ctrl
477 * Clocks SPD Bit SPD Bit Value
478 * ------- ------- ------- -----
479 * 1.0 0 0001
480 * 1.5 1 0010
481 * 2.0 2 2 0011
482 * 2.5 3 0100
483 * 3.0 4 3 0101
484 * 3.5 5 0110
485 * 4.0 4 0111
486 * 4.5 1000
487 * 5.0 5 1001
488 */
York Sun5614e712013-09-30 09:22:09 -0700489#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500490 caslat_ctrl = (cas_latency + 1) & 0x07;
York Sun5614e712013-09-30 09:22:09 -0700491#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500492 caslat_ctrl = 2 * cas_latency - 1;
493#else
Dave Liuc360cea2009-03-14 12:48:30 +0800494 /*
495 * if the CAS latency more than 8 cycle,
496 * we need set extend bit for it at
497 * TIMING_CFG_3[EXT_CASLAT]
498 */
York Sun34e026f2014-03-27 17:54:47 -0700499 if (fsl_ddr_get_version() <= 0x40400)
500 caslat_ctrl = 2 * cas_latency - 1;
501 else
502 caslat_ctrl = (cas_latency - 1) << 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500503#endif
504
York Sun34e026f2014-03-27 17:54:47 -0700505#ifdef CONFIG_SYS_FSL_DDR4
506 refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
507 wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
508 acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4);
509 wrtord_mclk = max(2, picos_to_mclk(2500));
York Sun349689b2014-04-01 14:20:49 -0700510 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
511 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
York Sun34e026f2014-03-27 17:54:47 -0700512 else
513 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
514#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530515 refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
516 wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
York Sun34e026f2014-03-27 17:54:47 -0700517 acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
518 wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
York Sun349689b2014-04-01 14:20:49 -0700519 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
520 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
York Sun45064ad2012-08-17 08:22:40 +0000521 else
522 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
York Sun34e026f2014-03-27 17:54:47 -0700523#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530524 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800525 wrrec_mclk += 2;
526
Dave Liuc360cea2009-03-14 12:48:30 +0800527 /*
528 * JEDEC has min requirement for tRRD
529 */
York Sun5614e712013-09-30 09:22:09 -0700530#if defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +0800531 if (acttoact_mclk < 4)
532 acttoact_mclk = 4;
533#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800534 /*
535 * JEDEC has some min requirements for tWTR
536 */
York Sun5614e712013-09-30 09:22:09 -0700537#if defined(CONFIG_SYS_FSL_DDR2)
Dave Liuc360cea2009-03-14 12:48:30 +0800538 if (wrtord_mclk < 2)
539 wrtord_mclk = 2;
York Sun5614e712013-09-30 09:22:09 -0700540#elif defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +0800541 if (wrtord_mclk < 4)
542 wrtord_mclk = 4;
543#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530544 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800545 wrtord_mclk += 2;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500546
547 ddr->timing_cfg_1 = (0
Dave Liu80ee3ce2008-11-21 16:31:22 +0800548 | ((pretoact_mclk & 0x0F) << 28)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500549 | ((acttopre_mclk & 0x0F) << 24)
Dave Liu80ee3ce2008-11-21 16:31:22 +0800550 | ((acttorw_mclk & 0xF) << 20)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500551 | ((caslat_ctrl & 0xF) << 16)
552 | ((refrec_ctrl & 0xF) << 12)
Dave Liu80ee3ce2008-11-21 16:31:22 +0800553 | ((wrrec_mclk & 0x0F) << 8)
York Sun57495e42012-10-08 07:44:22 +0000554 | ((acttoact_mclk & 0x0F) << 4)
555 | ((wrtord_mclk & 0x0F) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500556 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400557 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500558}
559
560/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
561static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
562 const memctl_options_t *popts,
563 const common_timing_params_t *common_dimm,
564 unsigned int cas_latency,
565 unsigned int additive_latency)
566{
567 /* Additive latency */
568 unsigned char add_lat_mclk;
569 /* CAS-to-preamble override */
570 unsigned short cpo;
571 /* Write latency */
572 unsigned char wr_lat;
573 /* Read to precharge (tRTP) */
574 unsigned char rd_to_pre;
575 /* Write command to write data strobe timing adjustment */
576 unsigned char wr_data_delay;
577 /* Minimum CKE pulse width (tCKE) */
578 unsigned char cke_pls;
579 /* Window for four activates (tFAW) */
580 unsigned short four_act;
581
582 /* FIXME add check that this must be less than acttorw_mclk */
583 add_lat_mclk = additive_latency;
584 cpo = popts->cpo_override;
585
York Sun5614e712013-09-30 09:22:09 -0700586#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500587 /*
588 * This is a lie. It should really be 1, but if it is
589 * set to 1, bits overlap into the old controller's
590 * otherwise unused ACSM field. If we leave it 0, then
591 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
592 */
593 wr_lat = 0;
York Sun5614e712013-09-30 09:22:09 -0700594#elif defined(CONFIG_SYS_FSL_DDR2)
Dave Liu6a819782009-03-14 12:48:19 +0800595 wr_lat = cas_latency - 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500596#else
Dave Liuc360cea2009-03-14 12:48:30 +0800597 wr_lat = compute_cas_write_latency();
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500598#endif
599
York Sun34e026f2014-03-27 17:54:47 -0700600#ifdef CONFIG_SYS_FSL_DDR4
601 rd_to_pre = picos_to_mclk(7500);
602#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530603 rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
York Sun34e026f2014-03-27 17:54:47 -0700604#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800605 /*
606 * JEDEC has some min requirements for tRTP
607 */
York Sun5614e712013-09-30 09:22:09 -0700608#if defined(CONFIG_SYS_FSL_DDR2)
Dave Liuc360cea2009-03-14 12:48:30 +0800609 if (rd_to_pre < 2)
610 rd_to_pre = 2;
York Sun34e026f2014-03-27 17:54:47 -0700611#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800612 if (rd_to_pre < 4)
613 rd_to_pre = 4;
Dave Liu6a819782009-03-14 12:48:19 +0800614#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530615 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800616 rd_to_pre += 2; /* according to UM */
617
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500618 wr_data_delay = popts->write_data_delay;
York Sun34e026f2014-03-27 17:54:47 -0700619#ifdef CONFIG_SYS_FSL_DDR4
620 cpo = 0;
621 cke_pls = max(3, picos_to_mclk(5000));
622#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530623 cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
York Sun34e026f2014-03-27 17:54:47 -0700624#endif
625
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530626 four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500627
628 ddr->timing_cfg_2 = (0
Dave Liu22ff3d02008-11-21 16:31:29 +0800629 | ((add_lat_mclk & 0xf) << 28)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500630 | ((cpo & 0x1f) << 23)
Dave Liu22ff3d02008-11-21 16:31:29 +0800631 | ((wr_lat & 0xf) << 19)
York Sun34e026f2014-03-27 17:54:47 -0700632 | ((wr_lat & 0x10) << 14)
Dave Liuc360cea2009-03-14 12:48:30 +0800633 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
634 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500635 | ((cke_pls & 0x7) << 6)
Dave Liu22ff3d02008-11-21 16:31:29 +0800636 | ((four_act & 0x3f) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500637 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400638 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500639}
640
york9490ff42010-07-02 22:25:55 +0000641/* DDR SDRAM Register Control Word */
642static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000643 const memctl_options_t *popts,
york9490ff42010-07-02 22:25:55 +0000644 const common_timing_params_t *common_dimm)
645{
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530646 if (common_dimm->all_dimms_registered &&
647 !common_dimm->all_dimms_unbuffered) {
York Sune1fd16b2011-01-10 12:03:00 +0000648 if (popts->rcw_override) {
649 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
650 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
651 } else {
652 ddr->ddr_sdram_rcw_1 =
653 common_dimm->rcw[0] << 28 | \
654 common_dimm->rcw[1] << 24 | \
655 common_dimm->rcw[2] << 20 | \
656 common_dimm->rcw[3] << 16 | \
657 common_dimm->rcw[4] << 12 | \
658 common_dimm->rcw[5] << 8 | \
659 common_dimm->rcw[6] << 4 | \
660 common_dimm->rcw[7];
661 ddr->ddr_sdram_rcw_2 =
662 common_dimm->rcw[8] << 28 | \
663 common_dimm->rcw[9] << 24 | \
664 common_dimm->rcw[10] << 20 | \
665 common_dimm->rcw[11] << 16 | \
666 common_dimm->rcw[12] << 12 | \
667 common_dimm->rcw[13] << 8 | \
668 common_dimm->rcw[14] << 4 | \
669 common_dimm->rcw[15];
670 }
york9490ff42010-07-02 22:25:55 +0000671 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
672 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
673 }
674}
675
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500676/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
677static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
678 const memctl_options_t *popts,
679 const common_timing_params_t *common_dimm)
680{
681 unsigned int mem_en; /* DDR SDRAM interface logic enable */
682 unsigned int sren; /* Self refresh enable (during sleep) */
683 unsigned int ecc_en; /* ECC enable. */
684 unsigned int rd_en; /* Registered DIMM enable */
685 unsigned int sdram_type; /* Type of SDRAM */
686 unsigned int dyn_pwr; /* Dynamic power management mode */
687 unsigned int dbw; /* DRAM dta bus width */
Dave Liu22ff3d02008-11-21 16:31:29 +0800688 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500689 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530690 unsigned int threet_en; /* Enable 3T timing */
691 unsigned int twot_en; /* Enable 2T timing */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500692 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
693 unsigned int x32_en = 0; /* x32 enable */
694 unsigned int pchb8 = 0; /* precharge bit 8 enable */
695 unsigned int hse; /* Global half strength override */
696 unsigned int mem_halt = 0; /* memory controller halt */
697 unsigned int bi = 0; /* Bypass initialization */
698
699 mem_en = 1;
700 sren = popts->self_refresh_in_sleep;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530701 if (common_dimm->all_dimms_ecc_capable) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500702 /* Allow setting of ECC only if all DIMMs are ECC. */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530703 ecc_en = popts->ecc_mode;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500704 } else {
705 ecc_en = 0;
706 }
707
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530708 if (common_dimm->all_dimms_registered &&
709 !common_dimm->all_dimms_unbuffered) {
York Sune1fd16b2011-01-10 12:03:00 +0000710 rd_en = 1;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530711 twot_en = 0;
York Sune1fd16b2011-01-10 12:03:00 +0000712 } else {
713 rd_en = 0;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530714 twot_en = popts->twot_en;
York Sune1fd16b2011-01-10 12:03:00 +0000715 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500716
717 sdram_type = CONFIG_FSL_SDRAM_TYPE;
718
719 dyn_pwr = popts->dynamic_power;
720 dbw = popts->data_bus_width;
Dave Liuc360cea2009-03-14 12:48:30 +0800721 /* 8-beat burst enable DDR-III case
722 * we must clear it when use the on-the-fly mode,
723 * must set it when use the 32-bits bus mode.
724 */
York Sun34e026f2014-03-27 17:54:47 -0700725 if ((sdram_type == SDRAM_TYPE_DDR3) ||
726 (sdram_type == SDRAM_TYPE_DDR4)) {
Dave Liuc360cea2009-03-14 12:48:30 +0800727 if (popts->burst_length == DDR_BL8)
728 eight_be = 1;
729 if (popts->burst_length == DDR_OTF)
730 eight_be = 0;
731 if (dbw == 0x1)
732 eight_be = 1;
733 }
734
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530735 threet_en = popts->threet_en;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500736 ba_intlv_ctl = popts->ba_intlv_ctl;
737 hse = popts->half_strength_driver_enable;
738
739 ddr->ddr_sdram_cfg = (0
740 | ((mem_en & 0x1) << 31)
741 | ((sren & 0x1) << 30)
742 | ((ecc_en & 0x1) << 29)
743 | ((rd_en & 0x1) << 28)
744 | ((sdram_type & 0x7) << 24)
745 | ((dyn_pwr & 0x1) << 21)
746 | ((dbw & 0x3) << 19)
747 | ((eight_be & 0x1) << 18)
748 | ((ncap & 0x1) << 17)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530749 | ((threet_en & 0x1) << 16)
750 | ((twot_en & 0x1) << 15)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500751 | ((ba_intlv_ctl & 0x7F) << 8)
752 | ((x32_en & 0x1) << 5)
753 | ((pchb8 & 0x1) << 4)
754 | ((hse & 0x1) << 3)
755 | ((mem_halt & 0x1) << 1)
756 | ((bi & 0x1) << 0)
757 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400758 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500759}
760
761/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
762static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000763 const memctl_options_t *popts,
764 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500765{
766 unsigned int frc_sr = 0; /* Force self refresh */
767 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
York Suncae7c1b2011-08-26 11:32:40 -0700768 unsigned int odt_cfg = 0; /* ODT configuration */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500769 unsigned int num_pr; /* Number of posted refreshes */
York Sun57495e42012-10-08 07:44:22 +0000770 unsigned int slow = 0; /* DDR will be run less than 1250 */
York Sunb61e0612013-06-25 11:37:47 -0700771 unsigned int x4_en = 0; /* x4 DRAM enable */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500772 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
773 unsigned int ap_en; /* Address Parity Enable */
774 unsigned int d_init; /* DRAM data initialization */
775 unsigned int rcw_en = 0; /* Register Control Word Enable */
776 unsigned int md_en = 0; /* Mirrored DIMM Enable */
york5800e7a2010-07-02 22:25:53 +0000777 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
York Suncae7c1b2011-08-26 11:32:40 -0700778 int i;
York Sun34e026f2014-03-27 17:54:47 -0700779#ifndef CONFIG_SYS_FSL_DDR4
780 unsigned int dll_rst_dis = 1; /* DLL reset disable */
781 unsigned int dqs_cfg; /* DQS configuration */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500782
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530783 dqs_cfg = popts->dqs_config;
York Sun34e026f2014-03-27 17:54:47 -0700784#endif
York Suncae7c1b2011-08-26 11:32:40 -0700785 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
786 if (popts->cs_local_opts[i].odt_rd_cfg
787 || popts->cs_local_opts[i].odt_wr_cfg) {
788 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
789 break;
790 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500791 }
792
793 num_pr = 1; /* Make this configurable */
794
795 /*
796 * 8572 manual says
797 * {TIMING_CFG_1[PRETOACT]
798 * + [DDR_SDRAM_CFG_2[NUM_PR]
799 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
800 * << DDR_SDRAM_INTERVAL[REFINT]
801 */
York Sun34e026f2014-03-27 17:54:47 -0700802#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530803 obc_cfg = popts->otf_burst_chop_en;
Dave Liuc360cea2009-03-14 12:48:30 +0800804#else
805 obc_cfg = 0;
806#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500807
York Sun57495e42012-10-08 07:44:22 +0000808#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
809 slow = get_ddr_freq(0) < 1249000000;
810#endif
811
York Sune1fd16b2011-01-10 12:03:00 +0000812 if (popts->registered_dimm_en) {
813 rcw_en = 1;
814 ap_en = popts->ap_en;
815 } else {
York Sune1fd16b2011-01-10 12:03:00 +0000816 ap_en = 0;
817 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500818
York Sunb61e0612013-06-25 11:37:47 -0700819 x4_en = popts->x4_en ? 1 : 0;
820
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500821#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
822 /* Use the DDR controller to auto initialize memory. */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530823 d_init = popts->ecc_init_using_memctl;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500824 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
825 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
826#else
827 /* Memory will be initialized via DMA, or not at all. */
828 d_init = 0;
829#endif
830
York Sun34e026f2014-03-27 17:54:47 -0700831#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800832 md_en = popts->mirrored_dimm;
833#endif
york5800e7a2010-07-02 22:25:53 +0000834 qd_en = popts->quad_rank_present ? 1 : 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500835 ddr->ddr_sdram_cfg_2 = (0
836 | ((frc_sr & 0x1) << 31)
837 | ((sr_ie & 0x1) << 30)
York Sun34e026f2014-03-27 17:54:47 -0700838#ifndef CONFIG_SYS_FSL_DDR4
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500839 | ((dll_rst_dis & 0x1) << 29)
840 | ((dqs_cfg & 0x3) << 26)
York Sun34e026f2014-03-27 17:54:47 -0700841#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500842 | ((odt_cfg & 0x3) << 21)
843 | ((num_pr & 0xf) << 12)
York Sun57495e42012-10-08 07:44:22 +0000844 | ((slow & 1) << 11)
York Sunb61e0612013-06-25 11:37:47 -0700845 | (x4_en << 10)
york5800e7a2010-07-02 22:25:53 +0000846 | (qd_en << 9)
York Sune1fd16b2011-01-10 12:03:00 +0000847 | (unq_mrs_en << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500848 | ((obc_cfg & 0x1) << 6)
849 | ((ap_en & 0x1) << 5)
850 | ((d_init & 0x1) << 4)
851 | ((rcw_en & 0x1) << 2)
852 | ((md_en & 0x1) << 0)
853 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400854 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500855}
856
York Sun34e026f2014-03-27 17:54:47 -0700857#ifdef CONFIG_SYS_FSL_DDR4
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500858/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
Dave Liu1aa3d082009-12-16 10:24:38 -0600859static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000860 const memctl_options_t *popts,
Valentin Longchamp7e157b02013-10-18 11:47:20 +0200861 const common_timing_params_t *common_dimm,
York Sune1fd16b2011-01-10 12:03:00 +0000862 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500863{
864 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
865 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
York Sun34e026f2014-03-27 17:54:47 -0700866 int i;
867 unsigned int wr_crc = 0; /* Disable */
868 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
869 unsigned int srt = 0; /* self-refresh temerature, normal range */
870 unsigned int cwl = compute_cas_write_latency() - 9;
871 unsigned int mpr = 0; /* serial */
872 unsigned int wc_lat;
873 const unsigned int mclk_ps = get_memory_clk_period_ps();
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500874
York Sun34e026f2014-03-27 17:54:47 -0700875 if (popts->rtt_override)
876 rtt_wr = popts->rtt_wr_override_value;
877 else
878 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
879
880 if (common_dimm->extended_op_srt)
881 srt = common_dimm->extended_op_srt;
882
883 esdmode2 = (0
884 | ((wr_crc & 0x1) << 12)
885 | ((rtt_wr & 0x3) << 9)
886 | ((srt & 0x3) << 6)
887 | ((cwl & 0x7) << 3));
888
889 if (mclk_ps >= 1250)
890 wc_lat = 0;
891 else if (mclk_ps >= 833)
892 wc_lat = 1;
893 else
894 wc_lat = 2;
895
896 esdmode3 = (0
897 | ((mpr & 0x3) << 11)
898 | ((wc_lat & 0x3) << 9));
899
900 ddr->ddr_sdram_mode_2 = (0
901 | ((esdmode2 & 0xFFFF) << 16)
902 | ((esdmode3 & 0xFFFF) << 0)
903 );
904 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
905
906 if (unq_mrs_en) { /* unique mode registers are supported */
907 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
908 if (popts->rtt_override)
909 rtt_wr = popts->rtt_wr_override_value;
910 else
911 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
912
913 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
914 esdmode2 |= (rtt_wr & 0x3) << 9;
915 switch (i) {
916 case 1:
917 ddr->ddr_sdram_mode_4 = (0
918 | ((esdmode2 & 0xFFFF) << 16)
919 | ((esdmode3 & 0xFFFF) << 0)
920 );
921 break;
922 case 2:
923 ddr->ddr_sdram_mode_6 = (0
924 | ((esdmode2 & 0xFFFF) << 16)
925 | ((esdmode3 & 0xFFFF) << 0)
926 );
927 break;
928 case 3:
929 ddr->ddr_sdram_mode_8 = (0
930 | ((esdmode2 & 0xFFFF) << 16)
931 | ((esdmode3 & 0xFFFF) << 0)
932 );
933 break;
934 }
935 }
936 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
937 ddr->ddr_sdram_mode_4);
938 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
939 ddr->ddr_sdram_mode_6);
940 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
941 ddr->ddr_sdram_mode_8);
942 }
943}
944#elif defined(CONFIG_SYS_FSL_DDR3)
945/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
946static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
947 const memctl_options_t *popts,
948 const common_timing_params_t *common_dimm,
949 const unsigned int unq_mrs_en)
950{
951 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
952 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
Kumar Gala92966832011-01-20 01:53:15 -0600953 int i;
Dave Liu1aa3d082009-12-16 10:24:38 -0600954 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
Dave Liuc360cea2009-03-14 12:48:30 +0800955 unsigned int srt = 0; /* self-refresh temerature, normal range */
956 unsigned int asr = 0; /* auto self-refresh disable */
957 unsigned int cwl = compute_cas_write_latency() - 5;
958 unsigned int pasr = 0; /* partial array self refresh disable */
959
Dave Liu1aa3d082009-12-16 10:24:38 -0600960 if (popts->rtt_override)
961 rtt_wr = popts->rtt_wr_override_value;
York Sune1fd16b2011-01-10 12:03:00 +0000962 else
963 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
Valentin Longchamp7e157b02013-10-18 11:47:20 +0200964
965 if (common_dimm->extended_op_srt)
966 srt = common_dimm->extended_op_srt;
967
Dave Liuc360cea2009-03-14 12:48:30 +0800968 esdmode2 = (0
969 | ((rtt_wr & 0x3) << 9)
970 | ((srt & 0x1) << 7)
971 | ((asr & 0x1) << 6)
972 | ((cwl & 0x7) << 3)
973 | ((pasr & 0x7) << 0));
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500974 ddr->ddr_sdram_mode_2 = (0
975 | ((esdmode2 & 0xFFFF) << 16)
976 | ((esdmode3 & 0xFFFF) << 0)
977 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400978 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
York Sune1fd16b2011-01-10 12:03:00 +0000979
York Sune1fd16b2011-01-10 12:03:00 +0000980 if (unq_mrs_en) { /* unique mode registers are supported */
Kumar Galadea7f882011-11-09 10:05:10 -0600981 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sune1fd16b2011-01-10 12:03:00 +0000982 if (popts->rtt_override)
983 rtt_wr = popts->rtt_wr_override_value;
984 else
985 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
986
987 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
988 esdmode2 |= (rtt_wr & 0x3) << 9;
989 switch (i) {
990 case 1:
991 ddr->ddr_sdram_mode_4 = (0
992 | ((esdmode2 & 0xFFFF) << 16)
993 | ((esdmode3 & 0xFFFF) << 0)
994 );
995 break;
996 case 2:
997 ddr->ddr_sdram_mode_6 = (0
998 | ((esdmode2 & 0xFFFF) << 16)
999 | ((esdmode3 & 0xFFFF) << 0)
1000 );
1001 break;
1002 case 3:
1003 ddr->ddr_sdram_mode_8 = (0
1004 | ((esdmode2 & 0xFFFF) << 16)
1005 | ((esdmode3 & 0xFFFF) << 0)
1006 );
1007 break;
1008 }
1009 }
1010 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1011 ddr->ddr_sdram_mode_4);
1012 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1013 ddr->ddr_sdram_mode_6);
1014 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1015 ddr->ddr_sdram_mode_8);
1016 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001017}
1018
York Sun34e026f2014-03-27 17:54:47 -07001019#else /* for DDR2 and DDR1 */
1020/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1021static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
1022 const memctl_options_t *popts,
1023 const common_timing_params_t *common_dimm,
1024 const unsigned int unq_mrs_en)
1025{
1026 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1027 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1028
1029 ddr->ddr_sdram_mode_2 = (0
1030 | ((esdmode2 & 0xFFFF) << 16)
1031 | ((esdmode3 & 0xFFFF) << 0)
1032 );
1033 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1034}
1035#endif
1036
1037#ifdef CONFIG_SYS_FSL_DDR4
1038/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1039static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1040 const memctl_options_t *popts,
1041 const common_timing_params_t *common_dimm,
1042 const unsigned int unq_mrs_en)
1043{
1044 int i;
1045 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1046 unsigned short esdmode5; /* Extended SDRAM mode 5 */
1047
1048 esdmode5 = 0x00000400; /* Data mask enabled */
1049
1050 ddr->ddr_sdram_mode_9 = (0
1051 | ((esdmode4 & 0xffff) << 16)
1052 | ((esdmode5 & 0xffff) << 0)
1053 );
1054 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1055 if (unq_mrs_en) { /* unique mode registers are supported */
1056 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1057 switch (i) {
1058 case 1:
1059 ddr->ddr_sdram_mode_11 = (0
1060 | ((esdmode4 & 0xFFFF) << 16)
1061 | ((esdmode5 & 0xFFFF) << 0)
1062 );
1063 break;
1064 case 2:
1065 ddr->ddr_sdram_mode_13 = (0
1066 | ((esdmode4 & 0xFFFF) << 16)
1067 | ((esdmode5 & 0xFFFF) << 0)
1068 );
1069 break;
1070 case 3:
1071 ddr->ddr_sdram_mode_15 = (0
1072 | ((esdmode4 & 0xFFFF) << 16)
1073 | ((esdmode5 & 0xFFFF) << 0)
1074 );
1075 break;
1076 }
1077 }
1078 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1079 ddr->ddr_sdram_mode_11);
1080 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1081 ddr->ddr_sdram_mode_13);
1082 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1083 ddr->ddr_sdram_mode_15);
1084 }
1085}
1086
1087/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1088static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
1089 const memctl_options_t *popts,
1090 const common_timing_params_t *common_dimm,
1091 const unsigned int unq_mrs_en)
1092{
1093 int i;
1094 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1095 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
1096 unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
1097
1098 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1099
1100 ddr->ddr_sdram_mode_10 = (0
1101 | ((esdmode6 & 0xffff) << 16)
1102 | ((esdmode7 & 0xffff) << 0)
1103 );
1104 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1105 if (unq_mrs_en) { /* unique mode registers are supported */
1106 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1107 switch (i) {
1108 case 1:
1109 ddr->ddr_sdram_mode_12 = (0
1110 | ((esdmode6 & 0xFFFF) << 16)
1111 | ((esdmode7 & 0xFFFF) << 0)
1112 );
1113 break;
1114 case 2:
1115 ddr->ddr_sdram_mode_14 = (0
1116 | ((esdmode6 & 0xFFFF) << 16)
1117 | ((esdmode7 & 0xFFFF) << 0)
1118 );
1119 break;
1120 case 3:
1121 ddr->ddr_sdram_mode_16 = (0
1122 | ((esdmode6 & 0xFFFF) << 16)
1123 | ((esdmode7 & 0xFFFF) << 0)
1124 );
1125 break;
1126 }
1127 }
1128 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1129 ddr->ddr_sdram_mode_12);
1130 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1131 ddr->ddr_sdram_mode_14);
1132 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1133 ddr->ddr_sdram_mode_16);
1134 }
1135}
1136
1137#endif
1138
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001139/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1140static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
1141 const memctl_options_t *popts,
1142 const common_timing_params_t *common_dimm)
1143{
1144 unsigned int refint; /* Refresh interval */
1145 unsigned int bstopre; /* Precharge interval */
1146
1147 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
1148
1149 bstopre = popts->bstopre;
1150
1151 /* refint field used 0x3FFF in earlier controllers */
1152 ddr->ddr_sdram_interval = (0
1153 | ((refint & 0xFFFF) << 16)
1154 | ((bstopre & 0x3FFF) << 0)
1155 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001156 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001157}
1158
York Sun34e026f2014-03-27 17:54:47 -07001159#ifdef CONFIG_SYS_FSL_DDR4
Dave Liuc360cea2009-03-14 12:48:30 +08001160/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1161static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1162 const memctl_options_t *popts,
1163 const common_timing_params_t *common_dimm,
1164 unsigned int cas_latency,
York Sune1fd16b2011-01-10 12:03:00 +00001165 unsigned int additive_latency,
1166 const unsigned int unq_mrs_en)
Dave Liuc360cea2009-03-14 12:48:30 +08001167{
York Sun34e026f2014-03-27 17:54:47 -07001168 int i;
1169 unsigned short esdmode; /* Extended SDRAM mode */
1170 unsigned short sdmode; /* SDRAM mode */
1171
1172 /* Mode Register - MR1 */
1173 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1174 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1175 unsigned int rtt;
1176 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1177 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1178 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1179 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1180 0=Disable (Test/Debug) */
1181
1182 /* Mode Register - MR0 */
1183 unsigned int wr = 0; /* Write Recovery */
1184 unsigned int dll_rst; /* DLL Reset */
1185 unsigned int mode; /* Normal=0 or Test=1 */
1186 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1187 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1188 unsigned int bt;
1189 unsigned int bl; /* BL: Burst Length */
1190
1191 unsigned int wr_mclk;
1192 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1193 static const u8 wr_table[] = {
1194 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1195 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1196 static const u8 cas_latency_table[] = {
1197 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1198 9, 9, 10, 10, 11, 11};
1199
1200 if (popts->rtt_override)
1201 rtt = popts->rtt_override_value;
1202 else
1203 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1204
1205 if (additive_latency == (cas_latency - 1))
1206 al = 1;
1207 if (additive_latency == (cas_latency - 2))
1208 al = 2;
1209
1210 if (popts->quad_rank_present)
1211 dic = 1; /* output driver impedance 240/7 ohm */
1212
1213 /*
1214 * The esdmode value will also be used for writing
1215 * MR1 during write leveling for DDR3, although the
1216 * bits specifically related to the write leveling
1217 * scheme will be handled automatically by the DDR
1218 * controller. so we set the wrlvl_en = 0 here.
1219 */
1220 esdmode = (0
1221 | ((qoff & 0x1) << 12)
1222 | ((tdqs_en & 0x1) << 11)
1223 | ((rtt & 0x7) << 8)
1224 | ((wrlvl_en & 0x1) << 7)
1225 | ((al & 0x3) << 3)
1226 | ((dic & 0x3) << 1) /* DIC field is split */
1227 | ((dll_en & 0x1) << 0)
1228 );
1229
1230 /*
1231 * DLL control for precharge PD
1232 * 0=slow exit DLL off (tXPDLL)
1233 * 1=fast exit DLL on (tXP)
1234 */
1235
1236 wr_mclk = picos_to_mclk(common_dimm->twr_ps);
1237 if (wr_mclk <= 24) {
1238 wr = wr_table[wr_mclk - 10];
1239 } else {
1240 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1241 wr_mclk);
1242 }
1243
1244 dll_rst = 0; /* dll no reset */
1245 mode = 0; /* normal mode */
1246
1247 /* look up table to get the cas latency bits */
1248 if (cas_latency >= 9 && cas_latency <= 24)
1249 caslat = cas_latency_table[cas_latency - 9];
1250 else
1251 printf("Error: unsupported cas latency for mode register\n");
1252
1253 bt = 0; /* Nibble sequential */
1254
1255 switch (popts->burst_length) {
1256 case DDR_BL8:
1257 bl = 0;
1258 break;
1259 case DDR_OTF:
1260 bl = 1;
1261 break;
1262 case DDR_BC4:
1263 bl = 2;
1264 break;
1265 default:
1266 printf("Error: invalid burst length of %u specified. ",
1267 popts->burst_length);
1268 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1269 bl = 1;
1270 break;
1271 }
1272
1273 sdmode = (0
1274 | ((wr & 0x7) << 9)
1275 | ((dll_rst & 0x1) << 8)
1276 | ((mode & 0x1) << 7)
1277 | (((caslat >> 1) & 0x7) << 4)
1278 | ((bt & 0x1) << 3)
1279 | ((caslat & 1) << 2)
1280 | ((bl & 0x3) << 0)
1281 );
1282
1283 ddr->ddr_sdram_mode = (0
1284 | ((esdmode & 0xFFFF) << 16)
1285 | ((sdmode & 0xFFFF) << 0)
1286 );
1287
1288 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1289
1290 if (unq_mrs_en) { /* unique mode registers are supported */
1291 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1292 if (popts->rtt_override)
1293 rtt = popts->rtt_override_value;
1294 else
1295 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1296
1297 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1298 esdmode |= (rtt & 0x7) << 8;
1299 switch (i) {
1300 case 1:
1301 ddr->ddr_sdram_mode_3 = (0
1302 | ((esdmode & 0xFFFF) << 16)
1303 | ((sdmode & 0xFFFF) << 0)
1304 );
1305 break;
1306 case 2:
1307 ddr->ddr_sdram_mode_5 = (0
1308 | ((esdmode & 0xFFFF) << 16)
1309 | ((sdmode & 0xFFFF) << 0)
1310 );
1311 break;
1312 case 3:
1313 ddr->ddr_sdram_mode_7 = (0
1314 | ((esdmode & 0xFFFF) << 16)
1315 | ((sdmode & 0xFFFF) << 0)
1316 );
1317 break;
1318 }
1319 }
1320 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1321 ddr->ddr_sdram_mode_3);
1322 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1323 ddr->ddr_sdram_mode_5);
1324 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1325 ddr->ddr_sdram_mode_5);
1326 }
1327}
1328
1329#elif defined(CONFIG_SYS_FSL_DDR3)
1330/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1331static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1332 const memctl_options_t *popts,
1333 const common_timing_params_t *common_dimm,
1334 unsigned int cas_latency,
1335 unsigned int additive_latency,
1336 const unsigned int unq_mrs_en)
1337{
1338 int i;
Dave Liuc360cea2009-03-14 12:48:30 +08001339 unsigned short esdmode; /* Extended SDRAM mode */
1340 unsigned short sdmode; /* SDRAM mode */
1341
1342 /* Mode Register - MR1 */
1343 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1344 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1345 unsigned int rtt;
1346 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1347 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
York Sune1fd16b2011-01-10 12:03:00 +00001348 unsigned int dic = 0; /* Output driver impedance, 40ohm */
Dave Liuc360cea2009-03-14 12:48:30 +08001349 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1350 1=Disable (Test/Debug) */
1351
1352 /* Mode Register - MR0 */
1353 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
York Sunfcea3062012-08-17 08:22:38 +00001354 unsigned int wr = 0; /* Write Recovery */
Dave Liuc360cea2009-03-14 12:48:30 +08001355 unsigned int dll_rst; /* DLL Reset */
1356 unsigned int mode; /* Normal=0 or Test=1 */
1357 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1358 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1359 unsigned int bt;
1360 unsigned int bl; /* BL: Burst Length */
1361
1362 unsigned int wr_mclk;
York Sunf5b6fb72011-03-02 14:24:11 -08001363 /*
1364 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1365 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1366 * for this table
1367 */
1368 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
Dave Liuc360cea2009-03-14 12:48:30 +08001369
Dave Liuc360cea2009-03-14 12:48:30 +08001370 if (popts->rtt_override)
1371 rtt = popts->rtt_override_value;
York Sune1fd16b2011-01-10 12:03:00 +00001372 else
1373 rtt = popts->cs_local_opts[0].odt_rtt_norm;
Dave Liuc360cea2009-03-14 12:48:30 +08001374
1375 if (additive_latency == (cas_latency - 1))
1376 al = 1;
1377 if (additive_latency == (cas_latency - 2))
1378 al = 2;
1379
York Sune1fd16b2011-01-10 12:03:00 +00001380 if (popts->quad_rank_present)
1381 dic = 1; /* output driver impedance 240/7 ohm */
1382
Dave Liuc360cea2009-03-14 12:48:30 +08001383 /*
1384 * The esdmode value will also be used for writing
1385 * MR1 during write leveling for DDR3, although the
1386 * bits specifically related to the write leveling
1387 * scheme will be handled automatically by the DDR
1388 * controller. so we set the wrlvl_en = 0 here.
1389 */
1390 esdmode = (0
1391 | ((qoff & 0x1) << 12)
1392 | ((tdqs_en & 0x1) << 11)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001393 | ((rtt & 0x4) << 7) /* rtt field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001394 | ((wrlvl_en & 0x1) << 7)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001395 | ((rtt & 0x2) << 5) /* rtt field is split */
1396 | ((dic & 0x2) << 4) /* DIC field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001397 | ((al & 0x3) << 3)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001398 | ((rtt & 0x1) << 2) /* rtt field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001399 | ((dic & 0x1) << 1) /* DIC field is split */
1400 | ((dll_en & 0x1) << 0)
1401 );
1402
1403 /*
1404 * DLL control for precharge PD
1405 * 0=slow exit DLL off (tXPDLL)
1406 * 1=fast exit DLL on (tXP)
1407 */
1408 dll_on = 1;
York Sunf5b6fb72011-03-02 14:24:11 -08001409
York Sun34e026f2014-03-27 17:54:47 -07001410 wr_mclk = picos_to_mclk(common_dimm->twr_ps);
York Sunfcea3062012-08-17 08:22:38 +00001411 if (wr_mclk <= 16) {
1412 wr = wr_table[wr_mclk - 5];
1413 } else {
1414 printf("Error: unsupported write recovery for mode register "
1415 "wr_mclk = %d\n", wr_mclk);
1416 }
York Sunf5b6fb72011-03-02 14:24:11 -08001417
Dave Liuc360cea2009-03-14 12:48:30 +08001418 dll_rst = 0; /* dll no reset */
1419 mode = 0; /* normal mode */
1420
1421 /* look up table to get the cas latency bits */
York Sunfcea3062012-08-17 08:22:38 +00001422 if (cas_latency >= 5 && cas_latency <= 16) {
1423 unsigned char cas_latency_table[] = {
Dave Liuc360cea2009-03-14 12:48:30 +08001424 0x2, /* 5 clocks */
1425 0x4, /* 6 clocks */
1426 0x6, /* 7 clocks */
1427 0x8, /* 8 clocks */
1428 0xa, /* 9 clocks */
1429 0xc, /* 10 clocks */
York Sunfcea3062012-08-17 08:22:38 +00001430 0xe, /* 11 clocks */
1431 0x1, /* 12 clocks */
1432 0x3, /* 13 clocks */
1433 0x5, /* 14 clocks */
1434 0x7, /* 15 clocks */
1435 0x9, /* 16 clocks */
Dave Liuc360cea2009-03-14 12:48:30 +08001436 };
1437 caslat = cas_latency_table[cas_latency - 5];
York Sunfcea3062012-08-17 08:22:38 +00001438 } else {
1439 printf("Error: unsupported cas latency for mode register\n");
Dave Liuc360cea2009-03-14 12:48:30 +08001440 }
York Sunfcea3062012-08-17 08:22:38 +00001441
Dave Liuc360cea2009-03-14 12:48:30 +08001442 bt = 0; /* Nibble sequential */
1443
1444 switch (popts->burst_length) {
1445 case DDR_BL8:
1446 bl = 0;
1447 break;
1448 case DDR_OTF:
1449 bl = 1;
1450 break;
1451 case DDR_BC4:
1452 bl = 2;
1453 break;
1454 default:
1455 printf("Error: invalid burst length of %u specified. "
1456 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1457 popts->burst_length);
1458 bl = 1;
1459 break;
1460 }
1461
1462 sdmode = (0
1463 | ((dll_on & 0x1) << 12)
1464 | ((wr & 0x7) << 9)
1465 | ((dll_rst & 0x1) << 8)
1466 | ((mode & 0x1) << 7)
1467 | (((caslat >> 1) & 0x7) << 4)
1468 | ((bt & 0x1) << 3)
York Sunfcea3062012-08-17 08:22:38 +00001469 | ((caslat & 1) << 2)
Dave Liuc360cea2009-03-14 12:48:30 +08001470 | ((bl & 0x3) << 0)
1471 );
1472
1473 ddr->ddr_sdram_mode = (0
1474 | ((esdmode & 0xFFFF) << 16)
1475 | ((sdmode & 0xFFFF) << 0)
1476 );
1477
1478 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
York Sune1fd16b2011-01-10 12:03:00 +00001479
1480 if (unq_mrs_en) { /* unique mode registers are supported */
Kumar Galadea7f882011-11-09 10:05:10 -06001481 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sune1fd16b2011-01-10 12:03:00 +00001482 if (popts->rtt_override)
1483 rtt = popts->rtt_override_value;
1484 else
1485 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1486
1487 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1488 esdmode |= (0
1489 | ((rtt & 0x4) << 7) /* rtt field is split */
1490 | ((rtt & 0x2) << 5) /* rtt field is split */
1491 | ((rtt & 0x1) << 2) /* rtt field is split */
1492 );
1493 switch (i) {
1494 case 1:
1495 ddr->ddr_sdram_mode_3 = (0
1496 | ((esdmode & 0xFFFF) << 16)
1497 | ((sdmode & 0xFFFF) << 0)
1498 );
1499 break;
1500 case 2:
1501 ddr->ddr_sdram_mode_5 = (0
1502 | ((esdmode & 0xFFFF) << 16)
1503 | ((sdmode & 0xFFFF) << 0)
1504 );
1505 break;
1506 case 3:
1507 ddr->ddr_sdram_mode_7 = (0
1508 | ((esdmode & 0xFFFF) << 16)
1509 | ((sdmode & 0xFFFF) << 0)
1510 );
1511 break;
1512 }
1513 }
1514 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1515 ddr->ddr_sdram_mode_3);
1516 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1517 ddr->ddr_sdram_mode_5);
1518 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1519 ddr->ddr_sdram_mode_5);
1520 }
Dave Liuc360cea2009-03-14 12:48:30 +08001521}
1522
York Sun5614e712013-09-30 09:22:09 -07001523#else /* !CONFIG_SYS_FSL_DDR3 */
Dave Liuc360cea2009-03-14 12:48:30 +08001524
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001525/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1526static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1527 const memctl_options_t *popts,
1528 const common_timing_params_t *common_dimm,
1529 unsigned int cas_latency,
York Sune1fd16b2011-01-10 12:03:00 +00001530 unsigned int additive_latency,
1531 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001532{
1533 unsigned short esdmode; /* Extended SDRAM mode */
1534 unsigned short sdmode; /* SDRAM mode */
1535
1536 /*
1537 * FIXME: This ought to be pre-calculated in a
1538 * technology-specific routine,
1539 * e.g. compute_DDR2_mode_register(), and then the
1540 * sdmode and esdmode passed in as part of common_dimm.
1541 */
1542
1543 /* Extended Mode Register */
1544 unsigned int mrs = 0; /* Mode Register Set */
1545 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1546 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1547 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1548 unsigned int ocd = 0; /* 0x0=OCD not supported,
1549 0x7=OCD default state */
1550 unsigned int rtt;
1551 unsigned int al; /* Posted CAS# additive latency (AL) */
1552 unsigned int ods = 0; /* Output Drive Strength:
1553 0 = Full strength (18ohm)
1554 1 = Reduced strength (4ohm) */
1555 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1556 1=Disable (Test/Debug) */
1557
1558 /* Mode Register (MR) */
1559 unsigned int mr; /* Mode Register Definition */
1560 unsigned int pd; /* Power-Down Mode */
1561 unsigned int wr; /* Write Recovery */
1562 unsigned int dll_res; /* DLL Reset */
1563 unsigned int mode; /* Normal=0 or Test=1 */
Kumar Gala302e52e2008-09-05 14:40:29 -05001564 unsigned int caslat = 0;/* CAS# latency */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001565 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1566 unsigned int bt;
1567 unsigned int bl; /* BL: Burst Length */
1568
Priyanka Jain0dd38a32013-09-25 10:41:19 +05301569 dqs_en = !popts->dqs_config;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001570 rtt = fsl_ddr_get_rtt();
1571
1572 al = additive_latency;
1573
1574 esdmode = (0
1575 | ((mrs & 0x3) << 14)
1576 | ((outputs & 0x1) << 12)
1577 | ((rdqs_en & 0x1) << 11)
1578 | ((dqs_en & 0x1) << 10)
1579 | ((ocd & 0x7) << 7)
1580 | ((rtt & 0x2) << 5) /* rtt field is split */
1581 | ((al & 0x7) << 3)
1582 | ((rtt & 0x1) << 2) /* rtt field is split */
1583 | ((ods & 0x1) << 1)
1584 | ((dll_en & 0x1) << 0)
1585 );
1586
1587 mr = 0; /* FIXME: CHECKME */
1588
1589 /*
1590 * 0 = Fast Exit (Normal)
1591 * 1 = Slow Exit (Low Power)
1592 */
1593 pd = 0;
1594
York Sun5614e712013-09-30 09:22:09 -07001595#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001596 wr = 0; /* Historical */
York Sun5614e712013-09-30 09:22:09 -07001597#elif defined(CONFIG_SYS_FSL_DDR2)
York Sun34e026f2014-03-27 17:54:47 -07001598 wr = picos_to_mclk(common_dimm->twr_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001599#endif
1600 dll_res = 0;
1601 mode = 0;
1602
York Sun5614e712013-09-30 09:22:09 -07001603#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001604 if (1 <= cas_latency && cas_latency <= 4) {
1605 unsigned char mode_caslat_table[4] = {
1606 0x5, /* 1.5 clocks */
1607 0x2, /* 2.0 clocks */
1608 0x6, /* 2.5 clocks */
1609 0x3 /* 3.0 clocks */
1610 };
Kumar Gala302e52e2008-09-05 14:40:29 -05001611 caslat = mode_caslat_table[cas_latency - 1];
1612 } else {
1613 printf("Warning: unknown cas_latency %d\n", cas_latency);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001614 }
York Sun5614e712013-09-30 09:22:09 -07001615#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001616 caslat = cas_latency;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001617#endif
1618 bt = 0;
1619
1620 switch (popts->burst_length) {
Dave Liuc360cea2009-03-14 12:48:30 +08001621 case DDR_BL4:
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001622 bl = 2;
1623 break;
Dave Liuc360cea2009-03-14 12:48:30 +08001624 case DDR_BL8:
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001625 bl = 3;
1626 break;
1627 default:
1628 printf("Error: invalid burst length of %u specified. "
1629 " Defaulting to 4 beats.\n",
1630 popts->burst_length);
1631 bl = 2;
1632 break;
1633 }
1634
1635 sdmode = (0
1636 | ((mr & 0x3) << 14)
1637 | ((pd & 0x1) << 12)
1638 | ((wr & 0x7) << 9)
1639 | ((dll_res & 0x1) << 8)
1640 | ((mode & 0x1) << 7)
1641 | ((caslat & 0x7) << 4)
1642 | ((bt & 0x1) << 3)
1643 | ((bl & 0x7) << 0)
1644 );
1645
1646 ddr->ddr_sdram_mode = (0
1647 | ((esdmode & 0xFFFF) << 16)
1648 | ((sdmode & 0xFFFF) << 0)
1649 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001650 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001651}
Dave Liuc360cea2009-03-14 12:48:30 +08001652#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001653
1654/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1655static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1656{
1657 unsigned int init_value; /* Initialization value */
1658
Anatolij Gustschin5b933942013-01-21 23:50:27 +00001659#ifdef CONFIG_MEM_INIT_VALUE
1660 init_value = CONFIG_MEM_INIT_VALUE;
1661#else
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001662 init_value = 0xDEADBEEF;
Anatolij Gustschin5b933942013-01-21 23:50:27 +00001663#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001664 ddr->ddr_data_init = init_value;
1665}
1666
1667/*
1668 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1669 * The old controller on the 8540/60 doesn't have this register.
1670 * Hope it's OK to set it (to 0) anyway.
1671 */
1672static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1673 const memctl_options_t *popts)
1674{
1675 unsigned int clk_adjust; /* Clock adjust */
1676
1677 clk_adjust = popts->clk_adjust;
1678 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
york9490ff42010-07-02 22:25:55 +00001679 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001680}
1681
1682/* DDR Initialization Address (DDR_INIT_ADDR) */
1683static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1684{
1685 unsigned int init_addr = 0; /* Initialization address */
1686
1687 ddr->ddr_init_addr = init_addr;
1688}
1689
1690/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1691static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1692{
1693 unsigned int uia = 0; /* Use initialization address */
1694 unsigned int init_ext_addr = 0; /* Initialization address */
1695
1696 ddr->ddr_init_ext_addr = (0
1697 | ((uia & 0x1) << 31)
1698 | (init_ext_addr & 0xF)
1699 );
1700}
1701
1702/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
Dave Liuec145e82010-03-05 12:22:00 +08001703static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1704 const memctl_options_t *popts)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001705{
1706 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1707 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1708 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1709 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1710 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1711
York Sun34e026f2014-03-27 17:54:47 -07001712#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuec145e82010-03-05 12:22:00 +08001713 if (popts->burst_length == DDR_BL8) {
1714 /* We set BL/2 for fixed BL8 */
1715 rrt = 0; /* BL/2 clocks */
1716 wwt = 0; /* BL/2 clocks */
1717 } else {
1718 /* We need to set BL/2 + 2 to BC4 and OTF */
1719 rrt = 2; /* BL/2 + 2 clocks */
1720 wwt = 2; /* BL/2 + 2 clocks */
1721 }
York Sun34e026f2014-03-27 17:54:47 -07001722#endif
1723
1724#ifdef CONFIG_SYS_FSL_DDR4
1725 dll_lock = 2; /* tDLLK = 1024 clocks */
1726#elif defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +08001727 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1728#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001729 ddr->timing_cfg_4 = (0
1730 | ((rwt & 0xf) << 28)
1731 | ((wrt & 0xf) << 24)
1732 | ((rrt & 0xf) << 20)
1733 | ((wwt & 0xf) << 16)
1734 | (dll_lock & 0x3)
1735 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001736 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001737}
1738
1739/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
York Sune1fd16b2011-01-10 12:03:00 +00001740static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001741{
1742 unsigned int rodt_on = 0; /* Read to ODT on */
1743 unsigned int rodt_off = 0; /* Read to ODT off */
1744 unsigned int wodt_on = 0; /* Write to ODT on */
1745 unsigned int wodt_off = 0; /* Write to ODT off */
1746
York Sun34e026f2014-03-27 17:54:47 -07001747#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1748 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1749 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
York Sune1fd16b2011-01-10 12:03:00 +00001750 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
York Sun34e026f2014-03-27 17:54:47 -07001751 if (cas_latency >= wr_lat)
1752 rodt_on = cas_latency - wr_lat + 1;
Dave Liuc360cea2009-03-14 12:48:30 +08001753 rodt_off = 4; /* 4 clocks */
york5fb8a8a2010-07-02 22:25:56 +00001754 wodt_on = 1; /* 1 clocks */
Dave Liuc360cea2009-03-14 12:48:30 +08001755 wodt_off = 4; /* 4 clocks */
1756#endif
1757
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001758 ddr->timing_cfg_5 = (0
Dave Liu22ff3d02008-11-21 16:31:29 +08001759 | ((rodt_on & 0x1f) << 24)
1760 | ((rodt_off & 0x7) << 20)
1761 | ((wodt_on & 0x1f) << 12)
1762 | ((wodt_off & 0x7) << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001763 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001764 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001765}
1766
York Sun34e026f2014-03-27 17:54:47 -07001767#ifdef CONFIG_SYS_FSL_DDR4
1768static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1769{
1770 unsigned int hs_caslat = 0;
1771 unsigned int hs_wrlat = 0;
1772 unsigned int hs_wrrec = 0;
1773 unsigned int hs_clkadj = 0;
1774 unsigned int hs_wrlvl_start = 0;
1775
1776 ddr->timing_cfg_6 = (0
1777 | ((hs_caslat & 0x1f) << 24)
1778 | ((hs_wrlat & 0x1f) << 19)
1779 | ((hs_wrrec & 0x1f) << 12)
1780 | ((hs_clkadj & 0x1f) << 6)
1781 | ((hs_wrlvl_start & 0x1f) << 0)
1782 );
1783 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1784}
1785
1786static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
1787 const common_timing_params_t *common_dimm)
1788{
1789 unsigned int txpr, tcksre, tcksrx;
1790 unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1791
1792 txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000));
1793 tcksre = max(5, picos_to_mclk(10000));
1794 tcksrx = max(5, picos_to_mclk(10000));
1795 par_lat = 0;
1796 cs_to_cmd = 0;
1797
1798 if (txpr <= 200)
1799 cke_rst = 0;
1800 else if (txpr <= 256)
1801 cke_rst = 1;
1802 else if (txpr <= 512)
1803 cke_rst = 2;
1804 else
1805 cke_rst = 3;
1806
1807 if (tcksre <= 19)
1808 cksre = tcksre - 5;
1809 else
1810 cksre = 15;
1811
1812 if (tcksrx <= 19)
1813 cksrx = tcksrx - 5;
1814 else
1815 cksrx = 15;
1816
1817 ddr->timing_cfg_7 = (0
1818 | ((cke_rst & 0x3) << 28)
1819 | ((cksre & 0xf) << 24)
1820 | ((cksrx & 0xf) << 20)
1821 | ((par_lat & 0xf) << 16)
1822 | ((cs_to_cmd & 0xf) << 4)
1823 );
1824 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1825}
1826
1827static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
1828 const memctl_options_t *popts,
1829 const common_timing_params_t *common_dimm,
1830 unsigned int cas_latency)
1831{
1832 unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1833 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1834 unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
1835 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1836 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1837
1838 rwt_bg = cas_latency + 2 + 4 - wr_lat;
1839 if (rwt_bg < tccdl)
1840 rwt_bg = tccdl - rwt_bg;
1841 else
1842 rwt_bg = 0;
1843
1844 wrt_bg = wr_lat + 4 + 1 - cas_latency;
1845 if (wrt_bg < tccdl)
1846 wrt_bg = tccdl - wrt_bg;
1847 else
1848 wrt_bg = 0;
1849
1850 if (popts->burst_length == DDR_BL8) {
1851 rrt_bg = tccdl - 4;
1852 wwt_bg = tccdl - 4;
1853 } else {
1854 rrt_bg = tccdl - 2;
1855 wwt_bg = tccdl - 4;
1856 }
1857
1858 acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
1859 wrtord_bg = max(4, picos_to_mclk(7500));
1860 pre_all_rec = 0;
1861
1862 ddr->timing_cfg_8 = (0
1863 | ((rwt_bg & 0xf) << 28)
1864 | ((wrt_bg & 0xf) << 24)
1865 | ((rrt_bg & 0xf) << 20)
1866 | ((wwt_bg & 0xf) << 16)
1867 | ((acttoact_bg & 0xf) << 12)
1868 | ((wrtord_bg & 0xf) << 8)
1869 | ((pre_all_rec & 0x1f) << 0)
1870 );
1871
1872 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1873}
1874
1875static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1876{
1877 ddr->timing_cfg_9 = 0;
1878 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1879}
1880
1881static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1882 const dimm_params_t *dimm_params)
1883{
1884 ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
1885 ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
1886 ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
1887 ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
1888 ((dimm_params->dq_mapping[4] & 0x3F) << 2);
1889
1890 ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
1891 ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
1892 ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
1893 ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
1894 ((dimm_params->dq_mapping[11] & 0x3F) << 2);
1895
1896 ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
1897 ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
1898 ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
1899 ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
1900 ((dimm_params->dq_mapping[16] & 0x3F) << 2);
1901
1902 ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
1903 ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
1904 ((dimm_params->dq_mapping[9] & 0x3F) << 14) |
1905 dimm_params->dq_mapping_ors;
1906
1907 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
1908 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
1909 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
1910 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
1911}
1912static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
1913 const memctl_options_t *popts)
1914{
1915 int rd_pre;
1916
1917 rd_pre = popts->quad_rank_present ? 1 : 0;
1918
1919 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
1920
1921 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
1922}
1923#endif /* CONFIG_SYS_FSL_DDR4 */
1924
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001925/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
Dave Liuc360cea2009-03-14 12:48:30 +08001926static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001927{
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001928 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1929 /* Normal Operation Full Calibration Time (tZQoper) */
1930 unsigned int zqoper = 0;
1931 /* Normal Operation Short Calibration Time (tZQCS) */
1932 unsigned int zqcs = 0;
York Sun34e026f2014-03-27 17:54:47 -07001933#ifdef CONFIG_SYS_FSL_DDR4
1934 unsigned int zqcs_init;
1935#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001936
Dave Liuc360cea2009-03-14 12:48:30 +08001937 if (zq_en) {
York Sun34e026f2014-03-27 17:54:47 -07001938#ifdef CONFIG_SYS_FSL_DDR4
1939 zqinit = 10; /* 1024 clocks */
1940 zqoper = 9; /* 512 clocks */
1941 zqcs = 7; /* 128 clocks */
1942 zqcs_init = 5; /* 1024 refresh sequences */
1943#else
Dave Liuc360cea2009-03-14 12:48:30 +08001944 zqinit = 9; /* 512 clocks */
1945 zqoper = 8; /* 256 clocks */
1946 zqcs = 6; /* 64 clocks */
York Sun34e026f2014-03-27 17:54:47 -07001947#endif
Dave Liuc360cea2009-03-14 12:48:30 +08001948 }
1949
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001950 ddr->ddr_zq_cntl = (0
1951 | ((zq_en & 0x1) << 31)
1952 | ((zqinit & 0xF) << 24)
1953 | ((zqoper & 0xF) << 16)
1954 | ((zqcs & 0xF) << 8)
York Sun34e026f2014-03-27 17:54:47 -07001955#ifdef CONFIG_SYS_FSL_DDR4
1956 | ((zqcs_init & 0xF) << 0)
1957#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001958 );
York Sune1fd16b2011-01-10 12:03:00 +00001959 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001960}
1961
1962/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
Dave Liubdc9f7b2009-12-16 10:24:37 -06001963static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1964 const memctl_options_t *popts)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001965{
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001966 /*
1967 * First DQS pulse rising edge after margining mode
1968 * is programmed (tWL_MRD)
1969 */
1970 unsigned int wrlvl_mrd = 0;
1971 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1972 unsigned int wrlvl_odten = 0;
1973 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1974 unsigned int wrlvl_dqsen = 0;
1975 /* WRLVL_SMPL: Write leveling sample time */
1976 unsigned int wrlvl_smpl = 0;
1977 /* WRLVL_WLR: Write leveling repeition time */
1978 unsigned int wrlvl_wlr = 0;
1979 /* WRLVL_START: Write leveling start time */
1980 unsigned int wrlvl_start = 0;
1981
Dave Liuc360cea2009-03-14 12:48:30 +08001982 /* suggest enable write leveling for DDR3 due to fly-by topology */
1983 if (wrlvl_en) {
1984 /* tWL_MRD min = 40 nCK, we set it 64 */
1985 wrlvl_mrd = 0x6;
1986 /* tWL_ODTEN 128 */
1987 wrlvl_odten = 0x7;
1988 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1989 wrlvl_dqsen = 0x5;
1990 /*
Dave Liubdc9f7b2009-12-16 10:24:37 -06001991 * Write leveling sample time at least need 6 clocks
1992 * higher than tWLO to allow enough time for progagation
1993 * delay and sampling the prime data bits.
Dave Liuc360cea2009-03-14 12:48:30 +08001994 */
1995 wrlvl_smpl = 0xf;
1996 /*
1997 * Write leveling repetition time
1998 * at least tWLO + 6 clocks clocks
york5fb8a8a2010-07-02 22:25:56 +00001999 * we set it 64
Dave Liuc360cea2009-03-14 12:48:30 +08002000 */
york5fb8a8a2010-07-02 22:25:56 +00002001 wrlvl_wlr = 0x6;
Dave Liuc360cea2009-03-14 12:48:30 +08002002 /*
2003 * Write leveling start time
2004 * The value use for the DQS_ADJUST for the first sample
York Sune1fd16b2011-01-10 12:03:00 +00002005 * when write leveling is enabled. It probably needs to be
2006 * overriden per platform.
Dave Liuc360cea2009-03-14 12:48:30 +08002007 */
2008 wrlvl_start = 0x8;
Dave Liubdc9f7b2009-12-16 10:24:37 -06002009 /*
2010 * Override the write leveling sample and start time
2011 * according to specific board
2012 */
2013 if (popts->wrlvl_override) {
2014 wrlvl_smpl = popts->wrlvl_sample;
2015 wrlvl_start = popts->wrlvl_start;
2016 }
Dave Liuc360cea2009-03-14 12:48:30 +08002017 }
2018
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002019 ddr->ddr_wrlvl_cntl = (0
2020 | ((wrlvl_en & 0x1) << 31)
2021 | ((wrlvl_mrd & 0x7) << 24)
2022 | ((wrlvl_odten & 0x7) << 20)
2023 | ((wrlvl_dqsen & 0x7) << 16)
2024 | ((wrlvl_smpl & 0xf) << 12)
2025 | ((wrlvl_wlr & 0x7) << 8)
Dave Liu22ff3d02008-11-21 16:31:29 +08002026 | ((wrlvl_start & 0x1F) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002027 );
York Sune1fd16b2011-01-10 12:03:00 +00002028 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
York Sun57495e42012-10-08 07:44:22 +00002029 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2030 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2031 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2032 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2033
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002034}
2035
2036/* DDR Self Refresh Counter (DDR_SR_CNTR) */
Dave Liu22cca7e2008-11-21 16:31:35 +08002037static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002038{
Dave Liu22cca7e2008-11-21 16:31:35 +08002039 /* Self Refresh Idle Threshold */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002040 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2041}
2042
york7fd101c2010-07-02 22:25:54 +00002043static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2044{
2045 if (popts->addr_hash) {
2046 ddr->ddr_eor = 0x40000000; /* address hash enable */
Kumar Galac2a63f42011-03-18 11:53:06 -05002047 puts("Address hashing enabled.\n");
york7fd101c2010-07-02 22:25:54 +00002048 }
2049}
2050
York Sune1fd16b2011-01-10 12:03:00 +00002051static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2052{
2053 ddr->ddr_cdr1 = popts->ddr_cdr1;
2054 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2055}
2056
York Sun57495e42012-10-08 07:44:22 +00002057static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2058{
2059 ddr->ddr_cdr2 = popts->ddr_cdr2;
2060 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2061}
2062
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002063unsigned int
2064check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2065{
2066 unsigned int res = 0;
2067
2068 /*
2069 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2070 * not set at the same time.
2071 */
2072 if (ddr->ddr_sdram_cfg & 0x10000000
2073 && ddr->ddr_sdram_cfg & 0x00008000) {
2074 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2075 " should not be set at the same time.\n");
2076 res++;
2077 }
2078
2079 return res;
2080}
2081
2082unsigned int
2083compute_fsl_memctl_config_regs(const memctl_options_t *popts,
2084 fsl_ddr_cfg_regs_t *ddr,
2085 const common_timing_params_t *common_dimm,
2086 const dimm_params_t *dimm_params,
Haiying Wangfc0c2b62010-12-01 10:35:31 -05002087 unsigned int dbw_cap_adj,
2088 unsigned int size_only)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002089{
2090 unsigned int i;
2091 unsigned int cas_latency;
2092 unsigned int additive_latency;
Dave Liu22cca7e2008-11-21 16:31:35 +08002093 unsigned int sr_it;
Dave Liuc360cea2009-03-14 12:48:30 +08002094 unsigned int zq_en;
2095 unsigned int wrlvl_en;
York Sune1fd16b2011-01-10 12:03:00 +00002096 unsigned int ip_rev = 0;
2097 unsigned int unq_mrs_en = 0;
York Sun58edbc92010-10-18 13:46:50 -07002098 int cs_en = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002099
2100 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2101
2102 if (common_dimm == NULL) {
2103 printf("Error: subset DIMM params struct null pointer\n");
2104 return 1;
2105 }
2106
2107 /*
2108 * Process overrides first.
2109 *
2110 * FIXME: somehow add dereated caslat to this
2111 */
2112 cas_latency = (popts->cas_latency_override)
2113 ? popts->cas_latency_override_value
York Sun34e026f2014-03-27 17:54:47 -07002114 : common_dimm->lowest_common_spd_caslat;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002115
2116 additive_latency = (popts->additive_latency_override)
2117 ? popts->additive_latency_override_value
2118 : common_dimm->additive_latency;
2119
Dave Liu22cca7e2008-11-21 16:31:35 +08002120 sr_it = (popts->auto_self_refresh_en)
2121 ? popts->sr_it
2122 : 0;
Dave Liuc360cea2009-03-14 12:48:30 +08002123 /* ZQ calibration */
2124 zq_en = (popts->zq_en) ? 1 : 0;
2125 /* write leveling */
2126 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
Dave Liu22cca7e2008-11-21 16:31:35 +08002127
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002128 /* Chip Select Memory Bounds (CSn_BNDS) */
2129 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Suna4c66502012-08-17 08:22:39 +00002130 unsigned long long ea, sa;
york076bff82010-07-02 22:25:52 +00002131 unsigned int cs_per_dimm
2132 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2133 unsigned int dimm_number
2134 = i / cs_per_dimm;
2135 unsigned long long rank_density
York Suna4c66502012-08-17 08:22:39 +00002136 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002137
york076bff82010-07-02 22:25:52 +00002138 if (dimm_params[dimm_number].n_ranks == 0) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002139 debug("Skipping setup of CS%u "
york5800e7a2010-07-02 22:25:53 +00002140 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002141 continue;
2142 }
York Suna4c66502012-08-17 08:22:39 +00002143 if (popts->memctl_interleaving) {
york076bff82010-07-02 22:25:52 +00002144 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
York Suna4c66502012-08-17 08:22:39 +00002145 case FSL_DDR_CS0_CS1_CS2_CS3:
2146 break;
york076bff82010-07-02 22:25:52 +00002147 case FSL_DDR_CS0_CS1:
2148 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
York Sun58edbc92010-10-18 13:46:50 -07002149 if (i > 1)
2150 cs_en = 0;
york076bff82010-07-02 22:25:52 +00002151 break;
2152 case FSL_DDR_CS2_CS3:
York Suna4c66502012-08-17 08:22:39 +00002153 default:
York Sun58edbc92010-10-18 13:46:50 -07002154 if (i > 0)
2155 cs_en = 0;
york076bff82010-07-02 22:25:52 +00002156 break;
york076bff82010-07-02 22:25:52 +00002157 }
York Suna4c66502012-08-17 08:22:39 +00002158 sa = common_dimm->base_address;
York Sun123922b2012-10-08 07:44:23 +00002159 ea = sa + common_dimm->total_mem - 1;
York Suna4c66502012-08-17 08:22:39 +00002160 } else if (!popts->memctl_interleaving) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002161 /*
2162 * If memory interleaving between controllers is NOT
2163 * enabled, the starting address for each memory
2164 * controller is distinct. However, because rank
2165 * interleaving is enabled, the starting and ending
2166 * addresses of the total memory on that memory
2167 * controller needs to be programmed into its
2168 * respective CS0_BNDS.
2169 */
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002170 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2171 case FSL_DDR_CS0_CS1_CS2_CS3:
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002172 sa = common_dimm->base_address;
York Sun123922b2012-10-08 07:44:23 +00002173 ea = sa + common_dimm->total_mem - 1;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002174 break;
2175 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
York Suna4c66502012-08-17 08:22:39 +00002176 if ((i >= 2) && (dimm_number == 0)) {
york076bff82010-07-02 22:25:52 +00002177 sa = dimm_params[dimm_number].base_address +
York Suna4c66502012-08-17 08:22:39 +00002178 2 * rank_density;
2179 ea = sa + 2 * rank_density - 1;
york076bff82010-07-02 22:25:52 +00002180 } else {
2181 sa = dimm_params[dimm_number].base_address;
York Suna4c66502012-08-17 08:22:39 +00002182 ea = sa + 2 * rank_density - 1;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002183 }
2184 break;
2185 case FSL_DDR_CS0_CS1:
york076bff82010-07-02 22:25:52 +00002186 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2187 sa = dimm_params[dimm_number].base_address;
York Suna4c66502012-08-17 08:22:39 +00002188 ea = sa + rank_density - 1;
2189 if (i != 1)
2190 sa += (i % cs_per_dimm) * rank_density;
2191 ea += (i % cs_per_dimm) * rank_density;
york076bff82010-07-02 22:25:52 +00002192 } else {
2193 sa = 0;
2194 ea = 0;
2195 }
2196 if (i == 0)
York Suna4c66502012-08-17 08:22:39 +00002197 ea += rank_density;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002198 break;
2199 case FSL_DDR_CS2_CS3:
york076bff82010-07-02 22:25:52 +00002200 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2201 sa = dimm_params[dimm_number].base_address;
York Suna4c66502012-08-17 08:22:39 +00002202 ea = sa + rank_density - 1;
2203 if (i != 3)
2204 sa += (i % cs_per_dimm) * rank_density;
2205 ea += (i % cs_per_dimm) * rank_density;
york076bff82010-07-02 22:25:52 +00002206 } else {
2207 sa = 0;
2208 ea = 0;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002209 }
york076bff82010-07-02 22:25:52 +00002210 if (i == 2)
2211 ea += (rank_density >> dbw_cap_adj);
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002212 break;
2213 default: /* No bank(chip-select) interleaving */
York Suna4c66502012-08-17 08:22:39 +00002214 sa = dimm_params[dimm_number].base_address;
2215 ea = sa + rank_density - 1;
2216 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2217 sa += (i % cs_per_dimm) * rank_density;
2218 ea += (i % cs_per_dimm) * rank_density;
2219 } else {
2220 sa = 0;
2221 ea = 0;
2222 }
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002223 break;
2224 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002225 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002226
2227 sa >>= 24;
2228 ea >>= 24;
2229
York Sun123922b2012-10-08 07:44:23 +00002230 if (cs_en) {
2231 ddr->cs[i].bnds = (0
York Sund4263b82013-06-03 12:39:06 -07002232 | ((sa & 0xffff) << 16) /* starting address */
2233 | ((ea & 0xffff) << 0) /* ending address */
York Sun123922b2012-10-08 07:44:23 +00002234 );
2235 } else {
York Sund8556db2013-06-25 11:37:45 -07002236 /* setting bnds to 0xffffffff for inactive CS */
2237 ddr->cs[i].bnds = 0xffffffff;
York Sun123922b2012-10-08 07:44:23 +00002238 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002239
Haiying Wang1f293b42008-10-03 12:37:26 -04002240 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
York Sun123922b2012-10-08 07:44:23 +00002241 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2242 set_csn_config_2(i, ddr);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002243 }
2244
Haiying Wangfc0c2b62010-12-01 10:35:31 -05002245 /*
2246 * In the case we only need to compute the ddr sdram size, we only need
2247 * to set csn registers, so return from here.
2248 */
2249 if (size_only)
2250 return 0;
2251
york7fd101c2010-07-02 22:25:54 +00002252 set_ddr_eor(ddr, popts);
2253
York Sun5614e712013-09-30 09:22:09 -07002254#if !defined(CONFIG_SYS_FSL_DDR1)
York Sun123922b2012-10-08 07:44:23 +00002255 set_timing_cfg_0(ddr, popts, dimm_params);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002256#endif
2257
York Sund4263b82013-06-03 12:39:06 -07002258 set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
2259 additive_latency);
Dave Liuc360cea2009-03-14 12:48:30 +08002260 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002261 set_timing_cfg_2(ddr, popts, common_dimm,
2262 cas_latency, additive_latency);
2263
York Sune1fd16b2011-01-10 12:03:00 +00002264 set_ddr_cdr1(ddr, popts);
York Sun57495e42012-10-08 07:44:22 +00002265 set_ddr_cdr2(ddr, popts);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002266 set_ddr_sdram_cfg(ddr, popts, common_dimm);
York Sune1fd16b2011-01-10 12:03:00 +00002267 ip_rev = fsl_ddr_get_version();
2268 if (ip_rev > 0x40400)
2269 unq_mrs_en = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002270
York Sune1fd16b2011-01-10 12:03:00 +00002271 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002272 set_ddr_sdram_mode(ddr, popts, common_dimm,
York Sune1fd16b2011-01-10 12:03:00 +00002273 cas_latency, additive_latency, unq_mrs_en);
Valentin Longchamp7e157b02013-10-18 11:47:20 +02002274 set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
York Sun34e026f2014-03-27 17:54:47 -07002275#ifdef CONFIG_SYS_FSL_DDR4
2276 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2277 set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
2278#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002279 set_ddr_sdram_interval(ddr, popts, common_dimm);
2280 set_ddr_data_init(ddr);
2281 set_ddr_sdram_clk_cntl(ddr, popts);
2282 set_ddr_init_addr(ddr);
2283 set_ddr_init_ext_addr(ddr);
Dave Liuec145e82010-03-05 12:22:00 +08002284 set_timing_cfg_4(ddr, popts);
York Sune1fd16b2011-01-10 12:03:00 +00002285 set_timing_cfg_5(ddr, cas_latency);
York Sun34e026f2014-03-27 17:54:47 -07002286#ifdef CONFIG_SYS_FSL_DDR4
2287 set_ddr_sdram_cfg_3(ddr, popts);
2288 set_timing_cfg_6(ddr);
2289 set_timing_cfg_7(ddr, common_dimm);
2290 set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
2291 set_timing_cfg_9(ddr);
2292 set_ddr_dq_mapping(ddr, dimm_params);
2293#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002294
Dave Liuc360cea2009-03-14 12:48:30 +08002295 set_ddr_zq_cntl(ddr, zq_en);
Dave Liubdc9f7b2009-12-16 10:24:37 -06002296 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002297
Dave Liu22cca7e2008-11-21 16:31:35 +08002298 set_ddr_sr_cntr(ddr, sr_it);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002299
York Sune1fd16b2011-01-10 12:03:00 +00002300 set_ddr_sdram_rcw(ddr, popts, common_dimm);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002301
York Suncb930712013-06-25 11:37:41 -07002302#ifdef CONFIG_SYS_FSL_DDR_EMU
2303 /* disble DDR training for emulator */
2304 ddr->debug[2] = 0x00000400;
2305 ddr->debug[4] = 0xff800000;
2306#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002307 return check_fsl_memctl_config_regs(ddr);
2308}