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wdenka87589d2005-06-10 10:00:19 +00001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34#define CONFIG_HMI1001 1 /* HMI1001 board */
35
36#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37
38#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39#define BOOTFLAG_WARM 0x02 /* Software reboot */
40
41#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
42#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
43# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
44#endif
45
46#define CONFIG_BOARD_EARLY_INIT_R
47
48/*
49 * Serial console configuration
50 */
51#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
52#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
53#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
54
Wolfgang Denk08abe152005-07-21 15:23:29 +020055/* Partitions */
56#define CONFIG_DOS_PARTITION
57
wdenka87589d2005-06-10 10:00:19 +000058/*
59 * Supported commands
60 */
61#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
wdenk342717f2005-06-27 13:30:03 +000062 CFG_CMD_DATE | \
Wolfgang Denk9f96ae42005-08-30 13:04:12 +020063 CFG_CMD_DISPLAY | \
wdenka87589d2005-06-10 10:00:19 +000064 CFG_CMD_DHCP | \
wdenk342717f2005-06-27 13:30:03 +000065 CFG_CMD_EEPROM | \
66 CFG_CMD_I2C | \
Wolfgang Denk08abe152005-07-21 15:23:29 +020067 CFG_CMD_IDE | \
wdenka87589d2005-06-10 10:00:19 +000068 CFG_CMD_NFS | \
Wolfgang Denk98128f32005-08-16 15:17:53 +020069 CFG_CMD_PCI | \
Wolfgang Denk9f96ae42005-08-30 13:04:12 +020070 CFG_CMD_SNTP )
wdenka87589d2005-06-10 10:00:19 +000071
72/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
73#include <cmd_confdefs.h>
74
75#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
76
77#if (TEXT_BASE == 0xFFF00000) /* Boot low */
78# define CFG_LOWBOOT 1
79#endif
80
81/*
82 * Autobooting
83 */
84#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
85
86#define CONFIG_PREBOOT "echo;" \
87 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
88 "echo"
89
90#undef CONFIG_BOOTARGS
91
92#define CONFIG_EXTRA_ENV_SETTINGS \
93 "netdev=eth0\0" \
94 "nfsargs=setenv bootargs root=/dev/nfs rw " \
95 "nfsroot=$(serverip):$(rootpath)\0" \
96 "ramargs=setenv bootargs root=/dev/ram rw\0" \
97 "addip=setenv bootargs $(bootargs) " \
98 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
99 ":$(hostname):$(netdev):off panic=1\0" \
100 "flash_nfs=run nfsargs addip;" \
101 "bootm $(kernel_addr)\0" \
102 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
103 "rootpath=/opt/eldk/ppc_82xx\0" \
104 ""
105
106#define CONFIG_BOOTCOMMAND "run net_nfs"
107
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200108#define CONFIG_MISC_INIT_R 1
109
wdenka87589d2005-06-10 10:00:19 +0000110/*
111 * IPB Bus clocking configuration.
112 */
113#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
114
115/*
wdenk342717f2005-06-27 13:30:03 +0000116 * I2C configuration
117 */
118#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
119#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
120
121#define CFG_I2C_SPEED 100000 /* 100 kHz */
122#define CFG_I2C_SLAVE 0x7F
123
124/*
125 * EEPROM configuration
126 */
127#define CFG_I2C_EEPROM_ADDR 0x58
128#define CFG_I2C_EEPROM_ADDR_LEN 1
129#define CFG_EEPROM_PAGE_WRITE_BITS 4
130#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
131
132/*
133 * RTC configuration
134 */
135#define CONFIG_RTC_PCF8563
136#define CFG_I2C_RTC_ADDR 0x51
137
138/*
wdenka87589d2005-06-10 10:00:19 +0000139 * Flash configuration
140 */
141#define CFG_FLASH_BASE 0xFF800000
142
143#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
144#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
145
146#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
147#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
148 (= chip selects) */
149#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
150#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
151
152#define CFG_FLASH_CFI_DRIVER
153#define CFG_FLASH_CFI
154#define CFG_FLASH_EMPTY_INFO
155#define CFG_FLASH_CFI_AMD_RESET
wdenka87589d2005-06-10 10:00:19 +0000156
157/*
158 * Environment settings
159 */
160#define CFG_ENV_IS_IN_FLASH 1
161#define CFG_ENV_SIZE 0x4000
162#define CFG_ENV_SECT_SIZE 0x20000
wdenk024447b2005-06-20 10:28:38 +0000163#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
164#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
wdenka87589d2005-06-10 10:00:19 +0000165
166/*
167 * Memory map
168 */
169#define CFG_MBAR 0xF0000000
170#define CFG_SDRAM_BASE 0x00000000
171#define CFG_DEFAULT_MBAR 0x80000000
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200172#define CFG_DISPLAY_BASE 0x80600000
173#define CFG_STATUS1_BASE 0x80600200
174#define CFG_STATUS2_BASE 0x80600300
wdenka87589d2005-06-10 10:00:19 +0000175
176/* Settings for XLB = 132 MHz */
177#define SDRAM_DDR 1
178#define SDRAM_MODE 0x018D0000
179#define SDRAM_EMODE 0x40090000
180#define SDRAM_CONTROL 0x714f0f00
181#define SDRAM_CONFIG1 0x73722930
182#define SDRAM_CONFIG2 0x47770000
183#define SDRAM_TAPDELAY 0x10000000
184
185/* Use ON-Chip SRAM until RAM will be available */
186#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
187#ifdef CONFIG_POST
188/* preserve space for the post_word at end of on-chip SRAM */
189#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
190#else
191#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
192#endif
193
194
195#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
196#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
197#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
198
199#define CFG_MONITOR_BASE TEXT_BASE
200#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
201# define CFG_RAMBOOT 1
202#endif
203
204#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk342717f2005-06-27 13:30:03 +0000205#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
wdenka87589d2005-06-10 10:00:19 +0000206#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
207
208/*
209 * Ethernet configuration
210 */
211#define CONFIG_MPC5xxx_FEC 1
212#define CONFIG_PHY_ADDR 0x00
213
214/*
215 * GPIO configuration
216 */
217#define CFG_GPS_PORT_CONFIG 0x01051004
218
219/*
wdenka87589d2005-06-10 10:00:19 +0000220 * Miscellaneous configurable options
221 */
222#define CFG_LONGHELP /* undef to save memory */
223#define CFG_PROMPT "=> " /* Monitor Command Prompt */
224#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
225#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
226#else
227#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
228#endif
229#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
230#define CFG_MAXARGS 16 /* max number of command args */
231#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
232
233/* Enable an alternate, more extensive memory test */
234#define CFG_ALT_MEMTEST
235
236#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
237#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
238
239#define CFG_LOAD_ADDR 0x100000 /* default load address */
240
241#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
242
243/*
244 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
245 * which is normally part of the default commands (CFV_CMD_DFL)
246 */
247#define CONFIG_LOOPW
248
249/*
250 * Various low-level settings
251 */
252#if defined(CONFIG_MPC5200)
253#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
254#define CFG_HID0_FINAL HID0_ICE
255#else
256#define CFG_HID0_INIT 0
257#define CFG_HID0_FINAL 0
258#endif
259
260#define CFG_BOOTCS_START CFG_FLASH_BASE
261#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
262#define CFG_BOOTCS_CFG 0x0004FB00
263#define CFG_CS0_START CFG_FLASH_BASE
264#define CFG_CS0_SIZE CFG_FLASH_SIZE
265
266/* 8Mbit SRAM @0x80100000 */
267#define CFG_CS1_START 0x80100000
268#define CFG_CS1_SIZE 0x00100000
269#define CFG_CS1_CFG 0x19B00
270
271/* FRAM 32Kbyte @0x80700000 */
272#define CFG_CS2_START 0x80700000
273#define CFG_CS2_SIZE 0x00008000
274#define CFG_CS2_CFG 0x19800
275
276/* Display H1, Status Inputs, EPLD @0x80600000 */
277#define CFG_CS3_START 0x80600000
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200278#define CFG_CS3_SIZE 0x00100000
Wolfgang Denkf7fbf262005-08-30 13:43:18 +0200279#define CFG_CS3_CFG 0x00019800
wdenka87589d2005-06-10 10:00:19 +0000280
281#define CFG_CS_BURST 0x00000000
282#define CFG_CS_DEADCYCLE 0x33333333
283
Wolfgang Denk08abe152005-07-21 15:23:29 +0200284/*-----------------------------------------------------------------------
285 * IDE/ATA stuff Supports IDE harddisk
286 *-----------------------------------------------------------------------
287 */
288
289#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
290
291#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
292#undef CONFIG_IDE_LED /* LED for ide not supported */
293
294#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
295#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
296
Wolfgang Denk9d3338d2005-08-10 10:06:25 +0200297#define CONFIG_IDE_PREINIT 1
298
Wolfgang Denk08abe152005-07-21 15:23:29 +0200299#define CFG_ATA_IDE0_OFFSET 0x0000
300
301#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
302
303/* Offset for data I/O */
304#define CFG_ATA_DATA_OFFSET (0x0060)
305
306/* Offset for normal register accesses */
307#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
308
309/* Offset for alternate registers */
310#define CFG_ATA_ALT_OFFSET (0x005C)
311
312/* Interval between registers */
313#define CFG_ATA_STRIDE 4
314
315#define CONFIG_ATAPI 1
316
Wolfgang Denk98128f32005-08-16 15:17:53 +0200317/*
318 * PCI Mapping:
319 * 0x40000000 - 0x4fffffff - PCI Memory
320 * 0x50000000 - 0x50ffffff - PCI IO Space
321 */
322#define CONFIG_PCI 1
323#define CONFIG_PCI_PNP 1
324#define CONFIG_PCI_SCAN_SHOW 1
325
326#define CONFIG_PCI_MEM_BUS 0x40000000
327#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
328#define CONFIG_PCI_MEM_SIZE 0x10000000
329
330#define CONFIG_PCI_IO_BUS 0x50000000
331#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
332#define CONFIG_PCI_IO_SIZE 0x01000000
333
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200334/*---------------------------------------------------------------------*/
335/* Display addresses */
336/*---------------------------------------------------------------------*/
337
338#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
339#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
340
wdenka87589d2005-06-10 10:00:19 +0000341#endif /* __CONFIG_H */