blob: f8cdade7636c079ef244821c3900051a4df472e5 [file] [log] [blame]
Michal Simekf7c8e492018-03-28 15:36:36 +02001/*
2 * Configuration for Xilinx ZynqMP zcu104
3 *
4 * (C) Copyright 2017 Xilinx, Inc.
5 * Michal Simek <michal.simek@xilinx.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_ZYNQMP_ZCU104_H
11#define __CONFIG_ZYNQMP_ZCU104_H
12
13#define CONFIG_ZYNQ_SDHCI1
14#define CONFIG_SYS_I2C_MAX_HOPS 1
15#define CONFIG_SYS_NUM_I2C_BUSES 9
16#define CONFIG_SYS_I2C_BUSES { \
17 {0, {I2C_NULL_HOP} }, \
18 {0, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
19 {0, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
20 {0, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
21 {0, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
22 {0, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
23 {0, {{I2C_MUX_PCA9548, 0x74, 5} } }, \
24 {0, {{I2C_MUX_PCA9548, 0x74, 6} } }, \
25 {0, {{I2C_MUX_PCA9548, 0x74, 7} } }, \
26 }
27
28#define CONFIG_PCA953X
29
30#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
31
32#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
33
34#include <configs/xilinx_zynqmp.h>
35
36#endif /* __CONFIG_ZYNQMP_ZCU104_H */