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gerrit.cesnet.cz / github / trini / u-boot / f7ae6b682c42a82a38ebeb3ea4a20f23ca623563 / . / drivers / reset / Kconfig
blob: cff00820e486e0025dbf07e0ede2372220b34bb8 [file] [log] [blame]
Stephen Warren89c1e2d2016-06-17 09:43:58 -0600[diff] [blame]1menu "Reset Controller Support"
2
3config DM_RESET
4 bool "Enable reset controllers using Driver Model"
5 depends on DM && OF_CONTROL
6 help
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
11 cases this API is applicable to chips outside the CPU as well,
12 although driving such reset isgnals using GPIOs may be more
13 appropriate in this case.
14
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]15config SANDBOX_RESET
16 bool "Enable the sandbox reset test driver"
17 depends on DM_MAILBOX && SANDBOX
18 help
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
21 doing anything beyond a little error checking.
22
Patrice Chotard584861f2017-03-22 10:54:03 +0100[diff] [blame]23config STI_RESET
24 bool "Enable the STi reset"
25 depends on ARCH_STI
26 help
27 Support for reset controllers on STMicroelectronics STiH407 family SoCs.
28 Say Y if you want to control reset signals provided by system config
29 block.
30
Patrice Chotard23a06412017-09-13 18:00:07 +0200[diff] [blame]31config STM32_RESET
32 bool "Enable the STM32 reset"
Patrick Delaunaya7519b32018-03-12 10:46:14 +0100[diff] [blame]33 depends on STM32 || ARCH_STM32MP
Patrice Chotard23a06412017-09-13 18:00:07 +0200[diff] [blame]34 help
35 Support for reset controllers on STMicroelectronics STM32 family SoCs.
36 This resset driver is compatible with STM32 F4/F7 and H7 SoCs.
37
Stephen Warrenfe60f062016-09-13 10:45:58 -0600[diff] [blame]38config TEGRA_CAR_RESET
39 bool "Enable Tegra CAR-based reset driver"
40 depends on TEGRA_CAR
41 help
42 Enable support for manipulating Tegra's on-SoC reset signals via
43 direct register access to the Tegra CAR (Clock And Reset controller).
44
Stephen Warren4dd99d12016-08-08 11:28:25 -0600[diff] [blame]45config TEGRA186_RESET
46 bool "Enable Tegra186 BPMP-based reset driver"
47 depends on TEGRA186_BPMP
48 help
49 Enable support for manipulating Tegra's on-SoC reset signals via IPC
50 requests to the BPMP (Boot and Power Management Processor).
51
Andreas Dannenberg65c8a792018-08-27 15:57:41 +0530[diff] [blame]52config RESET_TI_SCI
53 bool "TI System Control Interface (TI SCI) reset driver"
54 depends on DM_RESET && TI_SCI_PROTOCOL
55 help
56 This enables the reset driver support over TI System Control Interface
57 available on some new TI's SoCs. If you wish to use reset resources
58 managed by the TI System Controller, say Y here. Otherwise, say N.
59
Álvaro Fernández Rojas18393f72017-05-03 15:10:21 +0200[diff] [blame]60config RESET_BCM6345
61 bool "Reset controller driver for BCM6345"
62 depends on DM_RESET && ARCH_BMIPS
63 help
64 Support reset controller on BCM6345.
65
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900[diff] [blame]66config RESET_UNIPHIER
67 bool "Reset controller driver for UniPhier SoCs"
68 depends on ARCH_UNIPHIER
69 default y
70 help
71 Support for reset controllers on UniPhier SoCs.
72 Say Y if you want to control reset signals provided by System Control
73 block, Media I/O block, Peripheral Block.
74
maxims@google.com858d4972017-04-17 12:00:24 -0700[diff] [blame]75config AST2500_RESET
76 bool "Reset controller driver for AST2500 SoCs"
77 depends on DM_RESET && WDT_ASPEED
78 default y if ASPEED_AST2500
79 help
80 Support for reset controller on AST2500 SoC. This controller uses
81 watchdog to reset different peripherals and thus only supports
82 resets that are supported by watchdog. The main limitation though
83 is that some reset signals, like I2C or MISC reset multiple devices.
84
Elaine Zhang760188c2017-12-19 18:22:37 +0800[diff] [blame]85config RESET_ROCKCHIP
86 bool "Reset controller driver for Rockchip SoCs"
87 depends on DM_RESET && ARCH_ROCKCHIP && CLK
88 default y
89 help
90 Support for reset controller on rockchip SoC. The main limitation
91 though is that some reset signals, like I2C or MISC reset multiple
92 devices.
93
Neil Armstrong20367bb2018-03-29 14:55:25 +0200[diff] [blame]94config RESET_MESON
95 bool "Reset controller driver for Amlogic Meson SoCs"
96 depends on DM_RESET && ARCH_MESON
97 imply REGMAP
98 default y
99 help
100 Support for reset controller on Amlogic Meson SoC.
101
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500[diff] [blame]102config RESET_SOCFPGA
103 bool "Reset controller driver for SoCFPGA"
104 depends on DM_RESET && ARCH_SOCFPGA
105 default y
106 help
107 Support for reset controller on SoCFPGA platform.
108
Weijie Gao3e066bc2018-12-20 16:12:51 +0800[diff] [blame]109config RESET_MEDIATEK
110 bool "Reset controller driver for MediaTek SoCs"
111 depends on DM_RESET && ARCH_MEDIATEK && CLK
112 default y
113 help
114 Support for reset controller on MediaTek SoCs.
115
Weijie Gaof7ae6b62019-09-25 17:45:29 +0800[diff] [blame^]116config RESET_MTMIPS
117 bool "Reset controller driver for MediaTek MIPS platform"
118 depends on DM_RESET && ARCH_MTMIPS
119 default y
120 help
121 Support for reset controller on MediaTek MIPS platform.
122
Jagan Teki99ba4302019-01-18 22:18:13 +0530[diff] [blame]123config RESET_SUNXI
124 bool "RESET support for Allwinner SoCs"
125 depends on DM_RESET && ARCH_SUNXI
126 default y
127 help
128 This enables support for common reset driver for
129 Allwinner SoCs.
130
Shawn Guof5e6c162019-03-20 15:32:39 +0800[diff] [blame]131config RESET_HISILICON
132 bool "Reset controller driver for HiSilicon SoCs"
133 depends on DM_RESET
134 help
135 Support for reset controller on HiSilicon SoCs.
136
Patrick Wildt6300dc42019-10-03 16:08:35 +0200[diff] [blame]137config RESET_IMX7
138 bool "i.MX7/8 Reset Driver"
139 depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M)
140 default y
141 help
142 Support for reset controller on i.MX7/8 SoCs.
143
Stephen Warren89c1e2d2016-06-17 09:43:58 -0600[diff] [blame]144endmenu