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gerrit.cesnet.cz / github / trini / u-boot / f77b5a4cd1365bdb7bb6e108db374bb1c68b6f9f / . / drivers / clk / renesas / r8a7796-cpg-mssr.c
blob: de1b018b61bcef86971081c625aea44fd1acaf61 [file] [log] [blame]
Marek Vasutf77b5a42018-01-08 14:01:40 +0100[diff] [blame^]1/*
2 * Renesas R8A7796 CPG MSSR driver
3 *
4 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
8 *
9 * Copyright (C) 2016 Glider bvba
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#include <common.h>
15#include <clk-uclass.h>
16#include <dm.h>
17
18#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
19
20#include "renesas-cpg-mssr.h"
21
22static const struct cpg_core_clk r8a7796_core_clks[] = {
23 /* External Clock Inputs */
24 DEF_INPUT("extal", CLK_EXTAL),
25 DEF_INPUT("extalr", CLK_EXTALR),
26
27 /* Internal Core Clocks */
28 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
29 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
30 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
31 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
32 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
33 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
34
35 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
36 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
37 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
38 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
39 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
40 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
41 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
42 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
43
44 /* Core Clock Outputs */
45 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
46 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
47 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
48 DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
49 DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
50 DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
51 DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
52 DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
53 DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
54 DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
55 DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
56 DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
57 DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
58 DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
59 DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
60 DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
61 DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
62 DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
63 DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
64 DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
65
66 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
67 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
68 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
69 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
70
71 DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
72
73 DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
74 DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
75
76 /* NOTE: HDMI, CSI, CAN etc. clock are missing */
77
78 DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
79};
80
81static const struct mssr_mod_clk r8a7796_mod_clks[] = {
82 DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
83 DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
84 DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
85 DEF_MOD("scif1", 206, R8A7796_CLK_S3D4),
86 DEF_MOD("scif0", 207, R8A7796_CLK_S3D4),
87 DEF_MOD("msiof3", 208, R8A7796_CLK_MSO),
88 DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
89 DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
90 DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
91 DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
92 DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
93 DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
94 DEF_MOD("cmt3", 300, R8A7796_CLK_R),
95 DEF_MOD("cmt2", 301, R8A7796_CLK_R),
96 DEF_MOD("cmt1", 302, R8A7796_CLK_R),
97 DEF_MOD("cmt0", 303, R8A7796_CLK_R),
98 DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
99 DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
100 DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
101 DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
102 DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
103 DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
104 DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
105 DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
106 DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
107 DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
108 DEF_MOD("rwdt", 402, R8A7796_CLK_R),
109 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
110 DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
111 DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
112 DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
113 DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
114 DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
115 DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
116 DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
117 DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
118 DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
119 DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
120 DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
121 DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
122 DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
123 DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
124 DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1),
125 DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1),
126 DEF_MOD("thermal", 522, R8A7796_CLK_CP),
127 DEF_MOD("pwm", 523, R8A7796_CLK_S0D12),
128 DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2),
129 DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2),
130 DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),
131 DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1),
132 DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1),
133 DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1),
134 DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2),
135 DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2),
136 DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2),
137 DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),
138 DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
139 DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
140 DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
141 DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
142 DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
143 DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
144 DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
145 DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
146 DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
147 DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
148 DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
149 DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
150 DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
151 DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
152 DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
153 DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
154 DEF_MOD("vin4", 807, R8A7796_CLK_S0D2),
155 DEF_MOD("vin3", 808, R8A7796_CLK_S0D2),
156 DEF_MOD("vin2", 809, R8A7796_CLK_S0D2),
157 DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
158 DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
159 DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
160 DEF_MOD("imr1", 822, R8A7796_CLK_S0D2),
161 DEF_MOD("imr0", 823, R8A7796_CLK_S0D2),
162 DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
163 DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
164 DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
165 DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4),
166 DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4),
167 DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4),
168 DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4),
169 DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4),
170 DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
171 DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
172 DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
173 DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
174 DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
175 DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
176 DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
177 DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
178 DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
179 DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
180 DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2),
181 DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2),
182 DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
183 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
184 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
185 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
186 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
187 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
188 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
189 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
190 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
191 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
192 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
193 DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
194 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
195 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
196 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
197 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
198 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
199 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
200 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
201 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
202 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
203 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
204 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
205 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
206 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
207 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
208};
209
210static const struct mstp_stop_table r8a7796_mstp_table[] = {
211 { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
212 { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
213 { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
214 { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
215 { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
216 { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
217};
218
219static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
220 .core_clk = r8a7796_core_clks,
221 .core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
222 .mod_clk = r8a7796_mod_clks,
223 .mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
224 .mstp_table = r8a7796_mstp_table,
225 .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
226 .reset_node = "renesas,r8a7796-rst",
227 .extalr_node = "extalr",
228};
229
230static const struct udevice_id r8a7796_clk_ids[] = {
231 {
232 .compatible = "renesas,r8a7796-cpg-mssr",
233 .data = (ulong)&r8a7796_cpg_mssr_info,
234 },
235 { }
236};
237
238U_BOOT_DRIVER(clk_r8a7796) = {
239 .name = "clk_r8a7796",
240 .id = UCLASS_CLK,
241 .of_match = r8a7796_clk_ids,
242 .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
243 .ops = &gen3_clk_ops,
244 .probe = gen3_clk_probe,
245 .remove = gen3_clk_remove,
246};