Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <common.h> |
| 24 | #include <asm/mmu.h> |
| 25 | #include <asm/immap_85xx.h> |
Poonam Aggrwal | 82b7725 | 2009-09-19 17:50:17 +0530 | [diff] [blame] | 26 | #include <asm/processor.h> |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 27 | #include <asm/fsl_ddr_sdram.h> |
| 28 | #include <asm/io.h> |
| 29 | #include <asm/fsl_law.h> |
| 30 | |
Poonam Aggrwal | 82b7725 | 2009-09-19 17:50:17 +0530 | [diff] [blame] | 31 | DECLARE_GLOBAL_DATA_PTR; |
| 32 | |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 33 | extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, |
| 34 | unsigned int ctrl_num); |
| 35 | |
| 36 | #define DATARATE_400MHZ 400000000 |
| 37 | #define DATARATE_533MHZ 533333333 |
| 38 | #define DATARATE_667MHZ 666666666 |
| 39 | #define DATARATE_800MHZ 800000000 |
| 40 | |
| 41 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
| 42 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
| 43 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 |
| 44 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 |
| 45 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 |
| 46 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 |
| 47 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000 |
| 48 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000 |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 49 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 |
| 50 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 |
| 51 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 |
| 52 | #define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/ |
| 53 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 |
| 54 | #define CONFIG_SYS_DDR_TIMING_4 0x00000000 |
| 55 | #define CONFIG_SYS_DDR_TIMING_5 0x00000000 |
| 56 | |
| 57 | #define CONFIG_SYS_DDR_TIMING_3_400 0x00010000 |
| 58 | #define CONFIG_SYS_DDR_TIMING_0_400 0x00260802 |
| 59 | #define CONFIG_SYS_DDR_TIMING_1_400 0x39355322 |
| 60 | #define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca |
| 61 | #define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000 |
| 62 | #define CONFIG_SYS_DDR_MODE_1_400 0x00480432 |
| 63 | #define CONFIG_SYS_DDR_MODE_2_400 0x00000000 |
| 64 | #define CONFIG_SYS_DDR_INTERVAL_400 0x06180100 |
| 65 | |
| 66 | #define CONFIG_SYS_DDR_TIMING_3_533 0x00020000 |
| 67 | #define CONFIG_SYS_DDR_TIMING_0_533 0x00260802 |
| 68 | #define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432 |
| 69 | #define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce |
| 70 | #define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000 |
| 71 | #define CONFIG_SYS_DDR_MODE_1_533 0x00040642 |
| 72 | #define CONFIG_SYS_DDR_MODE_2_533 0x00000000 |
| 73 | #define CONFIG_SYS_DDR_INTERVAL_533 0x08200100 |
| 74 | |
| 75 | #define CONFIG_SYS_DDR_TIMING_3_667 0x00030000 |
| 76 | #define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 |
| 77 | #define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 |
| 78 | #define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 |
| 79 | #define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000 |
| 80 | #define CONFIG_SYS_DDR_MODE_1_667 0x00040852 |
| 81 | #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 |
| 82 | #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 |
| 83 | |
| 84 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00040000 |
| 85 | #define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 |
| 86 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 |
| 87 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 |
| 88 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000 |
| 89 | #define CONFIG_SYS_DDR_MODE_1_800 0x00440862 |
| 90 | #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 |
| 91 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 |
| 92 | |
| 93 | fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { |
| 94 | .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
| 95 | .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
| 96 | .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
| 97 | .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400, |
| 98 | .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400, |
| 99 | .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400, |
| 100 | .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400, |
| 101 | .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
| 102 | .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
| 103 | .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400, |
| 104 | .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400, |
| 105 | .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
| 106 | .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400, |
| 107 | .ddr_data_init = CONFIG_MEM_INIT_VALUE, |
| 108 | .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400, |
| 109 | .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
| 110 | .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
| 111 | .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
| 112 | .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
| 113 | .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
| 114 | .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 115 | .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
| 116 | .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
| 117 | .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
| 118 | }; |
| 119 | |
| 120 | fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = { |
| 121 | .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
| 122 | .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
| 123 | .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
| 124 | .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533, |
| 125 | .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533, |
| 126 | .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533, |
| 127 | .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533, |
| 128 | .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
| 129 | .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
| 130 | .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533, |
| 131 | .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533, |
| 132 | .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
| 133 | .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533, |
| 134 | .ddr_data_init = CONFIG_MEM_INIT_VALUE, |
| 135 | .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533, |
| 136 | .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
| 137 | .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
| 138 | .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
| 139 | .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
| 140 | .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
| 141 | .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 142 | .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
| 143 | .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
| 144 | .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
| 145 | }; |
| 146 | |
| 147 | fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { |
| 148 | .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
| 149 | .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
| 150 | .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
| 151 | .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667, |
| 152 | .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667, |
| 153 | .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667, |
| 154 | .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667, |
| 155 | .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
| 156 | .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
| 157 | .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667, |
| 158 | .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667, |
| 159 | .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
| 160 | .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667, |
| 161 | .ddr_data_init = CONFIG_MEM_INIT_VALUE, |
| 162 | .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667, |
| 163 | .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
| 164 | .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
| 165 | .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
| 166 | .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
| 167 | .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
| 168 | .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 169 | .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
| 170 | .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
| 171 | .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
| 172 | }; |
| 173 | |
| 174 | fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { |
| 175 | .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
| 176 | .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
| 177 | .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
| 178 | .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, |
| 179 | .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, |
| 180 | .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, |
| 181 | .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, |
| 182 | .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
| 183 | .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
| 184 | .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, |
| 185 | .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, |
| 186 | .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
| 187 | .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, |
| 188 | .ddr_data_init = CONFIG_MEM_INIT_VALUE, |
| 189 | .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, |
| 190 | .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
| 191 | .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
| 192 | .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
| 193 | .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
| 194 | .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
| 195 | .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 196 | .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
| 197 | .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
| 198 | .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
| 199 | }; |
| 200 | |
| 201 | /* |
| 202 | * Fixed sdram init -- doesn't use serial presence detect. |
| 203 | */ |
| 204 | |
| 205 | phys_size_t fixed_sdram (void) |
| 206 | { |
| 207 | sys_info_t sysinfo; |
| 208 | char buf[32]; |
Poonam Aggrwal | 82b7725 | 2009-09-19 17:50:17 +0530 | [diff] [blame] | 209 | fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL; |
| 210 | size_t ddr_size; |
| 211 | struct cpu_type *cpu; |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 212 | |
| 213 | get_sys_info(&sysinfo); |
| 214 | printf("Configuring DDR for %s MT/s data rate\n", |
| 215 | strmhz(buf, sysinfo.freqDDRBus)); |
| 216 | |
| 217 | if(sysinfo.freqDDRBus <= DATARATE_400MHZ) |
Poonam Aggrwal | 82b7725 | 2009-09-19 17:50:17 +0530 | [diff] [blame] | 218 | ddr_cfg_regs = &ddr_cfg_regs_400; |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 219 | else if(sysinfo.freqDDRBus <= DATARATE_533MHZ) |
Poonam Aggrwal | 82b7725 | 2009-09-19 17:50:17 +0530 | [diff] [blame] | 220 | ddr_cfg_regs = &ddr_cfg_regs_533; |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 221 | else if(sysinfo.freqDDRBus <= DATARATE_667MHZ) |
Poonam Aggrwal | 82b7725 | 2009-09-19 17:50:17 +0530 | [diff] [blame] | 222 | ddr_cfg_regs = &ddr_cfg_regs_667; |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 223 | else if(sysinfo.freqDDRBus <= DATARATE_800MHZ) |
Poonam Aggrwal | 82b7725 | 2009-09-19 17:50:17 +0530 | [diff] [blame] | 224 | ddr_cfg_regs = &ddr_cfg_regs_800; |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 225 | else |
| 226 | panic("Unsupported DDR data rate %s MT/s data rate\n", |
| 227 | strmhz(buf, sysinfo.freqDDRBus)); |
| 228 | |
Poonam Aggrwal | 82b7725 | 2009-09-19 17:50:17 +0530 | [diff] [blame] | 229 | cpu = gd->cpu; |
| 230 | /* P1020 and it's derivatives support max 32bit DDR width */ |
| 231 | if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || |
| 232 | cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { |
| 233 | ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE; |
| 234 | ddr_cfg_regs->cs[0].bnds = 0x0000001F; |
| 235 | ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); |
| 236 | } |
| 237 | else |
| 238 | ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
| 239 | |
| 240 | fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0); |
| 241 | |
| 242 | return ddr_size; |
Poonam Aggrwal | 728ece3 | 2009-08-05 13:29:24 +0530 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | phys_size_t initdram(int board_type) |
| 246 | { |
| 247 | phys_size_t dram_size = 0; |
| 248 | |
| 249 | dram_size = fixed_sdram(); |
| 250 | set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1); |
| 251 | |
| 252 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
| 253 | dram_size *= 0x100000; |
| 254 | |
| 255 | puts("DDR: "); |
| 256 | return dram_size; |
| 257 | } |