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gerrit.cesnet.cz / github / trini / u-boot / f71d9d91a2cd9c30b2b6369f15c1a46c11537c2b / . / cpu / mcf52x2 / start.S
blob: f6c58c2fef1ed58cec3de289779d4554cc7ce6a7 [file] [log] [blame]
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include "version.h"
26
27#ifndef CONFIG_IDENT_STRING
28#define CONFIG_IDENT_STRING ""
29#endif
30
31
32#define _START _start
33#define _FAULT _fault
34
35
36#define SAVE_ALL \
37 move.w #0x2700,%sr; /* disable intrs */ \
38 subl #60,%sp; /* space for 15 regs */ \
39 moveml %d0-%d7/%a0-%a6,%sp@; \
40
41#define RESTORE_ALL \
42 moveml %sp@,%d0-%d7/%a0-%a6; \
43 addl #60,%sp; /* space for 15 regs */ \
44 rte
45
46/* If we come from a pre-loader we don't need an initial exception
47 * table.
48 */
49#if !defined(CONFIG_MONITOR_IS_IN_RAM)
50
51.text
52/*
53 * Vector table. This is used for initial platform startup.
54 * These vectors are to catch any un-intended traps.
55 */
56_vectors:
57
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]58.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
59#if defined(CONFIG_R5200)
60.long 0x400
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]61#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]62.long _start - TEXT_BASE
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]63#else
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]64.long _START
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]65#endif
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]66
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102
103#endif
104
105 .text
106
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]107
108#if defined(CFG_INT_FLASH_BASE) && \
109 (defined(CONFIG_M5282) || defined(CONFIG_M5281))
110 #if (TEXT_BASE == CFG_INT_FLASH_BASE)
111 .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
112 .long 0xFFFFFFFF /* all sectors protected */
113 .long 0x00000000 /* supervisor/User restriction */
114 .long 0x00000000 /* programm/data space restriction */
115 .long 0x00000000 /* Flash security */
116 #endif
117#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]118 .globl _start
119_start:
120 nop
121 nop
122 move.w #0x2700,%sr
123
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]124#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]125 move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
126 move.c %d0, %MBAR
127
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]128 /*** The 5249 has MBAR2 as well ***/
129#ifdef CFG_MBAR2
130 move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
131 movec %d0, #0xc0e /* Set MBAR2 */
132#endif
133
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]134 move.l #(CFG_INIT_RAM_ADDR + 1), %d0
135 movec %d0, %RAMBAR0
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]136#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]137
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]138#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]139 /* Initialize IPSBAR */
140 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
141 move.l %d0, 0x40000000
142
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]143 /* Initialize RAMBAR1: locate SRAM and validate it */
144 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
145 movec %d0, %RAMBAR1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]146
Bartlomiej Siekadaa6e412006-12-20 00:27:32 +0100[diff] [blame]147#if defined(CONFIG_M5282)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]148#if (TEXT_BASE == CFG_INT_FLASH_BASE)
149 /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
150
151 move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
152 move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
153 move.l #(CFG_INIT_RAM_ADDR), %a2
154_copy_flash:
155 move.l (%a0)+, (%a2)+
156 cmp.l %a0, %a1
157 bgt.s _copy_flash
158 jmp CFG_INIT_RAM_ADDR
159
160_flashbar_setup:
161 /* Initialize FLASHBAR: locate internal Flash and validate it */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]162 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
TsiChung Liew43d60642008-03-13 14:26:32 -0500[diff] [blame]163 movec %d0, %FLASHBAR
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]164 jmp _after_flashbar_copy.L /* Force jump to absolute address */
165_flashbar_setup_end:
166 nop
167_after_flashbar_copy:
168#else
169 /* Setup code to initialize FLASHBAR, if start from external Memory */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]170 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
TsiChung Liew43d60642008-03-13 14:26:32 -0500[diff] [blame]171 movec %d0, %RAMBAR1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]172#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
173
174#endif
Wolfgang Denk6741ae92006-09-04 01:03:57 +0200[diff] [blame]175#endif
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]176 /* if we come from a pre-loader we have no exception table and
177 * therefore no VBR to set
178 */
179#if !defined(CONFIG_MONITOR_IS_IN_RAM)
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]180#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
181 move.l #CFG_INT_FLASH_BASE, %d0
182#else
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]183 move.l #CFG_FLASH_BASE, %d0
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]184#endif
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]185 movec %d0, %VBR
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]186#endif
187
188#ifdef CONFIG_R5200
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]189 move.l #(_flash_setup-CFG_FLASH_BASE), %a0
190 move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
191 move.l #(CFG_INIT_RAM_ADDR), %a2
192_copy_flash:
193 move.l (%a0)+, (%a2)+
194 cmp.l %a0, %a1
195 bgt.s _copy_flash
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]196 jmp CFG_INIT_RAM_ADDR
197_after_flash_copy:
198#endif
199
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame^]200#ifdef CONFIG_M5275
201 /* Initialize IPSBAR */
202 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
203 move.l %d0, 0x40000000
204/* movec %d0, %MBAR */
205
206 /* Initialize RAMBAR: locate SRAM and validate it */
207 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
208 movec %d0, %RAMBAR1
209#endif
210
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]211#if 0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]212 /* invalidate and disable cache */
213 move.l #0x01000000, %d0 /* Invalidate cache cmd */
214 movec %d0, %CACR /* Invalidate cache */
215 move.l #0, %d0
216 movec %d0, %ACR0
217 movec %d0, %ACR1
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]218#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]219
220 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
221 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
222 clr.l %sp@-
223
224 move.l #__got_start, %a5 /* put relocation table address to a5 */
225
226 bsr cpu_init_f /* run low-level CPU init code (from flash) */
227 bsr board_init_f /* run low-level board init code (from flash) */
228
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]229 /* board_init_f() does not return */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]230
231/*------------------------------------------------------------------------------*/
232
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]233#ifdef CONFIG_R5200
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]234_flash_setup:
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]235 /* CSAR0 */
236 move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]237 move.w %d0, 0x40000080
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]238
239 /* CSCR0 */
240 move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]241 move.w %d0, 0x4000008A
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]242
243 /* CSMR0 */
244 move.l #0x001f0001, %d0 /* 2 MB, valid */
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]245 move.l %d0, 0x40000084
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]246
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]247 jmp _after_flash_copy.L
248_flash_setup_end:
249#endif
250
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]251/*
252 * void relocate_code (addr_sp, gd, addr_moni)
253 *
254 * This "function" does not return, instead it continues in RAM
255 * after relocating the monitor code.
256 *
257 * r3 = dest
258 * r4 = src
259 * r5 = length in bytes
260 * r6 = cachelinesize
261 */
262 .globl relocate_code
263relocate_code:
264 link.w %a6,#0
265 move.l 8(%a6), %sp /* set new stack pointer */
266
267 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
268 move.l 16(%a6), %a0 /* Save copy of Destination Address */
269
270 move.l #CFG_MONITOR_BASE, %a1
271 move.l #__init_end, %a2
272 move.l %a0, %a3
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]273 /* copy the code to RAM */
2741:
275 move.l (%a1)+, (%a3)+
276 cmp.l %a1,%a2
277 bgt.s 1b
278
279/*
280 * We are done. Do not return, instead branch to second part of board
281 * initialization, now running from RAM.
282 */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]283 move.l %a0, %a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]284 add.l #(in_ram - CFG_MONITOR_BASE), %a1
285 jmp (%a1)
286
287in_ram:
288
289clear_bss:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]290 /*
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]291 * Now clear BSS segment
292 */
293 move.l %a0, %a1
294 add.l #(_sbss - CFG_MONITOR_BASE),%a1
295 move.l %a0, %d1
296 add.l #(_ebss - CFG_MONITOR_BASE),%d1
2976:
298 clr.l (%a1)+
299 cmp.l %a1,%d1
300 bgt.s 6b
301
302 /*
303 * fix got table in RAM
304 */
305 move.l %a0, %a1
306 add.l #(__got_start - CFG_MONITOR_BASE),%a1
307 move.l %a1,%a5 /* * fix got pointer register a5 */
308
309 move.l %a0, %a2
310 add.l #(__got_end - CFG_MONITOR_BASE),%a2
311
3127:
313 move.l (%a1),%d1
314 sub.l #_start,%d1
315 add.l %a0,%d1
316 move.l %d1,(%a1)+
317 cmp.l %a2, %a1
318 bne 7b
319
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]320#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
321 /* patch the 3 accesspoints to 3 ichache_state */
322 /* quick and dirty */
323
324 move.l %a0,%d1
325 add.l #(icache_state - CFG_MONITOR_BASE),%d1
326 move.l %a0,%a1
327 add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
328 move.l %d1,(%a1)
329 move.l %a0,%a1
330 add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
331 move.l %d1,(%a1)
332 move.l %a0,%a1
333 add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
334 move.l %d1,(%a1)
335#endif
336
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]337 /* calculate relative jump to board_init_r in ram */
338 move.l %a0, %a1
339 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
340
341 /* set parameters for board_init_r */
342 move.l %a0,-(%sp) /* dest_addr */
343 move.l %d0,-(%sp) /* gd */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]344#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
345 defined(CFG_HALT_BEFOR_RAM_JUMP)
346 halt
347#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]348 jsr (%a1)
349
350/*------------------------------------------------------------------------------*/
351/* exception code */
352 .globl _fault
353_fault:
354 jmp _fault
355
356 .globl _exc_handler
357_exc_handler:
358 SAVE_ALL
359 movel %sp,%sp@-
360 bsr exc_handler
361 addql #4,%sp
362 RESTORE_ALL
363
364 .globl _int_handler
365_int_handler:
366 SAVE_ALL
367 movel %sp,%sp@-
368 bsr int_handler
369 addql #4,%sp
370 RESTORE_ALL
371
372/*------------------------------------------------------------------------------*/
373/* cache functions */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]374#ifdef CONFIG_M5271
375 .globl icache_enable
376icache_enable:
377 move.l #0x01000000, %d0 /* Invalidate cache cmd */
378 movec %d0, %CACR /* Invalidate cache */
379 move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
380 movec %d0, %ACR0 /* Enable cache */
381
382 move.l #0x80000200, %d0 /* Setup cache mask */
383 movec %d0, %CACR /* Enable cache */
384 nop
385
386 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
387 moveq #1, %d0
388 move.l %d0, (%a1)
389 rts
390#endif
391
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]392#ifdef CONFIG_M5272
393 .globl icache_enable
394icache_enable:
395 move.l #0x01000000, %d0 /* Invalidate cache cmd */
396 movec %d0, %CACR /* Invalidate cache */
397 move.l #0x0000c000, %d0 /* Setup cache mask */
398 movec %d0, %ACR0 /* Enable cache */
399 move.l #0xff00c000, %d0 /* Setup cache mask */
400 movec %d0, %ACR1 /* Enable cache */
401 move.l #0x80000100, %d0 /* Setup cache mask */
402 movec %d0, %CACR /* Enable cache */
403 moveq #1, %d0
404 move.l %d0, icache_state
405 rts
406#endif
407
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame^]408#if defined(CONFIG_M5275)
409/*
410 * Instruction cache only
411 */
412 .globl icache_enable
413icache_enable:
414 move.l #0x01400000, %d0 /* Invalidate cache cmd */
415 movec %d0, %CACR /* Invalidate cache */
416 move.l #0x0000c000, %d0 /* Setup SDRAM caching */
417 movec %d0, %ACR0 /* Enable cache */
418 move.l #0x00000000, %d0 /* No other caching */
419 movec %d0, %ACR1 /* Enable cache */
420 move.l #0x80400100, %d0 /* Setup cache mask */
421 movec %d0, %CACR /* Enable cache */
422 moveq #1, %d0
423 move.l %d0, icache_state
424 rts
425#endif
426
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]427#ifdef CONFIG_M5282
428 .globl icache_enable
429icache_enable:
430 move.l #0x01000000, %d0 /* Invalidate cache cmd */
431 movec %d0, %CACR /* Invalidate cache */
432 move.l #0x0000c000, %d0 /* Setup cache mask */
433 movec %d0, %ACR0 /* Enable cache */
434 move.l #0xff00c000, %d0 /* Setup cache mask */
435 movec %d0, %ACR1 /* Enable cache */
436 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
437 movec %d0, %CACR /* Enable cache */
438 moveq #1, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]439icache_state_access_1:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]440 move.l %d0, icache_state
441 rts
442#endif
443
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]444#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]445 .globl icache_enable
446icache_enable:
447 /*
448 * Note: The 5249 Documentation doesn't give a bit position for CINV!
449 * From the 5272 and the 5307 documentation, I have deduced that it is
450 * probably CACR[24]. Should someone say something to Motorola?
451 * ~Jeremy
452 */
453 move.l #0x01000000, %d0 /* Invalidate whole cache */
454 move.c %d0,%CACR
455 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
456 move.c %d0, %ACR0
457 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
458 move.c %d0, %ACR1
459 move.l #0x90000200, %d0 /* Set cache enable cmd */
460 move.c %d0,%CACR
461 moveq #1, %d0
462 move.l %d0, icache_state
463 rts
464#endif
465
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]466 .globl icache_disable
467icache_disable:
468 move.l #0x00000100, %d0 /* Setup cache mask */
469 movec %d0, %CACR /* Enable cache */
470 clr.l %d0 /* Setup cache mask */
471 movec %d0, %ACR0 /* Enable cache */
472 movec %d0, %ACR1 /* Enable cache */
473 moveq #0, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]474icache_state_access_2:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]475 move.l %d0, icache_state
476 rts
477
478 .globl icache_status
479icache_status:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]480icache_state_access_3:
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]481 move.l #(icache_state), %a0
482 move.l (%a0), %d0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]483 rts
484
485 .data
486icache_state:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]487 .long 0 /* cache is diabled on inirialization */
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]488
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]489 .globl dcache_enable
490dcache_enable:
491 /* dummy function */
492 rts
493
494 .globl dcache_disable
495dcache_disable:
496 /* dummy function */
497 rts
498
499 .globl dcache_status
500dcache_status:
501 /* dummy function */
502 rts
503
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]504/*------------------------------------------------------------------------------*/
505
506 .globl version_string
507version_string:
508 .ascii U_BOOT_VERSION
509 .ascii " (", __DATE__, " - ", __TIME__, ")"
510 .ascii CONFIG_IDENT_STRING, "\0"