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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * (C) Copyright 2003
3 * Josef Baumgartner <josef.baumgartner@telex.de>
4 *
Heiko Schocher9acb6262006-04-20 08:42:42 +02005 * MCF5282 additionals
6 * (C) Copyright 2005
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
8 *
Matthew Fettkef71d9d92008-02-04 15:38:20 -06009 * MCF5275 additions
10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
11 *
wdenkbf9e3b32004-02-12 00:47:09 +000012 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <common.h>
32#include <watchdog.h>
33#include <command.h>
TsiChungLiew83ec20b2007-08-15 19:21:21 -050034#include <asm/immap.h>
wdenkbf9e3b32004-02-12 00:47:09 +000035
Zachary P. Landaueacbd312006-01-26 17:35:56 -050036#ifdef CONFIG_M5271
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010037/*
38 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
39 * determine which one we are running on, based on the Chip Identification
40 * Register (CIR).
41 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -050042int checkcpu(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -050043{
Marian Balakowiczb75ef852006-05-09 11:45:31 +020044 char buf[32];
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010045 unsigned short cir; /* Chip Identification Register */
46 unsigned short pin; /* Part identification number */
47 unsigned char prn; /* Part revision number */
48 char *cpu_model;
Marian Balakowiczb75ef852006-05-09 11:45:31 +020049
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010050 cir = mbar_readShort(MCF_CCM_CIR);
51 pin = cir >> MCF_CCM_CIR_PIN_LEN;
52 prn = cir & MCF_CCM_CIR_PRN_MASK;
53
54 switch (pin) {
55 case MCF_CCM_CIR_PIN_MCF5270:
56 cpu_model = "5270";
57 break;
58 case MCF_CCM_CIR_PIN_MCF5271:
59 cpu_model = "5271";
60 break;
61 default:
62 cpu_model = NULL;
63 break;
64 }
65
66 if (cpu_model)
67 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
TsiChungLiew83ec20b2007-08-15 19:21:21 -050068 cpu_model, prn, strmhz(buf, CFG_CLK));
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010069 else
70 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
TsiChungLiew83ec20b2007-08-15 19:21:21 -050071 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
72 pin, prn, strmhz(buf, CFG_CLK));
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010073
Zachary P. Landaueacbd312006-01-26 17:35:56 -050074 return 0;
75}
76
TsiChungLiew83ec20b2007-08-15 19:21:21 -050077int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
78{
Zachary P. Landaueacbd312006-01-26 17:35:56 -050079 mbar_writeByte(MCF_RCM_RCR,
TsiChungLiew83ec20b2007-08-15 19:21:21 -050080 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
Zachary P. Landaueacbd312006-01-26 17:35:56 -050081 return 0;
82};
83
84#if defined(CONFIG_WATCHDOG)
TsiChungLiew83ec20b2007-08-15 19:21:21 -050085void watchdog_reset(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -050086{
87 mbar_writeShort(MCF_WTM_WSR, 0x5555);
88 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
89}
90
TsiChungLiew83ec20b2007-08-15 19:21:21 -050091int watchdog_disable(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -050092{
93 mbar_writeShort(MCF_WTM_WCR, 0);
94 return (0);
95}
96
TsiChungLiew83ec20b2007-08-15 19:21:21 -050097int watchdog_init(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -050098{
Zachary P. Landaueacbd312006-01-26 17:35:56 -050099 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
100 return (0);
101}
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500102#endif /* #ifdef CONFIG_WATCHDOG */
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500103
104#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000105
106#ifdef CONFIG_M5272
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500107int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
108{
109 volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdenkbf9e3b32004-02-12 00:47:09 +0000110
111 wdp->wdog_wrrr = 0;
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500112 udelay(1000);
wdenkbf9e3b32004-02-12 00:47:09 +0000113
114 /* enable watchdog, set timeout to 0 and wait */
115 wdp->wdog_wrrr = 1;
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500116 while (1) ;
wdenkbf9e3b32004-02-12 00:47:09 +0000117
118 /* we don't return! */
119 return 0;
120};
121
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500122int checkcpu(void)
123{
124 volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
wdenkbf9e3b32004-02-12 00:47:09 +0000125 uchar msk;
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500126 char *suf;
wdenkbf9e3b32004-02-12 00:47:09 +0000127
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500128 puts("CPU: ");
129 msk = (sysctrl->sc_dir > 28) & 0xf;
wdenkbf9e3b32004-02-12 00:47:09 +0000130 switch (msk) {
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500131 case 0x2:
132 suf = "1K75N";
133 break;
134 case 0x4:
135 suf = "3K75N";
136 break;
137 default:
138 suf = NULL;
139 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
140 break;
141 }
wdenkbf9e3b32004-02-12 00:47:09 +0000142
143 if (suf)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500144 printf("Freescale MCF5272 %s\n", suf);
wdenkbf9e3b32004-02-12 00:47:09 +0000145 return 0;
146};
147
wdenkbf9e3b32004-02-12 00:47:09 +0000148#if defined(CONFIG_WATCHDOG)
149/* Called by macro WATCHDOG_RESET */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500150void watchdog_reset(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000151{
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500152 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
153 wdt->wdog_wcr = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000154}
155
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500156int watchdog_disable(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000157{
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500158 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
wdenkbf9e3b32004-02-12 00:47:09 +0000159
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500160 wdt->wdog_wcr = 0; /* reset watchdog counter */
161 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
162 wdt->wdog_wrrr = 0; /* disable watchdog timer */
wdenkbf9e3b32004-02-12 00:47:09 +0000163
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500164 puts("WATCHDOG:disabled\n");
wdenkbf9e3b32004-02-12 00:47:09 +0000165 return (0);
166}
167
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500168int watchdog_init(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000169{
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500170 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
wdenkbf9e3b32004-02-12 00:47:09 +0000171
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500172 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
wdenkbf9e3b32004-02-12 00:47:09 +0000173
174 /* set timeout and enable watchdog */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500175 wdt->wdog_wrrr =
176 ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
177 wdt->wdog_wcr = 0; /* reset watchdog counter */
wdenkbf9e3b32004-02-12 00:47:09 +0000178
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500179 puts("WATCHDOG:enabled\n");
wdenkbf9e3b32004-02-12 00:47:09 +0000180 return (0);
181}
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500182#endif /* #ifdef CONFIG_WATCHDOG */
wdenkbf9e3b32004-02-12 00:47:09 +0000183
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500184#endif /* #ifdef CONFIG_M5272 */
wdenkbf9e3b32004-02-12 00:47:09 +0000185
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600186#ifdef CONFIG_M5275
187int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
188{
189 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
190
191 udelay(1000);
192
193 rcm->rcr = RCM_RCR_SOFTRST;
194
195 /* we don't return! */
196 return 0;
197};
198
199int checkcpu(void)
200{
201 char buf[32];
202
203 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
204 strmhz(buf, CFG_CLK));
205 return 0;
206};
207
208
209#if defined(CONFIG_WATCHDOG)
210/* Called by macro WATCHDOG_RESET */
211void watchdog_reset(void)
212{
213 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
214 wdt->wsr = 0x5555;
215 wdt->wsr = 0xAAAA;
216}
217
218int watchdog_disable(void)
219{
220 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
221
222 wdt->wsr = 0x5555; /* reset watchdog counter */
223 wdt->wsr = 0xAAAA;
224 wdt->wcr = 0; /* disable watchdog timer */
225
226 puts("WATCHDOG:disabled\n");
227 return (0);
228}
229
230int watchdog_init(void)
231{
232 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
233
234 wdt->wcr = 0; /* disable watchdog */
235
236 /* set timeout and enable watchdog */
237 wdt->wmr =
238 ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
239 wdt->wsr = 0x5555; /* reset watchdog counter */
240 wdt->wsr = 0xAAAA;
241
242 puts("WATCHDOG:enabled\n");
243 return (0);
244}
245#endif /* #ifdef CONFIG_WATCHDOG */
246
247#endif /* #ifdef CONFIG_M5275 */
248
wdenkbf9e3b32004-02-12 00:47:09 +0000249#ifdef CONFIG_M5282
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500250int checkcpu(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000251{
Wolfgang Denk4176c792006-06-10 19:27:47 +0200252 unsigned char resetsource = MCFRESET_RSR;
Heiko Schocher9acb6262006-04-20 08:42:42 +0200253
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500254 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
255 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
256 printf("Reset:%s%s%s%s%s%s%s\n",
257 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
258 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
259 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
260 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
261 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
262 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
263 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
wdenkbf9e3b32004-02-12 00:47:09 +0000264 return 0;
265}
266
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500267int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
Heiko Schocher9acb6262006-04-20 08:42:42 +0200268{
269 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
wdenkbf9e3b32004-02-12 00:47:09 +0000270 return 0;
271};
272#endif
stroese8c725b92004-12-16 18:09:49 +0000273
TsiChungLiewa1436a82007-08-16 13:20:50 -0500274#ifdef CONFIG_M5249
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500275int checkcpu(void)
stroese8c725b92004-12-16 18:09:49 +0000276{
277 char buf[32];
278
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500279 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
280 strmhz(buf, CFG_CLK));
stroese8c725b92004-12-16 18:09:49 +0000281 return 0;
282}
283
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500284int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
285{
stroese8c725b92004-12-16 18:09:49 +0000286 /* enable watchdog, set timeout to 0 and wait */
287 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500288 while (1) ;
stroese8c725b92004-12-16 18:09:49 +0000289
290 /* we don't return! */
291 return 0;
292};
293#endif
TsiChungLiewa1436a82007-08-16 13:20:50 -0500294
295#ifdef CONFIG_M5253
296int checkcpu(void)
297{
298 char buf[32];
299
300 unsigned char resetsource = mbar_readLong(SIM_RSR);
301 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
302 strmhz(buf, CFG_CLK));
303
304 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
305 printf("Reset:%s%s\n",
306 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
307 : "",
308 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
309 "");
310 }
311 return 0;
312}
313
314int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
315{
316 /* enable watchdog, set timeout to 0 and wait */
317 mbar_writeByte(SIM_SYPCR, 0xc0);
318 while (1) ;
319
320 /* we don't return! */
321 return 0;
322};
323#endif