Hoan Hoang | 0f52b56 | 2009-01-18 22:44:17 -0500 | [diff] [blame] | 1 | /* |
| 2 | * U-boot - Configuration file for IBF-DSP561 board |
| 3 | */ |
| 4 | |
| 5 | #ifndef __CONFIG_IBF_DSP561__H__ |
| 6 | #define __CONFIG_IBF_DSP561__H__ |
| 7 | |
Mike Frysinger | f348ab8 | 2009-04-24 17:22:40 -0400 | [diff] [blame] | 8 | #include <asm/config-pre.h> |
Hoan Hoang | 0f52b56 | 2009-01-18 22:44:17 -0500 | [diff] [blame] | 9 | |
| 10 | |
| 11 | /* |
| 12 | * Processor Settings |
| 13 | */ |
| 14 | #define CONFIG_BFIN_CPU bf561-0.5 |
| 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
| 16 | |
| 17 | |
| 18 | /* |
| 19 | * Clock Settings |
| 20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
| 21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
| 22 | */ |
| 23 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
| 24 | #define CONFIG_CLKIN_HZ 25000000 |
| 25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
| 26 | /* 1 = CLKIN / 2 */ |
| 27 | #define CONFIG_CLKIN_HALF 0 |
| 28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
| 29 | /* 1 = bypass PLL */ |
| 30 | #define CONFIG_PLL_BYPASS 0 |
| 31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
| 32 | /* Values can range from 0-63 (where 0 means 64) */ |
| 33 | #define CONFIG_VCO_MULT 24 |
| 34 | /* CCLK_DIV controls the core clock divider */ |
| 35 | /* Values can be 1, 2, 4, or 8 ONLY */ |
| 36 | #define CONFIG_CCLK_DIV 1 |
| 37 | /* SCLK_DIV controls the system clock divider */ |
| 38 | /* Values can range from 1-15 */ |
| 39 | #define CONFIG_SCLK_DIV 5 |
| 40 | |
| 41 | |
| 42 | /* |
| 43 | * Memory Settings |
| 44 | */ |
| 45 | #define CONFIG_MEM_ADD_WDTH 9 |
| 46 | #define CONFIG_MEM_SIZE 64 |
| 47 | |
| 48 | #define CONFIG_EBIU_SDRRC_VAL 0x377 |
| 49 | #define CONFIG_EBIU_SDGCTL_VAL 0x91998d |
| 50 | #define CONFIG_EBIU_SDBCTL_VAL 0x15 |
| 51 | |
| 52 | #define CONFIG_EBIU_AMGCTL_VAL 0x3F |
| 53 | #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 |
| 54 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 |
| 55 | |
| 56 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
| 57 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) |
| 58 | |
| 59 | |
| 60 | /* |
| 61 | * Flash Settings |
| 62 | */ |
| 63 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
| 64 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 65 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET |
| 66 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
| 67 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 68 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ |
| 69 | /* The BF561-EZKIT uses a top boot flash */ |
| 70 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 71 | #define CONFIG_ENV_ADDR 0x20004000 |
| 72 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) |
| 73 | #define CONFIG_ENV_SIZE 0x2000 |
| 74 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ |
| 75 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
| 76 | #define ENV_IS_EMBEDDED |
| 77 | #else |
| 78 | #define ENV_IS_EMBEDDED_CUSTOM |
| 79 | #endif |
Mike Frysinger | 9ff67e5 | 2009-06-14 06:29:07 -0400 | [diff] [blame] | 80 | #ifdef ENV_IS_EMBEDDED |
| 81 | /* WARNING - the following is hand-optimized to fit within |
| 82 | * the sector before the environment sector. If it throws |
| 83 | * an error during compilation remove an object here to get |
| 84 | * it linked after the configuration sector. |
| 85 | */ |
| 86 | # define LDS_BOARD_TEXT \ |
| 87 | cpu/blackfin/traps.o (.text .text.*); \ |
| 88 | cpu/blackfin/interrupt.o (.text .text.*); \ |
| 89 | cpu/blackfin/serial.o (.text .text.*); \ |
| 90 | common/dlmalloc.o (.text .text.*); \ |
| 91 | lib_generic/crc32.o (.text .text.*); \ |
| 92 | lib_generic/zlib.o (.text .text.*); \ |
| 93 | board/ibf-dsp561/ibf-dsp561.o (.text .text.*); \ |
| 94 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 95 | common/env_embedded.o (.text .text.*); |
| 96 | #endif |
Hoan Hoang | 0f52b56 | 2009-01-18 22:44:17 -0500 | [diff] [blame] | 97 | |
| 98 | |
| 99 | /* |
| 100 | * I2C Settings |
| 101 | */ |
| 102 | #define CONFIG_SOFT_I2C 1 |
| 103 | #define PF_SCL 0x1/*PF0*/ |
| 104 | #define PF_SDA 0x2/*PF1*/ |
| 105 | |
| 106 | #ifdef CONFIG_SOFT_I2C |
| 107 | #define I2C_INIT do { *pFIO0_DIR |= PF_SCL; SSYNC(); } while (0) |
| 108 | #define I2C_ACTIVE do { *pFIO0_DIR |= PF_SDA; *pFIO0_INEN &= ~PF_SDA; SSYNC(); } while (0) |
| 109 | #define I2C_TRISTATE do { *pFIO0_DIR &= ~PF_SDA; *pFIO0_INEN |= PF_SDA; SSYNC(); } while (0) |
| 110 | #define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0) |
| 111 | #define I2C_SDA(bit) \ |
| 112 | do { \ |
| 113 | if (bit) \ |
| 114 | *pFIO0_FLAG_S = PF_SDA; \ |
| 115 | else \ |
| 116 | *pFIO0_FLAG_C = PF_SDA; \ |
| 117 | SSYNC(); \ |
| 118 | } while (0) |
| 119 | #define I2C_SCL(bit) \ |
| 120 | do { \ |
| 121 | if (bit) \ |
| 122 | *pFIO0_FLAG_S = PF_SCL; \ |
| 123 | else \ |
| 124 | *pFIO0_FLAG_C = PF_SCL; \ |
| 125 | SSYNC(); \ |
| 126 | } while (0) |
| 127 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
| 128 | |
| 129 | #define CONFIG_SYS_I2C_SPEED 50000 |
| 130 | #define CONFIG_SYS_I2C_SLAVE 0 |
| 131 | #endif |
| 132 | |
| 133 | |
| 134 | /* |
| 135 | * Misc Settings |
| 136 | */ |
| 137 | #define CONFIG_UART_CONSOLE 0 |
| 138 | |
| 139 | |
| 140 | /* |
| 141 | * Pull in common ADI header for remaining command/environment setup |
| 142 | */ |
| 143 | #include <configs/bfin_adi_common.h> |
| 144 | |
Mike Frysinger | f348ab8 | 2009-04-24 17:22:40 -0400 | [diff] [blame] | 145 | #endif |