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wdenk983fda82004-10-28 00:09:35 +00001/*
2 * (C) Copyright 2004, Freescale, Inc
3 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25/*
26 * Minimal serial functions needed to use one of the PSC ports
27 * as serial console interface.
28 */
29
30#include <common.h>
31#include <mpc8220.h>
32
33#define PSC_BASE MMAP_PSC1
34
35#if defined(CONFIG_PSC_CONSOLE)
wdenk7680c142005-05-16 15:23:22 +000036int serial_init (void)
wdenk983fda82004-10-28 00:09:35 +000037{
38 DECLARE_GLOBAL_DATA_PTR;
39 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
40 u32 counter;
41
42 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
43 psc->cr = 0;
44 psc->ipcr_acr = 0;
45 psc->isr_imr = 0;
46
47 /* write to CSR: RX/TX baud rate from timers */
48 psc->sr_csr = 0xdd000000;
49
wdenk3c2b3d42005-04-05 23:32:21 +000050 psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1;
wdenk983fda82004-10-28 00:09:35 +000051
52 /* Setting up BaudRate */
53 counter = ((gd->bus_clk / gd->baudrate)) >> 5;
54 counter++;
55
56 /* write to CTUR: divide counter upper byte */
57 psc->ctur = ((counter & 0xff00) << 16);
58 /* write to CTLR: divide counter lower byte */
59 psc->ctlr = ((counter & 0x00ff) << 24);
60
61 psc->cr = PSC_CR_RST_RX_CMD;
62 psc->cr = PSC_CR_RST_TX_CMD;
63 psc->cr = PSC_CR_RST_ERR_STS_CMD;
64 psc->cr = PSC_CR_RST_BRK_INT_CMD;
65 psc->cr = PSC_CR_RST_MR_PTR_CMD;
66
67 psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
68 return (0);
69}
70
wdenk7680c142005-05-16 15:23:22 +000071void serial_putc (const char c)
wdenk983fda82004-10-28 00:09:35 +000072{
73 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
74
75 if (c == '\n')
76 serial_putc ('\r');
77
78 /* Wait for last character to go. */
wdenk12b43d52005-04-05 21:57:18 +000079 while (!(psc->sr_csr & PSC_SR_TXRDY));
wdenk983fda82004-10-28 00:09:35 +000080
81 psc->xmitbuf[0] = c;
82}
83
wdenk7680c142005-05-16 15:23:22 +000084void serial_puts (const char *s)
wdenk983fda82004-10-28 00:09:35 +000085{
86 while (*s) {
87 serial_putc (*s++);
88 }
89}
90
wdenk7680c142005-05-16 15:23:22 +000091int serial_getc (void)
wdenk983fda82004-10-28 00:09:35 +000092{
93 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
94
95 /* Wait for a character to arrive. */
96 while (!(psc->sr_csr & PSC_SR_RXRDY));
97 return psc->xmitbuf[2];
98}
99
wdenk7680c142005-05-16 15:23:22 +0000100int serial_tstc (void)
wdenk983fda82004-10-28 00:09:35 +0000101{
102 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
103
104 return (psc->sr_csr & PSC_SR_RXRDY);
105}
106
wdenk7680c142005-05-16 15:23:22 +0000107void serial_setbrg (void)
wdenk983fda82004-10-28 00:09:35 +0000108{
109 DECLARE_GLOBAL_DATA_PTR;
110
111 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
112 u32 counter;
113
114 counter = ((gd->bus_clk / gd->baudrate)) >> 5;
115 counter++;
116
117 /* write to CTUR: divide counter upper byte */
118 psc->ctur = ((counter & 0xff00) << 16);
119 /* write to CTLR: divide counter lower byte */
120 psc->ctlr = ((counter & 0x00ff) << 24);
121
122 psc->cr = PSC_CR_RST_RX_CMD;
123 psc->cr = PSC_CR_RST_TX_CMD;
124
125 psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
126}
127#endif /* CONFIG_PSC_CONSOLE */