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gerrit.cesnet.cz / github / trini / u-boot / f68d0678c878b33fe690e8bcfc9f88b67d870e39 / . / drivers / net / sk98lin / skgesirq.c
blob: 53229d28933a6dc422611cb8f764b88d227a5ab1 [file] [log] [blame]
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1/******************************************************************************
2 *
3 * Name: skgesirq.c
4 * Project: GEnesis, PCI Gigabit Ethernet Adapter
5 * Version: $Revision: 1.83 $
6 * Date: $Date: 2003/02/05 15:10:59 $
7 * Purpose: Special IRQ module
8 *
9 ******************************************************************************/
10
11/******************************************************************************
12 *
13 * (C)Copyright 1998-2003 SysKonnect GmbH.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * The information in this file is provided "AS IS" without warranty.
21 *
22 ******************************************************************************/
23
24/******************************************************************************
25 *
26 * History:
27 *
28 * $Log: skgesirq.c,v $
29 * Revision 1.83 2003/02/05 15:10:59 rschmidt
30 * Fixed setting of PLinkSpeedUsed in SkHWLinkUp() when
31 * auto-negotiation is disabled.
32 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]33 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]34 * Revision 1.82 2003/01/29 13:34:33 rschmidt
35 * Added some typecasts to avoid compiler warnings.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]36 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]37 * Revision 1.81 2002/12/05 10:49:51 rschmidt
38 * Fixed missing Link Down Event for fiber (Bug Id #10768)
39 * Added reading of cable length when link is up
40 * Removed testing of unused error bits in PHY ISR
41 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]42 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]43 * Revision 1.80 2002/11/12 17:15:21 rschmidt
44 * Replaced SkPnmiGetVar() by ...MacStatistic() in SkMacParity().
45 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]46 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]47 * Revision 1.79 2002/10/14 15:14:51 rschmidt
48 * Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in
49 * SkMacParity() depending on GIChipRev (HW-Bug #8).
50 * Added error messages for GPHY Auto-Negotiation Error and
51 * FIFO Overflow/Underrun in SkPhyIsrGmac().
52 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]53 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]54 * Revision 1.78 2002/10/10 15:54:29 mkarl
55 * changes for PLinkSpeedUsed
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]56 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]57 * Revision 1.77 2002/09/12 08:58:51 rwahl
58 * Retrieve counters needed for XMAC errata workarounds directly because
59 * PNMI returns corrected counter values (e.g. #10620).
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]60 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]61 * Revision 1.76 2002/08/16 15:21:54 rschmidt
62 * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
63 * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros.
64 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]65 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]66 * Revision 1.75 2002/08/12 13:50:47 rschmidt
67 * Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in
68 * SkMacParity() by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE (HW-Bug #8).
69 * Added clearing of IS_IRQ_TIST_OV and IS_IRQ_SENSOR in SkGeHwErr().
70 * Corrected handling of Link Up and Auto-Negotiation Over for GPHY.
71 * in SkGePortCheckUpGmac().
72 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]73 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]74 * Revision 1.74 2002/08/08 16:17:04 rschmidt
75 * Added PhyType check for SK_HWEV_SET_ROLE event (copper only)
76 * Changed Link Up check reading PHY Specific Status (YUKON)
77 * Editorial changes
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]78 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]79 * Revision 1.73 2002/07/15 18:36:53 rwahl
80 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]81 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]82 * Revision 1.72 2002/07/15 15:46:26 rschmidt
83 * Added new event: SK_HWEV_SET_SPEED
84 * Editorial changes
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]85 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]86 * Revision 1.71 2002/06/10 09:34:19 rschmidt
87 * Editorial changes
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]88 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]89 * Revision 1.70 2002/06/05 08:29:18 rschmidt
90 * SkXmRxTxEnable() replaced by SkMacRxTxEnable().
91 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]92 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]93 * Revision 1.69 2002/04/25 13:03:49 rschmidt
94 * Changes for handling YUKON.
95 * Use of #ifdef OTHER_PHY to eliminate code for unused Phy types.
96 * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(),
97 * SkMacIrqDisable().
98 * Added handling for GMAC FIFO in SkMacParity().
99 * Replaced all SkXm...() functions with SkMac...() to handle also
100 * YUKON's GMAC.
101 * Macros for XMAC PHY access PHY_READ(), PHY_WRITE() replaced
102 * by functions SkXmPhyRead(), SkXmPhyWrite().
103 * Disabling all PHY interrupts moved to SkMacIrqDisable().
104 * Added handling for GPHY IRQ in SkGeSirqIsr().
105 * Removed status parameter from MAC IRQ handler SkMacIrq().
106 * Added SkGePortCheckUpGmac(), SkPhyIsrGmac() for GMAC.
107 * Editorial changes
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]108 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]109 * Revision 1.68 2002/02/26 15:24:53 rwahl
110 * Fix: no link with manual configuration (#10673). The previous fix for
111 * #10639 was removed. So for RLMT mode = CLS the RLMT may switch to
112 * misconfigured port. It should not occur for the other RLMT modes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]113 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]114 * Revision 1.67 2001/11/20 09:19:58 rwahl
115 * Reworked bugfix #10639 (no dependency to RLMT mode).
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]116 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]117 * Revision 1.66 2001/10/26 07:52:53 afischer
118 * Port switching bug in `check local link` mode
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]119 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]120 * Revision 1.65 2001/02/23 13:41:51 gklug
121 * fix: PHYS2INST should be used correctly for Dual Net operation
122 * chg: do no longer work with older PNMI
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]123 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]124 * Revision 1.64 2001/02/15 11:27:04 rassmann
125 * Working with RLMT v1 if SK_MAX_NETS undefined.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]126 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]127 * Revision 1.63 2001/02/06 10:44:23 mkunz
128 * - NetIndex added to interface functions of pnmi V4 with dual net support
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]129 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]130 * Revision 1.62 2001/01/31 15:31:41 gklug
131 * fix: problem with autosensing an SR8800 switch
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]132 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]133 * Revision 1.61 2000/11/09 11:30:09 rassmann
134 * WA: Waiting after releasing reset until BCom chip is accessible.
135 *
136 * Revision 1.60 2000/10/18 12:37:48 cgoos
137 * Reinserted the comment for version 1.56.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]138 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]139 * Revision 1.59 2000/10/18 12:22:20 cgoos
140 * Added workaround for half duplex hangup.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]141 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]142 * Revision 1.58 2000/09/28 13:06:04 gklug
143 * fix: BCom may NOT be touched if XMAC is in RESET state
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]144 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]145 * Revision 1.57 2000/09/08 12:38:39 cgoos
146 * Added forgotten variable declaration.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]147 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]148 * Revision 1.56 2000/09/08 08:12:13 cgoos
149 * Changed handling of parity errors in SkGeHwErr (correct reset of error).
150 *
151 * Revision 1.55 2000/06/19 08:36:25 cgoos
152 * Changed comment.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]153 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]154 * Revision 1.54 2000/05/22 08:45:57 malthoff
155 * Fix: #10523 is valid for all BCom PHYs.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]156 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]157 * Revision 1.53 2000/05/19 10:20:30 cgoos
158 * Removed Solaris debug output code.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]159 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]160 * Revision 1.52 2000/05/19 10:19:37 cgoos
161 * Added PHY state check in HWLinkDown.
162 * Move PHY interrupt code to IS_EXT_REG case in SkGeSirqIsr.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]163 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]164 * Revision 1.51 2000/05/18 05:56:20 cgoos
165 * Fixed typo.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]166 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]167 * Revision 1.50 2000/05/17 12:49:49 malthoff
168 * Fixes BCom link bugs (#10523).
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]169 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]170 * Revision 1.49 1999/12/17 11:02:50 gklug
171 * fix: read PHY_STAT of Broadcom chip more often to assure good status
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]172 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]173 * Revision 1.48 1999/12/06 10:01:17 cgoos
174 * Added SET function for Role.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]175 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]176 * Revision 1.47 1999/11/22 13:34:24 cgoos
177 * Changed license header to GPL.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]178 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]179 * Revision 1.46 1999/09/16 10:30:07 cgoos
180 * Removed debugging output statement from Linux.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]181 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]182 * Revision 1.45 1999/09/16 07:32:55 cgoos
183 * Fixed dual-port copperfield bug (PHY_READ from resetted port).
184 * Removed some unused variables.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]185 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]186 * Revision 1.44 1999/08/03 15:25:04 cgoos
187 * Removed workaround for disabled interrupts in half duplex mode.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]188 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]189 * Revision 1.43 1999/08/03 14:27:58 cgoos
190 * Removed SENSE mode code from SkGePortCheckUpBcom.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]191 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]192 * Revision 1.42 1999/07/26 09:16:54 cgoos
193 * Added some typecasts to avoid compiler warnings.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]194 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]195 * Revision 1.41 1999/05/19 07:28:59 cgoos
196 * Changes for 1000Base-T.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]197 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]198 * Revision 1.40 1999/04/08 13:59:39 gklug
199 * fix: problem with 3Com switches endless RESTARTs
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]200 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]201 * Revision 1.39 1999/03/08 10:10:52 gklug
202 * fix: AutoSensing did switch to next mode even if LiPa indicated offline
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]203 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]204 * Revision 1.38 1999/03/08 09:49:03 gklug
205 * fix: Bug using pAC instead of IoC, causing AIX problems
206 * fix: change compare for Linux compiler bug workaround
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]207 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]208 * Revision 1.37 1999/01/28 14:51:33 gklug
209 * fix: monitor for autosensing and extra RESETS the RX on wire counters
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]210 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]211 * Revision 1.36 1999/01/22 09:19:55 gklug
212 * fix: Init DupMode and InitPauseMd are now called in RxTxEnable
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]213 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]214 * Revision 1.35 1998/12/11 15:22:59 gklug
215 * chg: autosensing: check for receive if manual mode was guessed
216 * chg: simplified workaround for XMAC errata
217 * chg: wait additional 100 ms before link goes up.
218 * chg: autoneg timeout to 600 ms
219 * chg: restart autoneg even if configured to autonegotiation
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]220 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]221 * Revision 1.34 1998/12/10 10:33:14 gklug
222 * add: more debug messages
223 * fix: do a new InitPhy if link went down (AutoSensing problem)
224 * chg: Check for zero shorts if link is NOT up
225 * chg: reset Port if link goes down
226 * chg: wait additional 100 ms when link comes up to check shorts
227 * fix: dummy read extended autoneg status to prevent link going down immediately
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]228 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]229 * Revision 1.33 1998/12/07 12:18:29 gklug
230 * add: refinement of autosense mode: take into account the autoneg cap of LiPa
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]231 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]232 * Revision 1.32 1998/12/07 07:11:21 gklug
233 * fix: compiler warning
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]234 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]235 * Revision 1.31 1998/12/02 09:29:05 gklug
236 * fix: WA XMAC Errata: FCSCt check was not correct.
237 * fix: WA XMAC Errata: Prec Counter were NOT updated in case of short checks.
238 * fix: Clear Stat : now clears the Prev counters of all known Ports
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]239 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]240 * Revision 1.30 1998/12/01 10:54:15 gklug
241 * dd: workaround for XMAC errata changed. Check RX count and CRC err Count, too.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]242 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]243 * Revision 1.29 1998/12/01 10:01:53 gklug
244 * fix: if MAC IRQ occurs during port down, this will be handled correctly
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]245 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]246 * Revision 1.28 1998/11/26 16:22:11 gklug
247 * fix: bug in autosense if manual modes are used
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]248 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]249 * Revision 1.27 1998/11/26 15:50:06 gklug
250 * fix: PNMI needs to set PLinkModeConf
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]251 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]252 * Revision 1.26 1998/11/26 14:51:58 gklug
253 * add: AutoSensing functionalty
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]254 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]255 * Revision 1.25 1998/11/26 07:34:37 gklug
256 * fix: Init PrevShorts when restarting port due to Link connection
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]257 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]258 * Revision 1.24 1998/11/25 10:57:32 gklug
259 * fix: remove unreferenced local vars
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]260 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]261 * Revision 1.23 1998/11/25 08:26:40 gklug
262 * fix: don't do a RESET on a starting or stopping port
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]263 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]264 * Revision 1.22 1998/11/24 13:29:44 gklug
265 * add: Workaround for MAC parity errata
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]266 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]267 * Revision 1.21 1998/11/18 15:31:06 gklug
268 * fix: lint bugs
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]269 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]270 * Revision 1.20 1998/11/18 12:58:54 gklug
271 * fix: use PNMI query instead of hardware access
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]272 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]273 * Revision 1.19 1998/11/18 12:54:55 gklug
274 * chg: add new workaround for XMAC Errata
275 * add: short event counter monitoring on active link too
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]276 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]277 * Revision 1.18 1998/11/13 14:27:41 malthoff
278 * Bug Fix: Packet Arbiter Timeout was not cleared correctly
279 * for timeout on TX1 and TX2.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]280 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]281 * Revision 1.17 1998/11/04 07:01:59 cgoos
282 * Moved HW link poll sequence.
283 * Added call to SkXmRxTxEnable.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]284 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]285 * Revision 1.16 1998/11/03 13:46:03 gklug
286 * add: functionality of SET_LMODE and SET_FLOW_MODE
287 * fix: send RLMT LinkDown event when Port stop is given with LinkUp
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]288 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]289 * Revision 1.15 1998/11/03 12:56:47 gklug
290 * fix: Needs more events
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]291 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]292 * Revision 1.14 1998/10/30 07:36:35 gklug
293 * rmv: unnecessary code
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]294 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]295 * Revision 1.13 1998/10/29 15:21:57 gklug
296 * add: Poll link feature for activating HW link
297 * fix: Deactivate HWLink when Port STOP is given
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]298 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]299 * Revision 1.12 1998/10/28 07:38:57 cgoos
300 * Checking link status at begin of SkHWLinkUp.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]301 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]302 * Revision 1.11 1998/10/22 09:46:50 gklug
303 * fix SysKonnectFileId typo
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]304 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]305 * Revision 1.10 1998/10/14 13:57:47 gklug
306 * add: Port start/stop event
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]307 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]308 * Revision 1.9 1998/10/14 05:48:29 cgoos
309 * Added definition for Para.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]310 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]311 * Revision 1.8 1998/10/14 05:40:09 gklug
312 * add: Hardware Linkup signal used
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]313 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]314 * Revision 1.7 1998/10/09 06:50:20 malthoff
315 * Remove ID_sccs by SysKonnectFileId.
316 *
317 * Revision 1.6 1998/10/08 09:11:49 gklug
318 * add: clear IRQ commands
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]319 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]320 * Revision 1.5 1998/10/02 14:27:35 cgoos
321 * Fixed some typos and wrong event names.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]322 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]323 * Revision 1.4 1998/10/02 06:24:17 gklug
324 * add: HW error function
325 * fix: OUT macros
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]326 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]327 * Revision 1.3 1998/10/01 07:03:00 gklug
328 * add: ISR for the usual interrupt source register
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]329 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]330 * Revision 1.2 1998/09/03 13:50:33 gklug
331 * add: function prototypes
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]332 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]333 * Revision 1.1 1998/08/27 11:50:21 gklug
334 * initial revision
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]335 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]336 *
337 *
338 ******************************************************************************/
339
wdenk149dded2003-09-10 18:20:28 +0000[diff] [blame]340#include <config.h>
341
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]342/*
343 * Special Interrupt handler
344 *
345 * The following abstract should show how this module is included
346 * in the driver path:
347 *
348 * In the ISR of the driver the bits for frame transmission complete and
349 * for receive complete are checked and handled by the driver itself.
350 * The bits of the slow path mask are checked after that and then the
351 * entry into the so-called "slow path" is prepared. It is an implementors
352 * decision whether this is executed directly or just scheduled by
353 * disabling the mask. In the interrupt service routine some events may be
354 * generated, so it would be a good idea to call the EventDispatcher
355 * right after this ISR.
356 *
357 * The Interrupt source register of the adapter is NOT read by this module.
358 * SO if the drivers implementor needs a while loop around the
359 * slow data paths interrupt bits, he needs to call the SkGeSirqIsr() for
360 * each loop entered.
361 *
362 * However, the MAC Interrupt status registers are read in a while loop.
363 *
364 */
365
366static const char SysKonnectFileId[] =
367 "$Id: skgesirq.c,v 1.83 2003/02/05 15:10:59 rschmidt Exp $" ;
368
369#include "h/skdrv1st.h" /* Driver Specific Definitions */
370#include "h/skgepnmi.h" /* PNMI Definitions */
371#include "h/skrlmt.h" /* RLMT Definitions */
372#include "h/skdrv2nd.h" /* Adapter Control and Driver specific Def. */
373
374/* local function prototypes */
375static int SkGePortCheckUpXmac(SK_AC*, SK_IOC, int);
376static int SkGePortCheckUpBcom(SK_AC*, SK_IOC, int);
377static int SkGePortCheckUpGmac(SK_AC*, SK_IOC, int);
378static void SkPhyIsrBcom(SK_AC*, SK_IOC, int, SK_U16);
379static void SkPhyIsrGmac(SK_AC*, SK_IOC, int, SK_U16);
380#ifdef OTHER_PHY
381static int SkGePortCheckUpLone(SK_AC*, SK_IOC, int);
382static int SkGePortCheckUpNat(SK_AC*, SK_IOC, int);
383static void SkPhyIsrLone(SK_AC*, SK_IOC, int, SK_U16);
384#endif /* OTHER_PHY */
385
386/*
387 * array of Rx counter from XMAC which are checked
388 * in AutoSense mode to check whether a link is not able to auto-negotiate.
389 */
390static const SK_U16 SkGeRxRegs[]= {
391 XM_RXF_64B,
392 XM_RXF_127B,
393 XM_RXF_255B,
394 XM_RXF_511B,
395 XM_RXF_1023B,
396 XM_RXF_MAX_SZ
397} ;
398
399#ifdef __C2MAN__
400/*
401 * Special IRQ function
402 *
403 * General Description:
404 *
405 */
406intro()
407{}
408#endif
409
410/* Define return codes of SkGePortCheckUp and CheckShort */
411#define SK_HW_PS_NONE 0 /* No action needed */
412#define SK_HW_PS_RESTART 1 /* Restart needed */
413#define SK_HW_PS_LINK 2 /* Link Up actions needed */
414
415/******************************************************************************
416 *
417 * SkHWInitDefSense() - Default Autosensing mode initialization
418 *
419 * Description: sets the PLinkMode for HWInit
420 *
421 * Returns: N/A
422 */
423static void SkHWInitDefSense(
424SK_AC *pAC, /* adapter context */
425SK_IOC IoC, /* IO context */
426int Port) /* Port Index (MAC_1 + n) */
427{
428 SK_GEPORT *pPrt; /* GIni Port struct pointer */
429
430 pPrt = &pAC->GIni.GP[Port];
431
432 pPrt->PAutoNegTimeOut = 0;
433
434 if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
435 pPrt->PLinkMode = pPrt->PLinkModeConf;
436 return;
437 }
438
439 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
440 ("AutoSensing: First mode %d on Port %d\n",
441 (int)SK_LMODE_AUTOFULL, Port));
442
443 pPrt->PLinkMode = SK_LMODE_AUTOFULL;
444
445 return;
446} /* SkHWInitDefSense */
447
448
449/******************************************************************************
450 *
451 * SkHWSenseGetNext() - Get Next Autosensing Mode
452 *
453 * Description: gets the appropriate next mode
454 *
455 * Note:
456 *
457 */
458SK_U8 SkHWSenseGetNext(
459SK_AC *pAC, /* adapter context */
460SK_IOC IoC, /* IO context */
461int Port) /* Port Index (MAC_1 + n) */
462{
463 SK_GEPORT *pPrt; /* GIni Port struct pointer */
464
465 pPrt = &pAC->GIni.GP[Port];
466
467 pPrt->PAutoNegTimeOut = 0;
468
469 if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
470 /* Leave all as configured */
471 return(pPrt->PLinkModeConf);
472 }
473
474 if (pPrt->PLinkMode == SK_LMODE_AUTOFULL) {
475 /* Return next mode AUTOBOTH */
476 return(SK_LMODE_AUTOBOTH);
477 }
478
479 /* Return default autofull */
480 return(SK_LMODE_AUTOFULL);
481} /* SkHWSenseGetNext */
482
483
484/******************************************************************************
485 *
486 * SkHWSenseSetNext() - Autosensing Set next mode
487 *
488 * Description: sets the appropriate next mode
489 *
490 * Returns: N/A
491 */
492void SkHWSenseSetNext(
493SK_AC *pAC, /* adapter context */
494SK_IOC IoC, /* IO context */
495int Port, /* Port Index (MAC_1 + n) */
496SK_U8 NewMode) /* New Mode to be written in sense mode */
497{
498 SK_GEPORT *pPrt; /* GIni Port struct pointer */
499
500 pPrt = &pAC->GIni.GP[Port];
501
502 pPrt->PAutoNegTimeOut = 0;
503
504 if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
505 return;
506 }
507
508 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
509 ("AutoSensing: next mode %d on Port %d\n",
510 (int)NewMode, Port));
511
512 pPrt->PLinkMode = NewMode;
513
514 return;
515} /* SkHWSenseSetNext */
516
517
518/******************************************************************************
519 *
520 * SkHWLinkDown() - Link Down handling
521 *
522 * Description: handles the hardware link down signal
523 *
524 * Returns: N/A
525 */
526void SkHWLinkDown(
527SK_AC *pAC, /* adapter context */
528SK_IOC IoC, /* IO context */
529int Port) /* Port Index (MAC_1 + n) */
530{
531 SK_GEPORT *pPrt; /* GIni Port struct pointer */
532
533 pPrt = &pAC->GIni.GP[Port];
534
535 /* Disable all MAC interrupts */
536 SkMacIrqDisable(pAC, IoC, Port);
537
538 /* Disable Receiver and Transmitter */
539 SkMacRxTxDisable(pAC, IoC, Port);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]540
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]541 /* Init default sense mode */
542 SkHWInitDefSense(pAC, IoC, Port);
543
544 if (!pPrt->PHWLinkUp) {
545 return;
546 }
547
548 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
549 ("Link down Port %d\n", Port));
550
551 /* Set Link to DOWN */
552 pPrt->PHWLinkUp = SK_FALSE;
553
554 /* Reset Port stati */
555 pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
556 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
557 pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_INDETERMINATED;
558
559 /* Re-init Phy especially when the AutoSense default is set now */
560 SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
561
562 /* GP0: used for workaround of Rev. C Errata 2 */
563
564 /* Do NOT signal to RLMT */
565
566 /* Do NOT start the timer here */
567} /* SkHWLinkDown */
568
569
570/******************************************************************************
571 *
572 * SkHWLinkUp() - Link Up handling
573 *
574 * Description: handles the hardware link up signal
575 *
576 * Returns: N/A
577 */
578void SkHWLinkUp(
579SK_AC *pAC, /* adapter context */
580SK_IOC IoC, /* IO context */
581int Port) /* Port Index (MAC_1 + n) */
582{
583 SK_GEPORT *pPrt; /* GIni Port struct pointer */
584
585 pPrt = &pAC->GIni.GP[Port];
586
587 if (pPrt->PHWLinkUp) {
588 /* We do NOT need to proceed on active link */
589 return;
590 }
591
592 pPrt->PHWLinkUp = SK_TRUE;
593 pPrt->PAutoNegFail = SK_FALSE;
594 pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
595
596 if (pPrt->PLinkMode != SK_LMODE_AUTOHALF &&
597 pPrt->PLinkMode != SK_LMODE_AUTOFULL &&
598 pPrt->PLinkMode != SK_LMODE_AUTOBOTH) {
599 /* Link is up and no Auto-negotiation should be done */
600
601 /* Link speed should be the configured one */
602 switch (pPrt->PLinkSpeed) {
603 case SK_LSPEED_AUTO:
604 /* default is 1000 Mbps */
605 case SK_LSPEED_1000MBPS:
606 pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS;
607 break;
608 case SK_LSPEED_100MBPS:
609 pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_100MBPS;
610 break;
611 case SK_LSPEED_10MBPS:
612 pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_10MBPS;
613 break;
614 }
615
616 /* Set Link Mode Status */
617 if (pPrt->PLinkMode == SK_LMODE_FULL) {
618 pPrt->PLinkModeStatus = SK_LMODE_STAT_FULL;
619 }
620 else {
621 pPrt->PLinkModeStatus = SK_LMODE_STAT_HALF;
622 }
623
624 /* No flow control without auto-negotiation */
625 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
626
627 /* enable Rx/Tx */
628 SkMacRxTxEnable(pAC, IoC, Port);
629 }
630} /* SkHWLinkUp */
631
632
633/******************************************************************************
634 *
635 * SkMacParity() - MAC parity workaround
636 *
637 * Description: handles MAC parity errors correctly
638 *
639 * Returns: N/A
640 */
641static void SkMacParity(
642SK_AC *pAC, /* adapter context */
643SK_IOC IoC, /* IO context */
644int Port) /* Port Index of the port failed */
645{
646 SK_EVPARA Para;
647 SK_GEPORT *pPrt; /* GIni Port struct pointer */
648 SK_U32 TxMax; /* TxMax Counter */
649
650 pPrt = &pAC->GIni.GP[Port];
651
652 /* Clear IRQ Tx Parity Error */
653 if (pAC->GIni.GIGenesis) {
654 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_PERR);
655 }
656 else {
657 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
658 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T),
659 (SK_U8)((pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE));
660 }
661
662 if (pPrt->PCheckPar) {
663 if (Port == MAC_1) {
664 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG);
665 }
666 else {
667 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG);
668 }
669 Para.Para64 = Port;
670 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
671 Para.Para32[0] = Port;
672 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
673
674 return;
675 }
676
677 /* Check whether frames with a size of 1k were sent */
678 if (pAC->GIni.GIGenesis) {
679 /* Snap statistic counters */
680 (void)SkXmUpdateStats(pAC, IoC, Port);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]681
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]682 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXF_MAX_SZ, &TxMax);
683 }
684 else {
685 (void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax);
686 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]687
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]688 if (TxMax > 0) {
689 /* From now on check the parity */
690 pPrt->PCheckPar = SK_TRUE;
691 }
692} /* SkMacParity */
693
694
695/******************************************************************************
696 *
697 * SkGeHwErr() - Hardware Error service routine
698 *
699 * Description: handles all HW Error interrupts
700 *
701 * Returns: N/A
702 */
703static void SkGeHwErr(
704SK_AC *pAC, /* adapter context */
705SK_IOC IoC, /* IO context */
706SK_U32 HwStatus) /* Interrupt status word */
707{
708 SK_EVPARA Para;
709 SK_U16 Word;
710
711 if ((HwStatus & (IS_IRQ_MST_ERR | IS_IRQ_STAT)) != 0) {
712 /* PCI Errors occured */
713 if ((HwStatus & IS_IRQ_STAT) != 0) {
714 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG);
715 }
716 else {
717 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG);
718 }
719
720 /* Reset all bits in the PCI STATUS register */
721 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]722
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]723 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
724 SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
725 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
726
727 Para.Para64 = 0;
728 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
729 }
730
731 if (pAC->GIni.GIGenesis) {
732 if ((HwStatus & IS_NO_STAT_M1) != 0) {
733 /* Ignore it */
734 /* This situation is also indicated in the descriptor */
735 SK_OUT16(IoC, MR_ADDR(MAC_1, RX_MFF_CTRL1), MFF_CLR_INSTAT);
736 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]737
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]738 if ((HwStatus & IS_NO_STAT_M2) != 0) {
739 /* Ignore it */
740 /* This situation is also indicated in the descriptor */
741 SK_OUT16(IoC, MR_ADDR(MAC_2, RX_MFF_CTRL1), MFF_CLR_INSTAT);
742 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]743
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]744 if ((HwStatus & IS_NO_TIST_M1) != 0) {
745 /* Ignore it */
746 /* This situation is also indicated in the descriptor */
747 SK_OUT16(IoC, MR_ADDR(MAC_1, RX_MFF_CTRL1), MFF_CLR_INTIST);
748 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]749
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]750 if ((HwStatus & IS_NO_TIST_M2) != 0) {
751 /* Ignore it */
752 /* This situation is also indicated in the descriptor */
753 SK_OUT16(IoC, MR_ADDR(MAC_2, RX_MFF_CTRL1), MFF_CLR_INTIST);
754 }
755 }
756 else { /* YUKON */
757 /* This is necessary only for Rx timing measurements */
758 if ((HwStatus & IS_IRQ_TIST_OV) != 0) {
759 /* Clear Time Stamp Timer IRQ */
760 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ);
761 }
762
763 if ((HwStatus & IS_IRQ_SENSOR) != 0) {
764 /* Clear I2C IRQ */
765 SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
766 }
767 }
768
769 if ((HwStatus & IS_RAM_RD_PAR) != 0) {
770 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR);
771 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E014, SKERR_SIRQ_E014MSG);
772 Para.Para64 = 0;
773 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
774 }
775
776 if ((HwStatus & IS_RAM_WR_PAR) != 0) {
777 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR);
778 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E015, SKERR_SIRQ_E015MSG);
779 Para.Para64 = 0;
780 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
781 }
782
783 if ((HwStatus & IS_M1_PAR_ERR) != 0) {
784 SkMacParity(pAC, IoC, MAC_1);
785 }
786
787 if ((HwStatus & IS_M2_PAR_ERR) != 0) {
788 SkMacParity(pAC, IoC, MAC_2);
789 }
790
791 if ((HwStatus & IS_R1_PAR_ERR) != 0) {
792 /* Clear IRQ */
793 SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_P);
794
795 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
796 Para.Para64 = MAC_1;
797 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
798 Para.Para32[0] = MAC_1;
799 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
800 }
801
802 if ((HwStatus & IS_R2_PAR_ERR) != 0) {
803 /* Clear IRQ */
804 SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_P);
805
806 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
807 Para.Para64 = MAC_2;
808 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
809 Para.Para32[0] = MAC_2;
810 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
811 }
812} /* SkGeHwErr */
813
814
815/******************************************************************************
816 *
817 * SkGeSirqIsr() - Special Interrupt Service Routine
818 *
819 * Description: handles all non data transfer specific interrupts (slow path)
820 *
821 * Returns: N/A
822 */
823void SkGeSirqIsr(
824SK_AC *pAC, /* adapter context */
825SK_IOC IoC, /* IO context */
826SK_U32 Istatus) /* Interrupt status word */
827{
828 SK_EVPARA Para;
829 SK_U32 RegVal32; /* Read register value */
830 SK_GEPORT *pPrt; /* GIni Port struct pointer */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]831 unsigned Len;
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]832 SK_U64 Octets;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]833 SK_U16 PhyInt;
834 SK_U16 PhyIMsk;
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]835 int i;
836
837 if ((Istatus & IS_HW_ERR) != 0) {
838 /* read the HW Error Interrupt source */
839 SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]840
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]841 SkGeHwErr(pAC, IoC, RegVal32);
842 }
843
844 /*
845 * Packet Timeout interrupts
846 */
847 /* Check whether MACs are correctly initialized */
848 if (((Istatus & (IS_PA_TO_RX1 | IS_PA_TO_TX1)) != 0) &&
849 pAC->GIni.GP[MAC_1].PState == SK_PRT_RESET) {
850 /* MAC 1 was not initialized but Packet timeout occured */
851 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E004,
852 SKERR_SIRQ_E004MSG);
853 }
854
855 if (((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) != 0) &&
856 pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
857 /* MAC 2 was not initialized but Packet timeout occured */
858 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005,
859 SKERR_SIRQ_E005MSG);
860 }
861
862 if ((Istatus & IS_PA_TO_RX1) != 0) {
863 /* Means network is filling us up */
864 SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E002,
865 SKERR_SIRQ_E002MSG);
866 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX1);
867 }
868
869 if ((Istatus & IS_PA_TO_RX2) != 0) {
870 /* Means network is filling us up */
871 SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E003,
872 SKERR_SIRQ_E003MSG);
873 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX2);
874 }
875
876 if ((Istatus & IS_PA_TO_TX1) != 0) {
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]877
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]878 pPrt = &pAC->GIni.GP[0];
879
880 /* May be a normal situation in a server with a slow network */
881 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1);
882
883 /*
884 * workaround: if in half duplex mode, check for Tx hangup.
885 * Read number of TX'ed bytes, wait for 10 ms, then compare
886 * the number with current value. If nothing changed, we assume
887 * that Tx is hanging and do a FIFO flush (see event routine).
888 */
889 if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF ||
890 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) &&
891 !pPrt->HalfDupTimerActive) {
892 /*
893 * many more pack. arb. timeouts may come in between,
894 * we ignore those
895 */
896 pPrt->HalfDupTimerActive = SK_TRUE;
897
898 Len = sizeof(SK_U64);
899 SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets,
900 &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 0),
901 pAC->Rlmt.Port[0].Net->NetNumber);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]902
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]903 pPrt->LastOctets = Octets;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]904
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]905 Para.Para32[0] = 0;
906 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
907 SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
908 }
909 }
910
911 if ((Istatus & IS_PA_TO_TX2) != 0) {
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]912
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]913 pPrt = &pAC->GIni.GP[1];
914
915 /* May be a normal situation in a server with a slow network */
916 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2);
917
918 /* workaround: see above */
919 if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF ||
920 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) &&
921 !pPrt->HalfDupTimerActive) {
922 pPrt->HalfDupTimerActive = SK_TRUE;
923
924 Len = sizeof(SK_U64);
925 SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets,
926 &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 1),
927 pAC->Rlmt.Port[1].Net->NetNumber);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]928
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]929 pPrt->LastOctets = Octets;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]930
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]931 Para.Para32[0] = 1;
932 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
933 SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
934 }
935 }
936
937 /* Check interrupts of the particular queues */
938 if ((Istatus & IS_R1_C) != 0) {
939 /* Clear IRQ */
940 SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C);
941 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006,
942 SKERR_SIRQ_E006MSG);
943 Para.Para64 = MAC_1;
944 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
945 Para.Para32[0] = MAC_1;
946 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
947 }
948
949 if ((Istatus & IS_R2_C) != 0) {
950 /* Clear IRQ */
951 SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C);
952 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007,
953 SKERR_SIRQ_E007MSG);
954 Para.Para64 = MAC_2;
955 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
956 Para.Para32[0] = MAC_2;
957 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
958 }
959
960 if ((Istatus & IS_XS1_C) != 0) {
961 /* Clear IRQ */
962 SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C);
963 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008,
964 SKERR_SIRQ_E008MSG);
965 Para.Para64 = MAC_1;
966 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
967 Para.Para32[0] = MAC_1;
968 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
969 }
970
971 if ((Istatus & IS_XA1_C) != 0) {
972 /* Clear IRQ */
973 SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C);
974 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009,
975 SKERR_SIRQ_E009MSG);
976 Para.Para64 = MAC_1;
977 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
978 Para.Para32[0] = MAC_1;
979 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
980 }
981
982 if ((Istatus & IS_XS2_C) != 0) {
983 /* Clear IRQ */
984 SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C);
985 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010,
986 SKERR_SIRQ_E010MSG);
987 Para.Para64 = MAC_2;
988 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
989 Para.Para32[0] = MAC_2;
990 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
991 }
992
993 if ((Istatus & IS_XA2_C) != 0) {
994 /* Clear IRQ */
995 SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C);
996 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011,
997 SKERR_SIRQ_E011MSG);
998 Para.Para64 = MAC_2;
999 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
1000 Para.Para32[0] = MAC_2;
1001 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
1002 }
1003
1004 /* External reg interrupt */
1005 if ((Istatus & IS_EXT_REG) != 0) {
1006 /* Test IRQs from PHY */
1007 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1008
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1009 pPrt = &pAC->GIni.GP[i];
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1010
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1011 if (pPrt->PState == SK_PRT_RESET) {
1012 continue;
1013 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1014
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1015 switch (pPrt->PhyType) {
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1016
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1017 case SK_PHY_XMAC:
1018 break;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1019
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1020 case SK_PHY_BCOM:
1021 SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt);
1022 SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_MASK, &PhyIMsk);
1023
1024 if ((PhyInt & ~PhyIMsk) != 0) {
1025 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1026 ("Port %d Bcom Int: 0x%04X Mask: 0x%04X\n",
1027 i, PhyInt, PhyIMsk));
1028 SkPhyIsrBcom(pAC, IoC, i, PhyInt);
1029 }
1030 break;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1031
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1032 case SK_PHY_MARV_COPPER:
1033 case SK_PHY_MARV_FIBER:
1034 SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_STAT, &PhyInt);
1035 SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_MASK, &PhyIMsk);
1036
1037 if ((PhyInt & PhyIMsk) != 0) {
1038 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1039 ("Port %d Marv Int: 0x%04X Mask: 0x%04X\n",
1040 i, PhyInt, PhyIMsk));
1041 SkPhyIsrGmac(pAC, IoC, i, PhyInt);
1042 }
1043 break;
1044
1045#ifdef OTHER_PHY
1046 case SK_PHY_LONE:
1047 SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt);
1048 SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_ENAB, &PhyIMsk);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1049
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1050 if ((PhyInt & PhyIMsk) != 0) {
1051 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1052 ("Port %d Lone Int: %x Mask: %x\n",
1053 i, PhyInt, PhyIMsk));
1054 SkPhyIsrLone(pAC, IoC, i, PhyInt);
1055 }
1056 break;
1057 case SK_PHY_NAT:
1058 /* todo: National */
1059 break;
1060#endif /* OTHER_PHY */
1061 }
1062 }
1063 }
1064
1065 /* I2C Ready interrupt */
1066 if ((Istatus & IS_I2C_READY) != 0) {
1067 SkI2cIsr(pAC, IoC);
1068 }
1069
1070 if ((Istatus & IS_LNK_SYNC_M1) != 0) {
1071 /*
1072 * We do NOT need the Link Sync interrupt, because it shows
1073 * us only a link going down.
1074 */
1075 /* clear interrupt */
1076 SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LED_CLR_IRQ);
1077 }
1078
1079 /* Check MAC after link sync counter */
1080 if ((Istatus & IS_MAC1) != 0) {
1081 /* IRQ from MAC 1 */
1082 SkMacIrq(pAC, IoC, MAC_1);
1083 }
1084
1085 if ((Istatus & IS_LNK_SYNC_M2) != 0) {
1086 /*
1087 * We do NOT need the Link Sync interrupt, because it shows
1088 * us only a link going down.
1089 */
1090 /* clear interrupt */
1091 SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LED_CLR_IRQ);
1092 }
1093
1094 /* Check MAC after link sync counter */
1095 if ((Istatus & IS_MAC2) != 0) {
1096 /* IRQ from MAC 2 */
1097 SkMacIrq(pAC, IoC, MAC_2);
1098 }
1099
1100 /* Timer interrupt (served last) */
1101 if ((Istatus & IS_TIMINT) != 0) {
1102 SkHwtIsr(pAC, IoC);
1103 }
1104} /* SkGeSirqIsr */
1105
1106
1107/******************************************************************************
1108 *
1109 * SkGePortCheckShorts() - Implementing XMAC Workaround Errata # 2
1110 *
1111 * return:
1112 * 0 o.k. nothing needed
1113 * 1 Restart needed on this port
1114 */
1115static int SkGePortCheckShorts(
1116SK_AC *pAC, /* Adapter Context */
1117SK_IOC IoC, /* IO Context */
1118int Port) /* Which port should be checked */
1119{
1120 SK_U32 Shorts; /* Short Event Counter */
1121 SK_U32 CheckShorts; /* Check value for Short Event Counter */
1122 SK_U64 RxCts; /* Rx Counter (packets on network) */
1123 SK_U32 RxTmp; /* Rx temp. Counter */
1124 SK_U32 FcsErrCts; /* FCS Error Counter */
1125 SK_GEPORT *pPrt; /* GIni Port struct pointer */
1126 int Rtv; /* Return value */
1127 int i;
1128
1129 pPrt = &pAC->GIni.GP[Port];
1130
1131 /* Default: no action */
1132 Rtv = SK_HW_PS_NONE;
1133
1134 (void)SkXmUpdateStats(pAC, IoC, Port);
1135
1136 /* Extra precaution: check for short Event counter */
1137 (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXE_SHT_ERR, &Shorts);
1138
1139 /*
1140 * Read Rx counter (packets seen on the network and not necessarily
1141 * really received.
1142 */
1143 RxCts = 0;
1144
1145 for (i = 0; i < sizeof(SkGeRxRegs)/sizeof(SkGeRxRegs[0]); i++) {
1146 (void)SkXmMacStatistic(pAC, IoC, Port, SkGeRxRegs[i], &RxTmp);
1147 RxCts += (SK_U64)RxTmp;
1148 }
1149
1150 /* On default: check shorts against zero */
1151 CheckShorts = 0;
1152
1153 /* Extra precaution on active links */
1154 if (pPrt->PHWLinkUp) {
1155 /* Reset Link Restart counter */
1156 pPrt->PLinkResCt = 0;
1157 pPrt->PAutoNegTOCt = 0;
1158
1159 /* If link is up check for 2 */
1160 CheckShorts = 2;
1161
1162 (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXF_FCS_ERR, &FcsErrCts);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1163
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1164 if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
1165 pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN &&
1166 (pPrt->PLinkMode == SK_LMODE_HALF ||
1167 pPrt->PLinkMode == SK_LMODE_FULL)) {
1168 /*
1169 * This is autosensing and we are in the fallback
1170 * manual full/half duplex mode.
1171 */
1172 if (RxCts == pPrt->PPrevRx) {
1173 /* Nothing received, restart link */
1174 pPrt->PPrevFcs = FcsErrCts;
1175 pPrt->PPrevShorts = Shorts;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1176
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1177 return(SK_HW_PS_RESTART);
1178 }
1179 else {
1180 pPrt->PLipaAutoNeg = SK_LIPA_MANUAL;
1181 }
1182 }
1183
1184 if (((RxCts - pPrt->PPrevRx) > pPrt->PRxLim) ||
1185 (!(FcsErrCts - pPrt->PPrevFcs))) {
1186 /*
1187 * Note: The compare with zero above has to be done the way shown,
1188 * otherwise the Linux driver will have a problem.
1189 */
1190 /*
1191 * We received a bunch of frames or no CRC error occured on the
1192 * network -> ok.
1193 */
1194 pPrt->PPrevRx = RxCts;
1195 pPrt->PPrevFcs = FcsErrCts;
1196 pPrt->PPrevShorts = Shorts;
1197
1198 return(SK_HW_PS_NONE);
1199 }
1200
1201 pPrt->PPrevFcs = FcsErrCts;
1202 }
1203
1204
1205 if ((Shorts - pPrt->PPrevShorts) > CheckShorts) {
1206 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1207 ("Short Event Count Restart Port %d \n", Port));
1208 Rtv = SK_HW_PS_RESTART;
1209 }
1210
1211 pPrt->PPrevShorts = Shorts;
1212 pPrt->PPrevRx = RxCts;
1213
1214 return(Rtv);
1215} /* SkGePortCheckShorts */
1216
1217
1218/******************************************************************************
1219 *
1220 * SkGePortCheckUp() - Check if the link is up
1221 *
1222 * return:
1223 * 0 o.k. nothing needed
1224 * 1 Restart needed on this port
1225 * 2 Link came up
1226 */
1227static int SkGePortCheckUp(
1228SK_AC *pAC, /* Adapter Context */
1229SK_IOC IoC, /* IO Context */
1230int Port) /* Which port should be checked */
1231{
1232 switch (pAC->GIni.GP[Port].PhyType) {
1233 case SK_PHY_XMAC:
1234 return(SkGePortCheckUpXmac(pAC, IoC, Port));
1235 case SK_PHY_BCOM:
1236 return(SkGePortCheckUpBcom(pAC, IoC, Port));
1237 case SK_PHY_MARV_COPPER:
1238 case SK_PHY_MARV_FIBER:
1239 return(SkGePortCheckUpGmac(pAC, IoC, Port));
1240#ifdef OTHER_PHY
1241 case SK_PHY_LONE:
1242 return(SkGePortCheckUpLone(pAC, IoC, Port));
1243 case SK_PHY_NAT:
1244 return(SkGePortCheckUpNat(pAC, IoC, Port));
1245#endif /* OTHER_PHY */
1246 }
1247 return(SK_HW_PS_NONE);
1248} /* SkGePortCheckUp */
1249
1250
1251/******************************************************************************
1252 *
1253 * SkGePortCheckUpXmac() - Implementing of the Workaround Errata # 2
1254 *
1255 * return:
1256 * 0 o.k. nothing needed
1257 * 1 Restart needed on this port
1258 * 2 Link came up
1259 */
1260static int SkGePortCheckUpXmac(
1261SK_AC *pAC, /* Adapter Context */
1262SK_IOC IoC, /* IO Context */
1263int Port) /* Which port should be checked */
1264{
1265 SK_U32 Shorts; /* Short Event Counter */
1266 SK_GEPORT *pPrt; /* GIni Port struct pointer */
1267 int Done;
1268 SK_U32 GpReg; /* General Purpose register value */
Wolfgang Denk2d6d9f02009-09-11 09:36:31 +0200[diff] [blame]1269 SK_U32 *pGpReg; /* Pointer to -- " -- */
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1270 SK_U16 Isrc; /* Interrupt source register */
1271 SK_U16 IsrcSum; /* Interrupt source register sum */
1272 SK_U16 LpAb; /* Link Partner Ability */
1273 SK_U16 ResAb; /* Resolved Ability */
1274 SK_U16 ExtStat; /* Extended Status Register */
1275 SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */
1276 SK_U8 NextMode; /* Next AutoSensing Mode */
1277
Wolfgang Denk2d6d9f02009-09-11 09:36:31 +0200[diff] [blame]1278 pGpReg = &GpReg;
1279
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1280 pPrt = &pAC->GIni.GP[Port];
1281
1282 if (pPrt->PHWLinkUp) {
1283 if (pPrt->PhyType != SK_PHY_XMAC) {
1284 return(SK_HW_PS_NONE);
1285 }
1286 else {
1287 return(SkGePortCheckShorts(pAC, IoC, Port));
1288 }
1289 }
1290
1291 IsrcSum = pPrt->PIsave;
1292 pPrt->PIsave = 0;
1293
1294 /* Now wait for each port's link */
1295 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
1296 AutoNeg = SK_FALSE;
1297 }
1298 else {
1299 AutoNeg = SK_TRUE;
1300 }
1301
1302 if (pPrt->PLinkBroken) {
1303 /* Link was broken */
Wolfgang Denk2d6d9f02009-09-11 09:36:31 +0200[diff] [blame]1304 XM_IN32(IoC, Port, XM_GP_PORT, pGpReg);
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1305
1306 if ((GpReg & XM_GP_INP_ASS) == 0) {
1307 /* The Link is in sync */
1308 XM_IN16(IoC, Port, XM_ISRC, &Isrc);
1309 IsrcSum |= Isrc;
1310 SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1311
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1312 if ((Isrc & XM_IS_INP_ASS) == 0) {
1313 /* It has been in sync since last time */
1314 /* Restart the PORT */
1315 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1316 ("Link in sync Restart Port %d\n", Port));
1317
1318 (void)SkXmUpdateStats(pAC, IoC, Port);
1319
1320 /* We now need to reinitialize the PrevShorts counter */
1321 (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXE_SHT_ERR, &Shorts);
1322 pPrt->PPrevShorts = Shorts;
1323
1324 pPrt->PLinkBroken = SK_FALSE;
1325
1326 /*
1327 * Link Restart Workaround:
1328 * it may be possible that the other Link side
1329 * restarts its link as well an we detect
1330 * another LinkBroken. To prevent this
1331 * happening we check for a maximum number
1332 * of consecutive restart. If those happens,
1333 * we do NOT restart the active link and
1334 * check whether the link is now o.k.
1335 */
1336 pPrt->PLinkResCt++;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1337
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1338 pPrt->PAutoNegTimeOut = 0;
1339
1340 if (pPrt->PLinkResCt < SK_MAX_LRESTART) {
1341 return(SK_HW_PS_RESTART);
1342 }
1343
1344 pPrt->PLinkResCt = 0;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1345
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1346 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1347 ("Do NOT restart on Port %d %x %x\n", Port, Isrc, IsrcSum));
1348 }
1349 else {
1350 pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1351
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1352 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1353 ("Save Sync/nosync Port %d %x %x\n", Port, Isrc, IsrcSum));
1354
1355 /* Do nothing more if link is broken */
1356 return(SK_HW_PS_NONE);
1357 }
1358 }
1359 else {
1360 /* Do nothing more if link is broken */
1361 return(SK_HW_PS_NONE);
1362 }
1363
1364 }
1365 else {
1366 /* Link was not broken, check if it is */
1367 XM_IN16(IoC, Port, XM_ISRC, &Isrc);
1368 IsrcSum |= Isrc;
1369 if ((Isrc & XM_IS_INP_ASS) != 0) {
1370 XM_IN16(IoC, Port, XM_ISRC, &Isrc);
1371 IsrcSum |= Isrc;
1372 if ((Isrc & XM_IS_INP_ASS) != 0) {
1373 XM_IN16(IoC, Port, XM_ISRC, &Isrc);
1374 IsrcSum |= Isrc;
1375 if ((Isrc & XM_IS_INP_ASS) != 0) {
1376 pPrt->PLinkBroken = SK_TRUE;
1377 /* Re-Init Link partner Autoneg flag */
1378 pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
1379 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1380 ("Link broken Port %d\n", Port));
1381
1382 /* Cable removed-> reinit sense mode */
1383 SkHWInitDefSense(pAC, IoC, Port);
1384
1385 return(SK_HW_PS_RESTART);
1386 }
1387 }
1388 }
1389 else {
1390 SkXmAutoNegLipaXmac(pAC, IoC, Port, Isrc);
1391 if (SkGePortCheckShorts(pAC, IoC, Port) == SK_HW_PS_RESTART) {
1392 return(SK_HW_PS_RESTART);
1393 }
1394 }
1395 }
1396
1397 /*
1398 * here we usually can check whether the link is in sync and
1399 * auto-negotiation is done.
1400 */
Wolfgang Denk2d6d9f02009-09-11 09:36:31 +0200[diff] [blame]1401 XM_IN32(IoC, Port, XM_GP_PORT, pGpReg);
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1402 XM_IN16(IoC, Port, XM_ISRC, &Isrc);
1403 IsrcSum |= Isrc;
1404
1405 SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1406
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1407 if ((GpReg & XM_GP_INP_ASS) != 0 || (IsrcSum & XM_IS_INP_ASS) != 0) {
1408 if ((GpReg & XM_GP_INP_ASS) == 0) {
1409 /* Save Auto-negotiation Done interrupt only if link is in sync */
1410 pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND);
1411 }
1412#ifdef DEBUG
1413 if ((pPrt->PIsave & XM_IS_AND) != 0) {
1414 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1415 ("AutoNeg done rescheduled Port %d\n", Port));
1416 }
1417#endif /* DEBUG */
1418 return(SK_HW_PS_NONE);
1419 }
1420
1421 if (AutoNeg) {
1422 if ((IsrcSum & XM_IS_AND) != 0) {
1423 SkHWLinkUp(pAC, IoC, Port);
1424 Done = SkMacAutoNegDone(pAC, IoC, Port);
1425 if (Done != SK_AND_OK) {
1426 /* Get PHY parameters, for debugging only */
1427 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LpAb);
1428 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
1429 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1430 ("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n",
1431 Port, LpAb, ResAb));
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1432
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1433 /* Try next possible mode */
1434 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
1435 SkHWLinkDown(pAC, IoC, Port);
1436 if (Done == SK_AND_DUP_CAP) {
1437 /* GoTo next mode */
1438 SkHWSenseSetNext(pAC, IoC, Port, NextMode);
1439 }
1440
1441 return(SK_HW_PS_RESTART);
1442 }
1443 /*
1444 * Dummy Read extended status to prevent extra link down/ups
1445 * (clear Page Received bit if set)
1446 */
1447 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_EXP, &ExtStat);
1448 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1449 ("AutoNeg done Port %d\n", Port));
1450 return(SK_HW_PS_LINK);
1451 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1452
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1453 /* AutoNeg not done, but HW link is up. Check for timeouts */
1454 pPrt->PAutoNegTimeOut++;
1455 if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
1456 /* Increase the Timeout counter */
1457 pPrt->PAutoNegTOCt++;
1458
1459 /* Timeout occured */
1460 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1461 ("AutoNeg timeout Port %d\n", Port));
1462 if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
1463 pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
1464 /* Set Link manually up */
1465 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
1466 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1467 ("Set manual full duplex Port %d\n", Port));
1468 }
1469
1470 if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
1471 pPrt->PLipaAutoNeg == SK_LIPA_AUTO &&
1472 pPrt->PAutoNegTOCt >= SK_MAX_ANEG_TO) {
1473 /*
1474 * This is rather complicated.
1475 * we need to check here whether the LIPA_AUTO
1476 * we saw before is false alert. We saw at one
1477 * switch ( SR8800) that on boot time it sends
1478 * just one auto-neg packet and does no further
1479 * auto-negotiation.
1480 * Solution: we restart the autosensing after
1481 * a few timeouts.
1482 */
1483 pPrt->PAutoNegTOCt = 0;
1484 pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
1485 SkHWInitDefSense(pAC, IoC, Port);
1486 }
1487
1488 /* Do the restart */
1489 return(SK_HW_PS_RESTART);
1490 }
1491 }
1492 else {
1493 /* Link is up and we don't need more */
1494#ifdef DEBUG
1495 if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
1496 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1497 ("ERROR: Lipa auto detected on port %d\n", Port));
1498 }
1499#endif /* DEBUG */
1500 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1501 ("Link sync(GP), Port %d\n", Port));
1502 SkHWLinkUp(pAC, IoC, Port);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1503
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1504 /*
1505 * Link sync (GP) and so assume a good connection. But if not received
1506 * a bunch of frames received in a time slot (maybe broken tx cable)
1507 * the port is restart.
1508 */
1509 return(SK_HW_PS_LINK);
1510 }
1511
1512 return(SK_HW_PS_NONE);
1513} /* SkGePortCheckUpXmac */
1514
1515
1516/******************************************************************************
1517 *
1518 * SkGePortCheckUpBcom() - Check if the link is up on Bcom PHY
1519 *
1520 * return:
1521 * 0 o.k. nothing needed
1522 * 1 Restart needed on this port
1523 * 2 Link came up
1524 */
1525static int SkGePortCheckUpBcom(
1526SK_AC *pAC, /* Adapter Context */
1527SK_IOC IoC, /* IO Context */
1528int Port) /* Which port should be checked */
1529{
1530 SK_GEPORT *pPrt; /* GIni Port struct pointer */
1531 int Done;
1532 SK_U16 Isrc; /* Interrupt source register */
1533 SK_U16 PhyStat; /* Phy Status Register */
1534 SK_U16 ResAb; /* Master/Slave resolution */
1535 SK_U16 Ctrl; /* Broadcom control flags */
1536#ifdef DEBUG
1537 SK_U16 LpAb;
1538 SK_U16 ExtStat;
1539#endif /* DEBUG */
1540 SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */
1541
1542 pPrt = &pAC->GIni.GP[Port];
1543
1544 /* Check for No HCD Link events (#10523) */
1545 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &Isrc);
1546
1547#ifdef xDEBUG
1548 if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT) ==
1549 (PHY_B_IS_SCR_S_ER | PHY_B_IS_RRS_CHANGE | PHY_B_IS_LRS_CHANGE)) {
1550
1551 SK_U32 Stat1, Stat2, Stat3;
1552
1553 Stat1 = 0;
1554 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
1555 CMSMPrintString(
1556 pAC->pConfigTable,
1557 MSG_TYPE_RUNTIME_INFO,
1558 "CheckUp1 - Stat: %x, Mask: %x",
1559 (void *)Isrc,
1560 (void *)Stat1);
1561
1562 Stat1 = 0;
1563 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
1564 Stat2 = 0;
1565 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &Stat2);
1566 Stat1 = Stat1 << 16 | Stat2;
1567 Stat2 = 0;
1568 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
1569 Stat3 = 0;
1570 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
1571 Stat2 = Stat2 << 16 | Stat3;
1572 CMSMPrintString(
1573 pAC->pConfigTable,
1574 MSG_TYPE_RUNTIME_INFO,
1575 "Ctrl/Stat: %x, AN Adv/LP: %x",
1576 (void *)Stat1,
1577 (void *)Stat2);
1578
1579 Stat1 = 0;
1580 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
1581 Stat2 = 0;
1582 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
1583 Stat1 = Stat1 << 16 | Stat2;
1584 Stat2 = 0;
1585 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
1586 Stat3 = 0;
1587 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &Stat3);
1588 Stat2 = Stat2 << 16 | Stat3;
1589 CMSMPrintString(
1590 pAC->pConfigTable,
1591 MSG_TYPE_RUNTIME_INFO,
1592 "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
1593 (void *)Stat1,
1594 (void *)Stat2);
1595
1596 Stat1 = 0;
1597 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
1598 Stat2 = 0;
1599 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
1600 Stat1 = Stat1 << 16 | Stat2;
1601 Stat2 = 0;
1602 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
1603 Stat3 = 0;
1604 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
1605 Stat2 = Stat2 << 16 | Stat3;
1606 CMSMPrintString(
1607 pAC->pConfigTable,
1608 MSG_TYPE_RUNTIME_INFO,
1609 "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
1610 (void *)Stat1,
1611 (void *)Stat2);
1612 }
1613#endif /* DEBUG */
1614
1615 if ((Isrc & (PHY_B_IS_NO_HDCL /* | PHY_B_IS_NO_HDC */)) != 0) {
1616 /*
1617 * Workaround BCom Errata:
1618 * enable and disable loopback mode if "NO HCD" occurs.
1619 */
1620 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Ctrl);
1621 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL,
1622 (SK_U16)(Ctrl | PHY_CT_LOOP));
1623 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL,
1624 (SK_U16)(Ctrl & ~PHY_CT_LOOP));
1625 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1626 ("No HCD Link event, Port %d\n", Port));
1627#ifdef xDEBUG
1628 CMSMPrintString(
1629 pAC->pConfigTable,
1630 MSG_TYPE_RUNTIME_INFO,
1631 "No HCD link event, port %d.",
1632 (void *)Port,
1633 (void *)NULL);
1634#endif /* DEBUG */
1635 }
1636
1637 /* Not obsolete: link status bit is latched to 0 and autoclearing! */
1638 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
1639
1640 if (pPrt->PHWLinkUp) {
1641 return(SK_HW_PS_NONE);
1642 }
1643
1644#ifdef xDEBUG
1645 {
1646 SK_U32 Stat1, Stat2, Stat3;
1647
1648 Stat1 = 0;
1649 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
1650 CMSMPrintString(
1651 pAC->pConfigTable,
1652 MSG_TYPE_RUNTIME_INFO,
1653 "CheckUp1a - Stat: %x, Mask: %x",
1654 (void *)Isrc,
1655 (void *)Stat1);
1656
1657 Stat1 = 0;
1658 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
1659 Stat2 = 0;
1660 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
1661 Stat1 = Stat1 << 16 | PhyStat;
1662 Stat2 = 0;
1663 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
1664 Stat3 = 0;
1665 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
1666 Stat2 = Stat2 << 16 | Stat3;
1667 CMSMPrintString(
1668 pAC->pConfigTable,
1669 MSG_TYPE_RUNTIME_INFO,
1670 "Ctrl/Stat: %x, AN Adv/LP: %x",
1671 (void *)Stat1,
1672 (void *)Stat2);
1673
1674 Stat1 = 0;
1675 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
1676 Stat2 = 0;
1677 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
1678 Stat1 = Stat1 << 16 | Stat2;
1679 Stat2 = 0;
1680 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
1681 Stat3 = 0;
1682 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
1683 Stat2 = Stat2 << 16 | ResAb;
1684 CMSMPrintString(
1685 pAC->pConfigTable,
1686 MSG_TYPE_RUNTIME_INFO,
1687 "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
1688 (void *)Stat1,
1689 (void *)Stat2);
1690
1691 Stat1 = 0;
1692 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
1693 Stat2 = 0;
1694 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
1695 Stat1 = Stat1 << 16 | Stat2;
1696 Stat2 = 0;
1697 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
1698 Stat3 = 0;
1699 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
1700 Stat2 = Stat2 << 16 | Stat3;
1701 CMSMPrintString(
1702 pAC->pConfigTable,
1703 MSG_TYPE_RUNTIME_INFO,
1704 "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
1705 (void *)Stat1,
1706 (void *)Stat2);
1707 }
1708#endif /* DEBUG */
1709
1710 /* Now wait for each port's link */
1711 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
1712 AutoNeg = SK_FALSE;
1713 }
1714 else {
1715 AutoNeg = SK_TRUE;
1716 }
1717
1718 /*
1719 * Here we usually can check whether the link is in sync and
1720 * auto-negotiation is done.
1721 */
1722
1723 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
1724
1725 SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1726
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1727 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1728 ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat));
1729
1730 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
1731
1732 if ((ResAb & PHY_B_1000S_MSF) != 0) {
1733 /* Error */
1734 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1735 ("Master/Slave Fault port %d\n", Port));
1736 pPrt->PAutoNegFail = SK_TRUE;
1737 pPrt->PMSStatus = SK_MS_STAT_FAULT;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1738
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1739 return(SK_HW_PS_RESTART);
1740 }
1741
1742 if ((PhyStat & PHY_ST_LSYNC) == 0) {
1743 return(SK_HW_PS_NONE);
1744 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1745
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1746 pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
1747 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1748
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1749 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1750 ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat));
1751
1752 if (AutoNeg) {
1753 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
1754 SkHWLinkUp(pAC, IoC, Port);
1755 Done = SkMacAutoNegDone(pAC, IoC, Port);
1756 if (Done != SK_AND_OK) {
1757#ifdef DEBUG
1758 /* Get PHY parameters, for debugging only */
1759 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LpAb);
1760 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ExtStat);
1761 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1762 ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
1763 Port, LpAb, ExtStat));
1764#endif /* DEBUG */
1765 return(SK_HW_PS_RESTART);
1766 }
1767 else {
1768#ifdef xDEBUG
1769 /* Dummy read ISR to prevent extra link downs/ups */
1770 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
1771
1772 if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
1773 CMSMPrintString(
1774 pAC->pConfigTable,
1775 MSG_TYPE_RUNTIME_INFO,
1776 "CheckUp2 - Stat: %x",
1777 (void *)ExtStat,
1778 (void *)NULL);
1779 }
1780#endif /* DEBUG */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1781
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1782 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1783 ("AutoNeg done Port %d\n", Port));
1784 return(SK_HW_PS_LINK);
1785 }
1786 }
1787 }
1788 else { /* !AutoNeg */
1789 /* Link is up and we don't need more. */
1790#ifdef DEBUG
1791 if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
1792 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1793 ("ERROR: Lipa auto detected on port %d\n", Port));
1794 }
1795#endif /* DEBUG */
1796
1797#ifdef xDEBUG
1798 /* Dummy read ISR to prevent extra link downs/ups */
1799 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
1800
1801 if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
1802 CMSMPrintString(
1803 pAC->pConfigTable,
1804 MSG_TYPE_RUNTIME_INFO,
1805 "CheckUp3 - Stat: %x",
1806 (void *)ExtStat,
1807 (void *)NULL);
1808 }
1809#endif /* DEBUG */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1810
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1811 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1812 ("Link sync(GP), Port %d\n", Port));
1813 SkHWLinkUp(pAC, IoC, Port);
1814 return(SK_HW_PS_LINK);
1815 }
1816
1817 return(SK_HW_PS_NONE);
1818} /* SkGePortCheckUpBcom */
1819
1820
1821/******************************************************************************
1822 *
1823 * SkGePortCheckUpGmac() - Check if the link is up on Marvell PHY
1824 *
1825 * return:
1826 * 0 o.k. nothing needed
1827 * 1 Restart needed on this port
1828 * 2 Link came up
1829 */
1830static int SkGePortCheckUpGmac(
1831SK_AC *pAC, /* Adapter Context */
1832SK_IOC IoC, /* IO Context */
1833int Port) /* Which port should be checked */
1834{
1835 SK_GEPORT *pPrt; /* GIni Port struct pointer */
1836 int Done;
1837 SK_U16 Isrc; /* Interrupt source */
1838 SK_U16 PhyStat; /* Phy Status */
1839 SK_U16 PhySpecStat;/* Phy Specific Status */
1840 SK_U16 ResAb; /* Master/Slave resolution */
1841 SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */
1842
1843 pPrt = &pAC->GIni.GP[Port];
1844
1845 /* Read PHY Interrupt Status */
1846 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &Isrc);
1847
1848 if ((Isrc & PHY_M_IS_AN_COMPL) != 0) {
1849 /* TBD */
1850 }
1851
1852 if ((Isrc & PHY_M_IS_DOWNSH_DET) != 0) {
1853 /* TBD */
1854 }
1855
1856 if (pPrt->PHWLinkUp) {
1857 return(SK_HW_PS_NONE);
1858 }
1859
1860 /* Now wait for each port's link */
1861 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
1862 AutoNeg = SK_FALSE;
1863 }
1864 else {
1865 AutoNeg = SK_TRUE;
1866 }
1867
1868 /* Read PHY Status */
1869 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat);
1870
1871 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1872 ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat));
1873
1874 SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1875
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1876 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
1877
1878 if ((ResAb & PHY_B_1000S_MSF) != 0) {
1879 /* Error */
1880 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1881 ("Master/Slave Fault port %d\n", Port));
1882 pPrt->PAutoNegFail = SK_TRUE;
1883 pPrt->PMSStatus = SK_MS_STAT_FAULT;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1884
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1885 return(SK_HW_PS_RESTART);
1886 }
1887
1888 /* Read PHY Specific Status */
1889 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1890
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1891 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1892 ("AutoNeg: %d, PhySpecStat: 0x%04x\n", AutoNeg, PhySpecStat));
1893
1894 if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) {
1895 return(SK_HW_PS_NONE);
1896 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1897
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1898 pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
1899 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1900
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1901 pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1902
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1903 if (AutoNeg) {
1904 /* Auto-Negotiation Over ? */
1905 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1906
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1907 SkHWLinkUp(pAC, IoC, Port);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1908
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1909 Done = SkMacAutoNegDone(pAC, IoC, Port);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1910
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1911 if (Done != SK_AND_OK) {
1912 return(SK_HW_PS_RESTART);
1913 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1914
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1915 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1916 ("AutoNeg done Port %d\n", Port));
1917 return(SK_HW_PS_LINK);
1918 }
1919 }
1920 else { /* !AutoNeg */
1921 /* Link is up and we don't need more */
1922#ifdef DEBUG
1923 if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
1924 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1925 ("ERROR: Lipa auto detected on port %d\n", Port));
1926 }
1927#endif /* DEBUG */
1928
1929 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
1930 ("Link sync, Port %d\n", Port));
1931 SkHWLinkUp(pAC, IoC, Port);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1932
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1933 return(SK_HW_PS_LINK);
1934 }
1935
1936 return(SK_HW_PS_NONE);
1937} /* SkGePortCheckUpGmac */
1938
1939
1940#ifdef OTHER_PHY
1941/******************************************************************************
1942 *
1943 * SkGePortCheckUpLone() - Check if the link is up on Level One PHY
1944 *
1945 * return:
1946 * 0 o.k. nothing needed
1947 * 1 Restart needed on this port
1948 * 2 Link came up
1949 */
1950static int SkGePortCheckUpLone(
1951SK_AC *pAC, /* Adapter Context */
1952SK_IOC IoC, /* IO Context */
1953int Port) /* Which port should be checked */
1954{
1955 SK_GEPORT *pPrt; /* GIni Port struct pointer */
1956 int Done;
1957 SK_U16 Isrc; /* Interrupt source register */
1958 SK_U16 LpAb; /* Link Partner Ability */
1959 SK_U16 ExtStat; /* Extended Status Register */
1960 SK_U16 PhyStat; /* Phy Status Register */
1961 SK_U16 StatSum;
1962 SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */
1963 SK_U8 NextMode; /* Next AutoSensing Mode */
1964
1965 pPrt = &pAC->GIni.GP[Port];
1966
1967 if (pPrt->PHWLinkUp) {
1968 return(SK_HW_PS_NONE);
1969 }
1970
1971 StatSum = pPrt->PIsave;
1972 pPrt->PIsave = 0;
1973
1974 /* Now wait for each ports link */
1975 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
1976 AutoNeg = SK_FALSE;
1977 }
1978 else {
1979 AutoNeg = SK_TRUE;
1980 }
1981
1982 /*
1983 * here we usually can check whether the link is in sync and
1984 * auto-negotiation is done.
1985 */
1986 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_STAT, &PhyStat);
1987 StatSum |= PhyStat;
1988
1989 SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1990
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1991 if ((PhyStat & PHY_ST_LSYNC) == 0) {
1992 /* Save Auto-negotiation Done bit */
1993 pPrt->PIsave = (SK_U16)(StatSum & PHY_ST_AN_OVER);
1994#ifdef DEBUG
1995 if ((pPrt->PIsave & PHY_ST_AN_OVER) != 0) {
1996 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
1997 ("AutoNeg done rescheduled Port %d\n", Port));
1998 }
1999#endif /* DEBUG */
2000 return(SK_HW_PS_NONE);
2001 }
2002
2003 if (AutoNeg) {
2004 if ((StatSum & PHY_ST_AN_OVER) != 0) {
2005 SkHWLinkUp(pAC, IoC, Port);
2006 Done = SkMacAutoNegDone(pAC, IoC, Port);
2007 if (Done != SK_AND_OK) {
2008 /* Get PHY parameters, for debugging only */
2009 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LpAb);
2010 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ExtStat);
2011 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
2012 ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
2013 Port, LpAb, ExtStat));
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2014
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2015 /* Try next possible mode */
2016 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
2017 SkHWLinkDown(pAC, IoC, Port);
2018 if (Done == SK_AND_DUP_CAP) {
2019 /* GoTo next mode */
2020 SkHWSenseSetNext(pAC, IoC, Port, NextMode);
2021 }
2022
2023 return(SK_HW_PS_RESTART);
2024
2025 }
2026 else {
2027 /*
2028 * Dummy Read interrupt status to prevent
2029 * extra link down/ups
2030 */
2031 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat);
2032 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
2033 ("AutoNeg done Port %d\n", Port));
2034 return(SK_HW_PS_LINK);
2035 }
2036 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2037
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2038 /* AutoNeg not done, but HW link is up. Check for timeouts */
2039 pPrt->PAutoNegTimeOut++;
2040 if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
2041 /* Timeout occured */
2042 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
2043 ("AutoNeg timeout Port %d\n", Port));
2044 if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
2045 pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
2046 /* Set Link manually up */
2047 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
2048 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
2049 ("Set manual full duplex Port %d\n", Port));
2050 }
2051
2052 /* Do the restart */
2053 return(SK_HW_PS_RESTART);
2054 }
2055 }
2056 else {
2057 /* Link is up and we don't need more */
2058#ifdef DEBUG
2059 if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
2060 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
2061 ("ERROR: Lipa auto detected on port %d\n", Port));
2062 }
2063#endif /* DEBUG */
2064
2065 /*
2066 * Dummy Read interrupt status to prevent
2067 * extra link down/ups
2068 */
2069 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2070
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2071 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
2072 ("Link sync(GP), Port %d\n", Port));
2073 SkHWLinkUp(pAC, IoC, Port);
2074 return(SK_HW_PS_LINK);
2075 }
2076
2077 return(SK_HW_PS_NONE);
2078} /* SkGePortCheckUpLone */
2079
2080
2081/******************************************************************************
2082 *
2083 * SkGePortCheckUpNat() - Check if the link is up on National PHY
2084 *
2085 * return:
2086 * 0 o.k. nothing needed
2087 * 1 Restart needed on this port
2088 * 2 Link came up
2089 */
2090static int SkGePortCheckUpNat(
2091SK_AC *pAC, /* Adapter Context */
2092SK_IOC IoC, /* IO Context */
2093int Port) /* Which port should be checked */
2094{
2095 /* todo: National */
2096 return(SK_HW_PS_NONE);
2097} /* SkGePortCheckUpNat */
2098#endif /* OTHER_PHY */
2099
2100
2101/******************************************************************************
2102 *
2103 * SkGeSirqEvent() - Event Service Routine
2104 *
2105 * Description:
2106 *
2107 * Notes:
2108 */
2109int SkGeSirqEvent(
2110SK_AC *pAC, /* Adapter Context */
2111SK_IOC IoC, /* Io Context */
2112SK_U32 Event, /* Module specific Event */
2113SK_EVPARA Para) /* Event specific Parameter */
2114{
2115 SK_U64 Octets;
2116 SK_GEPORT *pPrt; /* GIni Port struct pointer */
2117 SK_U32 Port;
2118 SK_U32 Time;
2119 unsigned Len;
2120 int PortStat;
2121 SK_U8 Val8;
2122
2123 Port = Para.Para32[0];
2124 pPrt = &pAC->GIni.GP[Port];
2125
2126 switch (Event) {
2127 case SK_HWEV_WATIM:
2128 /* Check whether port came up */
2129 PortStat = SkGePortCheckUp(pAC, IoC, Port);
2130
2131 switch (PortStat) {
2132 case SK_HW_PS_RESTART:
2133 if (pPrt->PHWLinkUp) {
2134 /*
2135 * Set Link to down.
2136 */
2137 SkHWLinkDown(pAC, IoC, Port);
2138
2139 /*
2140 * Signal directly to RLMT to ensure correct
2141 * sequence of SWITCH and RESET event.
2142 */
2143 SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
2144 }
2145
2146 /* Restart needed */
2147 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
2148 break;
2149
2150 case SK_HW_PS_LINK:
2151 /* Signal to RLMT */
2152 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para);
2153 break;
2154
2155 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2156
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2157 /* Start again the check Timer */
2158 if (pPrt->PHWLinkUp) {
2159 Time = SK_WA_ACT_TIME;
2160 }
2161 else {
2162 Time = SK_WA_INA_TIME;
2163 }
2164
2165 /* Todo: still needed for non-XMAC PHYs??? */
2166 /* Start workaround Errata #2 timer */
2167 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Time,
2168 SKGE_HWAC, SK_HWEV_WATIM, Para);
2169 break;
2170
2171 case SK_HWEV_PORT_START:
2172 if (pPrt->PHWLinkUp) {
2173 /*
2174 * Signal directly to RLMT to ensure correct
2175 * sequence of SWITCH and RESET event.
2176 */
2177 SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
2178 }
2179
2180 SkHWLinkDown(pAC, IoC, Port);
2181
2182 /* Schedule Port RESET */
2183 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
2184
2185 /* Start workaround Errata #2 timer */
2186 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME,
2187 SKGE_HWAC, SK_HWEV_WATIM, Para);
2188 break;
2189
2190 case SK_HWEV_PORT_STOP:
2191 if (pPrt->PHWLinkUp) {
2192 /*
2193 * Signal directly to RLMT to ensure correct
2194 * sequence of SWITCH and RESET event.
2195 */
2196 SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
2197 }
2198
2199 /* Stop Workaround Timer */
2200 SkTimerStop(pAC, IoC, &pPrt->PWaTimer);
2201
2202 SkHWLinkDown(pAC, IoC, Port);
2203 break;
2204
2205 case SK_HWEV_UPDATE_STAT:
2206 /* We do NOT need to update any statistics */
2207 break;
2208
2209 case SK_HWEV_CLEAR_STAT:
2210 /* We do NOT need to clear any statistics */
2211 for (Port = 0; Port < (SK_U32)pAC->GIni.GIMacsFound; Port++) {
2212 pPrt->PPrevRx = 0;
2213 pPrt->PPrevFcs = 0;
2214 pPrt->PPrevShorts = 0;
2215 }
2216 break;
2217
2218 case SK_HWEV_SET_LMODE:
2219 Val8 = (SK_U8)Para.Para32[1];
2220 if (pPrt->PLinkModeConf != Val8) {
2221 /* Set New link mode */
2222 pPrt->PLinkModeConf = Val8;
2223
2224 /* Restart Port */
2225 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
2226 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
2227 }
2228 break;
2229
2230 case SK_HWEV_SET_FLOWMODE:
2231 Val8 = (SK_U8)Para.Para32[1];
2232 if (pPrt->PFlowCtrlMode != Val8) {
2233 /* Set New Flow Control mode */
2234 pPrt->PFlowCtrlMode = Val8;
2235
2236 /* Restart Port */
2237 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
2238 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
2239 }
2240 break;
2241
2242 case SK_HWEV_SET_ROLE:
2243 /* not possible for fiber */
2244 if (!pAC->GIni.GICopperType) {
2245 break;
2246 }
2247 Val8 = (SK_U8)Para.Para32[1];
2248 if (pPrt->PMSMode != Val8) {
2249 /* Set New link mode */
2250 pPrt->PMSMode = Val8;
2251
2252 /* Restart Port */
2253 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
2254 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
2255 }
2256 break;
2257
2258 case SK_HWEV_SET_SPEED:
2259 if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
2260 break;
2261 }
2262 Val8 = (SK_U8)Para.Para32[1];
2263 if (pPrt->PLinkSpeed != Val8) {
2264 /* Set New Speed parameter */
2265 pPrt->PLinkSpeed = Val8;
2266
2267 /* Restart Port */
2268 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
2269 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
2270 }
2271 break;
2272
2273 case SK_HWEV_HALFDUP_CHK:
2274 /*
2275 * half duplex hangup workaround.
2276 * See packet arbiter timeout interrupt for description
2277 */
2278 pPrt->HalfDupTimerActive = SK_FALSE;
2279 if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF ||
2280 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) {
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2281
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2282 Len = sizeof(SK_U64);
2283 SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets,
2284 &Len, (SK_U32)SK_PNMI_PORT_PHYS2INST(pAC, Port),
2285 pAC->Rlmt.Port[Port].Net->NetNumber);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2286
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2287 if (pPrt->LastOctets == Octets) {
2288 /* Tx hanging, a FIFO flush restarts it */
2289 SkMacFlushTxFifo(pAC, IoC, Port);
2290 }
2291 }
2292 break;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2293
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2294 default:
2295 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG);
2296 break;
2297 }
2298
2299 return(0);
2300} /* SkGeSirqEvent */
2301
2302
2303/******************************************************************************
2304 *
2305 * SkPhyIsrBcom() - PHY interrupt service routine
2306 *
2307 * Description: handles all interrupts from BCom PHY
2308 *
2309 * Returns: N/A
2310 */
2311static void SkPhyIsrBcom(
2312SK_AC *pAC, /* Adapter Context */
2313SK_IOC IoC, /* Io Context */
2314int Port, /* Port Num = PHY Num */
2315SK_U16 IStatus) /* Interrupt Status */
2316{
2317 SK_GEPORT *pPrt; /* GIni Port struct pointer */
2318 SK_EVPARA Para;
2319
2320 pPrt = &pAC->GIni.GP[Port];
2321
2322 if ((IStatus & PHY_B_IS_PSE) != 0) {
2323 /* Incorrectable pair swap error */
2324 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E022,
2325 SKERR_SIRQ_E022MSG);
2326 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2327
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2328 if ((IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) != 0) {
2329 Para.Para32[0] = (SK_U32)Port;
2330
2331 SkHWLinkDown(pAC, IoC, Port);
2332
2333 /* Signal to RLMT */
2334 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
2335
2336 /* Start workaround Errata #2 timer */
2337 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME,
2338 SKGE_HWAC, SK_HWEV_WATIM, Para);
2339 }
2340
2341} /* SkPhyIsrBcom */
2342
2343
2344/******************************************************************************
2345 *
2346 * SkPhyIsrGmac() - PHY interrupt service routine
2347 *
2348 * Description: handles all interrupts from Marvell PHY
2349 *
2350 * Returns: N/A
2351 */
2352static void SkPhyIsrGmac(
2353SK_AC *pAC, /* Adapter Context */
2354SK_IOC IoC, /* Io Context */
2355int Port, /* Port Num = PHY Num */
2356SK_U16 IStatus) /* Interrupt Status */
2357{
2358 SK_GEPORT *pPrt; /* GIni Port struct pointer */
2359 SK_EVPARA Para;
2360
2361 pPrt = &pAC->GIni.GP[Port];
2362
2363 if ((IStatus & (PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE)) != 0) {
2364 Para.Para32[0] = (SK_U32)Port;
2365
2366 SkHWLinkDown(pAC, IoC, Port);
2367
2368 /* Signal to RLMT */
2369 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
2370 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2371
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2372 if ((IStatus & PHY_M_IS_AN_ERROR) != 0) {
2373 /* Auto-Negotiation Error */
2374 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
2375 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2376
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2377 if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) {
2378 /* TBD */
2379 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2380
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2381 if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) {
2382 /* FIFO Overflow/Underrun Error */
2383 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG);
2384 }
2385} /* SkPhyIsrGmac */
2386
2387
2388#ifdef OTHER_PHY
2389/******************************************************************************
2390 *
2391 * SkPhyIsrLone() - PHY interrupt service routine
2392 *
2393 * Description: handles all interrupts from LONE PHY
2394 *
2395 * Returns: N/A
2396 */
2397static void SkPhyIsrLone(
2398SK_AC *pAC, /* Adapter Context */
2399SK_IOC IoC, /* Io Context */
2400int Port, /* Port Num = PHY Num */
2401SK_U16 IStatus) /* Interrupt Status */
2402{
2403 SK_EVPARA Para;
2404
2405 if (IStatus & (PHY_L_IS_DUP | PHY_L_IS_ISOL)) {
2406 SkHWLinkDown(pAC, IoC, Port);
2407
2408 /* Signal to RLMT */
2409 Para.Para32[0] = (SK_U32)Port;
2410 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
2411 }
2412
2413} /* SkPhyIsrLone */
2414#endif /* OTHER_PHY */
2415
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2416/* End of File */